1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's
TM
Data Sheet
TMOS E-FET
.
TM
Power Field Effect Transistor
TO-247 with Isolated Mounting Hole
NChannel EnhancementMode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Isolated Mounting Hole Reduces Mounting Hardware
MAXIMUM RATINGS
(TC = 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
VDSS
600
Vdc
DrainGate Voltage (RGS = 1.0 M
)
VDGR
600
Vdc
GateSource Voltage -- Continuous
GateSource Voltage
-- NonRepetitive (tp
10 ms)
VGS
VGSM
20
40
Vdc
Vpk
Drain Current -- Continuous
Drain Current
-- Continuous @ 100
C
Drain Current
-- Single Pulse (tp
10
s)
ID
ID
IDM
8.0
6.4
24
Adc
Apk
Total Power Dissipation
Derate above 25
C
PD
180
1.43
Watts
W/
C
Operating and Storage Temperature Range
TJ, Tstg
55 to 150
C
Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25
C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 24 Apk, L = 3.0 mH, RG = 25
)
EAS
864
mJ
Thermal Resistance -- Junction to Case
Thermal Resistance
-- Junction to Ambient
R
JC
R
JA
0.70
40
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
from case for 10 seconds
TL
260
C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
EFET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 4
Order this document
by MTW8N60E/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MTW8N60E
TMOS POWER FET
8.0 AMPERES
600 VOLTS
RDS(on) = 0.55 OHM
Motorola Preferred Device
D
S
G
CASE 340K01, Style 1
TO247AE
Motorola, Inc. 1996
MTW8N60E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250
Adc)
Temperature Coefficient (Positive)
V(BR)DSS
600
--
--
695
--
--
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125
C)
IDSS
--
--
--
--
10
100
Adc
GateBody Leakage Current (VGS =
20 Vdc, VDS = 0)
IGSS
--
--
100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
Adc)
Temperature Coefficient (Negative)
VGS(th)
2.0
--
3.0
7.0
4.0
--
Vdc
mV/
C
Static DrainSource OnResistance (VGS = 10 Vdc, ID = 4.0 Adc)
RDS(on)
--
0.46
0.55
Ohm
DrainSource OnVoltage (VGS = 10 Vdc)
(ID = 8.0 Adc)
(ID = 4.0 Adc, TJ = 125
C)
VDS(on)
--
--
3.2
--
4.8
4.6
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 4.0 Adc)
gFS
4.0
8.5
--
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
25 Vdc V
0 Vdc
Ciss
--
2480
3470
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
--
247
346
Reverse Transfer Capacitance
f = 1.0 MHz)
Crss
--
56
120
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
(V
300 Vd
I
8 0 Ad
td(on)
--
23.6
50
ns
Rise Time
(VDD = 300 Vdc, ID = 8.0 Adc,
VGS = 10 Vdc
tr
--
37.6
70
TurnOff Delay Time
VGS = 10 Vdc,
RG = 9.1
)
td(off)
--
80
170
Fall Time
G
)
tf
--
48
95
Gate Charge
(See Figure 8)
(V
300 Vd
I
8 0 Ad
QT
--
67
100
nC
(VDS = 300 Vdc, ID = 8.0 Adc,
VGS = 10 Vdc)
Q1
--
17
--
VGS = 10 Vdc)
Q2
--
26
--
Q3
--
27
--
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage (1)
(IS = 8.0 Adc, VGS = 0 Vdc)
(IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125
C)
VSD
--
--
0.829
0.71
1.1
--
Vdc
Reverse Recovery Time
(See Figure 14)
(I
8 0 Ad
V
0 Vd
trr
--
381
--
ns
(See Figure 14)
(IS = 8.0 Adc, VGS = 0 Vdc,
ta
--
225
--
( S
,
GS
,
dIS/dt = 100 A/
s)
tb
--
156
--
Reverse Recovery Stored Charge
QRR
--
4.61
--
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
from package to center of die)
LD
--
4.5
--
nH
Internal Source Inductance
(Measured from the source lead 0.25
from package to source bond pad)
LS
--
13
--
nH
(1) Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
(2) Switching characteristics are independent of operating junction temperature.
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