PREL

IMINAR

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

33982 Simplified Application Diagram

This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.

Document order number MC33982/D

Rev 4, 2/2003

33982

Preliminary Information

Intelligent High Current Self-
Protected Silicon High-Side Single
Switch

The 33982 is a self-protected silicon 2 m

high-side switch used to replace

electromechanical relays, fuses, and discrete devices in power management
applications. The 33982 is designed for harsh environments, and it includes
self-recovery features. The device is suitable for loads with high inrush current,
as well as motors and all types of resistive and inductive loads.

Programming, control, and diagnostics are implemented via the Serial

Peripheral Interface (SPI). A dedicated parallel input is available for alternate
and Pulse Width Modulation (PWM) control of the output. SPI programmable
fault trip thresholds allow the device to be adjusted for optimal performance in
the application.

The 33982 is packaged in a power enhanced 12 x 12 PQFN package with

exposed tabs.

Features

· Single 2.0 m

Max High-Side Switch with Parallel Input or SPI Control

· 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 µA
· Output Current Monitoring Output with two SPI Selectable Current

Ratios

· SPI Control of: Overcurrent Limit, Overcurrent Fault Blanking Time,

Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, slew rates and Fault Status Reporting

· SPI Status Reporting of: Overcurrent, Open and Shorted Loads, Over

Temperature, Under and Overvoltage Shutdown, Fail-Safe Pin Status,
and Program Status

· Enhanced 16 V Reverse Polarity V

PWR

Protection

FC SUFFIX

PLASTIC PACKAGE

CASE 1402

PQFN

INTELLIGENT SWITCH

2.0 m

ORDERING INFORMATION

Device

Temperature

Range (T

)

Package

PC33982FC/R2

- 40

C to 125

PQFN

MCU

33982

GND

PWRGND

LOAD

OUT

I/O

WAKE

SCLK

RST

CSNS

SCLK

I/O

A/D

GND

FSI

PWR

GND

10k

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

PIN FUNCTION DESCRIPTION

Pin

Pin Name

Description

CSNS

Output Current Monitoring. This pin is used to output a current proportional to the high-side output
current and used externally to generate a ground referenced voltage for the microcontroller to monitor
output current.

WAKE

WAKE. This pin is used to input a logic [1] signal so as to enable the Watchdog timer function. An internal
clamp protects this pin from high damaging voltages when the output is current limited with an external
resistor. This input has an internal passive pull-down.

RST

Reset. This is an input used to initialize the device configuration and fault registers, as well as place the
device in a low current sleep mode. The pin also starts the Watchdog timer when transitioning from logic
LOW-to-logic HIGH. This pin should not be allowed to be logic HIGH until V

is in regulation. This pin

has an internal passiv pull down.

Serial Input. The Input pin is used to directly control the output. This input has an internal active pull
down and requires CMOS logic levels. This input may be configured via SPI.

Fault Status. This is an open drain configured output requiring an external pull-up resistor to V

for fault

reporting. A device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are
reported via the SPI SO pin.

FSI

Fail-Safe Input. The level of this pin determines the state of the output after a Watchdog timeout occurs.
This pin incorporates and internal pull-up. If the FSI pin is left to float up to a logic [1] level, the output will
turn-ON when in the fail-safe state. When the FSI pin is connected to GND, the Watchdog circuit and fail-
safe operation are disabled.

Chip Select. This is an input pin connected to a chip select output of a system microcontroller. The
microcontroller determines which device is addressed (selected) to receive data by pulling the CS pin of
the selected device logic LOW, enabling SPI communication with the device. Other

unselected

devices

on the serial link having their CS pins pulled-up logic HIGH disregard the SPI communication data sent.

SCLK

Serial Clock. This is an input pin connected to the master microcontroller providing the required bit shift
clock for SPI communication. It transitions one time per bit transferred at an operating frequency, f

SPI

defined by the communication interface. See the SPI Interface Characteristics table. The 50 percent
duty cycle CMOS level serial clock signal is idle between command transfers. The signal is used to shift
data into and out-of the device. See operational description of SPI.

Serial Input. This is a command data input pin connected to the SPI Serial Data Output of the master
microcontroller or to the SO pin of the previous device of a daisy chain of devices. The input requires
CMOS logic level signals and incorporates an internal active pull-down. Device control is facilitated by
the input's receiving the MSB first of a serial 8-bit control command. The master ensures data is available
upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit
command into the internal command shift register.

SCLK

FSI

RST

WAKE

CSNS

OUT

PWR

OUT

GND

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Digital Drain Voltage (Power). This is an external voltage input pin used to supply power to the SPI
circuit. In the event V

is lost, an internal supply provides power to a portion of the logic, ensuring limited

functionality of the device.

Serial Output. This is an output pin connected to the SPI Serial Data Input pin of the master
microcontroller or to the SI pin of the next device of a daisy chain of devices. This output will remain tri-
stated (high impedance OFF condition) so long as the CS pin of the device is logic HIGH. SO is only
active when the CS pin of the device is asserted logic LOW. The generated SO output signals are CMOS
logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the
rising edge of SCLK. Serial output data provides status information for each bit assigned following an
MSB first-in-first-out protocol when the device is addressed. Fault bit assignments for return data follow
OD7 through OD0 are output status bits for message bits 7 through 0. See SPI operational details,
command verification, and daisy chain operation.

No Connect. This pin may not be connected.

GND

Ground. This pin is the ground for the logic and analog circuitry of the device.

PWR

Positive Power Supply. This pin connects to the positive power supply and is the source input of
operational power for the device. The V

PWR

pin is a backside surface mount tab of the package.

15 and 16

OUT

Output. Protected high-side power output to the load. All pins of output have to be connected in parallel
for operation according to this specification.

PIN FUNCTION DESCRIPTION

Pin

Pin Name

Description

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.

Rating

Symbol

Value

Unit

Operating Voltage Range

Steady-State

PWR(SS)

-16 to 41

Input Voltage (Note 1)

, RST, FSI

-0.3 to 7.0

WAKE Input Clamp Current

CL(WAKE)

2.5

CSNS Input Clamp Current

CL(CSNS)

2.5

Output Current (Note 2)

OUTt

Output Clamp Energy (Note 3)

TBD

Storage Temperature

STG

-55

to 150

Operating Junction Temperature

-40

to 150

Junction to Case Thermal Resistance

<1.0

C/W

Junction to Ambient Thermal Resistance

C/W

ESD Voltage

Human Body Model (Note 4)

Machine Model (Note 5)

ESD1

ESD2

2000

200

Notes:

Exceeding voltage limits on RST, IN, or FSI pins may cause a malfunction or permanent damage to the device.

Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required .

Active clamp energy using single pulse method.

SD1

testing is performed in accordance with the Human Body Model (C

ZAP

= 100 pF, R

ZAP

- 1500

SD2

testing is performed in accordance with the Machine Model (C

ZAP

= 200 pF, R

ZAP

- 0

)

and in accordance with the system module

specification with a capacitor > 0.01 µF connected form OUT to GND.

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V

5.5 V, 6 V

PWR

27 V, -40

150

C, unless otherwise noted. Typical

values noted reflect the approximate parameter mean at T

= 25

C under nominal conditions, unless otherwise noted.

Power Input

Characteristic

Symbol

Min

Typ

Max

Unit

Battery Supply Voltage Range

Full Operational

PWR

6.0

PWR

Operating Supply Current (Measured with Output ON, I

OUT

= 0)

PWR(on)

PWR

Supply Current

( Output OFF, Open Load Detect Disabled, WAKE > 0.7 V

RST = V

LOGIC HIGH

)

PWR(sby)

5.0

Sleep State Supply Current (

PWR

< 14 V, RST < 0.5 V, WAKE < 0.5 V)

= 25

= 85

PWR(sleep)

Supply Voltage

DD(on)

4.5

5.0

5.5

Supply Current

DD(on)

2.0

Sleep State Current

DD(sleep)

5.0

Over Voltage Shutdown

PWR(on)

Over Voltage Shutdown Hysteresis

PWR(ouhys)

0.2

0.8

1.5

Under Voltage Output Shutdown (Note 6)

P(uv)

5.0

5.5

6.0

Under Voltage Power-ON Reset

P(und)

5.0

Notes:

Output will automatically recover to instructed state when V

PWR

voltage is restored to normal so long as the V

PWR

degradation level did not

go below the under voltage power-on reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the
external Vdd supply is within specification.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V

5.5 V, 6 V

PWR

27 V, -40

150

C, unless otherwise noted. Typical

values noted reflect the approximate parameter mean at T

= 25

C under nominal conditions, unless otherwise noted.

Output

Characteristic

Symbol

Min

Typ

Max

Unit

Output Drain-to-Source ON Resistance

OUT

= 30 A,

= 25

PWR

= 6.0 V

PWR

= 9.0 V

PWR

= 13 V

DS(on)25

3.0

2.0

Output Drain-to-Source ON Resistance

(

OUT

= 30 A,

= 150

PWR

= 6.0 V

PWR

= 9.0 V

PWR

= 13 V

DS(on)150

5.1

3.4

Output Source-to-Drain ON Resistance (Note 7)

(

OUT

= 30 A,

= 25

PWR

= -12 V

SD(on)

4.0

Output Overcurrent High Detection Levels (9.0 V <

PWR

< 16 V)

SOCH = 0

SOCH = 1

OCH0

OCH1

120

150

100

180

120

Over current Low Detection Levels (SOCLA[2:0])

(000)

(001)

(010)

(011)

(100)

(101)

(110)

(111)

OCL0

OCL1

OCL2

OCL3

OCL4

OCL5

OCL6

OCL7

41
36
32
29
25
20
16
12

50
45
40
35
30
25
20
15

59
54
48
41
35
30
24
18

Current Sense Ratio (9.0 V < V

PWR

< 16 V CSNS < 4.5 V)

DICR D2 =0

DICR D2=1

CSR0

CSR1

1/40000

1/6000

Current Sense Ratio (C

SR0

) Accuracy

Output Current:

10 A

20 A

25 A

30 A

40 A

50 A

-20

-14

-13

-12

-13

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Current Sense Ratio (C

SR1

) Accuracy

Output Current:

10 A

20 A

25 A

30 A

40 A

50 A

TBD

Maximum Current Sense Clamp Voltage

CSNS

= 15 mA

CL(maxsns)

4.5

6.0

7.0

Open Load Detect Current (Note 8)

OLDC

100

Output Fault Detect Threshold

Output Programmed OFF

OLD(thres)

2.0

3.0

4.0

Output Negative Clamp Voltage

0.5A < =

OUT

< = 2.0 A, Output OFF

-20

Over Temperature Shutdown (Output OFF) (Note 9) (T

= 125

160

175

190

Over Temperature Shutdown Hysteresis (Note 9)

TSD

(hys)

5.0

Notes:

Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V

PWR

Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open
load condition when the specific output is commanded OFF.

Guaranteed by process monitor. Not production tested.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V

5.5 V, 6 V

PWR

27 V, -40

150

C, unless otherwise noted. Typical

values noted reflect the approximate parameter mean at T

= 25

C under nominal conditions, unless otherwise noted.

Control Interface

Characteristic

Symbol

Min

Typ

Max

Unit

Input Logic High Voltage (Note 10)

0.7V

Input Logic Low Voltage (Note 10)

0.2V

Input Logic Voltage Hysteresis (Note 10)

IN(hys)

100

350

750

Input Logic Pull-Down Current (SCLK, IN,SI)

DWN

5.0

RST Input Voltage Range

RST

4.5

5.0

5.5

SO, FS Tri-State Capacitance (Note 11)

Input Logic Pull-Down Resistor (RST) and WAKE

DWN

100

200

400

Input Capacitance (Note 12)

4.0

Wake Input Clamp Voltage (I

CL(WAKE)

<2.5 mA) (Note 13)

CL(WAKE)

7.0

Wake Input Forward Voltage (I

CL(WAKE)

= -2.5 mA)

F(WAKE)

-2.0

-0.3

SO High State Output Voltage (I

= 1.0 mA)

SOH

0.8 V

FS, SO Low State Output Voltage (I

= -1.6 mA)

SOL

0.2

0.4

SO Tri-State Leakage Current (CS > 0.7V

)

SO(leak)

-5.0

5.0

µA

Input Logic Pull-Up Current (CS, FSI, Vin >0.7 V

) (Note 14)

5.0

µA

Notes:

10.

Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN and WAKE input signals. The WAKE and RST signals may
be supplied by a derived voltage reference to V

PWR

11.

Parameter is guaranteed by process monitor but is not production tested.

12.

Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitor; but is not production tested.

13.

The current must be limited by a series resistance when using voltages > 7.0 V.

14.

Pull-up current is with CS OPEN. CS has an active internal pull-up to V

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V

5.5 V, 6 V

PWR

27 V, -40

150

C, unless otherwise noted. Typical

values noted reflect the approximate parameter mean at T

= 25

C under nominal conditions, unless otherwise noted.

Power Output Timing

Characteristic

Symbol

Min

Typ

Max

Unit

Output Rising Slow Slew Rate A (Note 15)

(DICR D3 = 0)

6 V< V

PWR

<9 V

9 V< V

PWR

<16 V

16 V< V

PWR

<27 V

rA_slow

0.6

V/µs

Output Rising Slow Slew Rate B (Note 17)

(DICR D3 = 0)

6 V< V

PWR

<9 V

9 V< V

PWR

<16 V

16 V< V

PWR

<27 V

RB_SLOW

0.05

V/µs

Output Rising Fast Slew Rate A (Note 15)

(DICR D3 = 1)

6 V< V

PWR

<9 V

9 V< V

PWR

<16 V

16 V< V

PWR

<27 V

RA_FAST

2.0

V/µs

Output Rising Fast Slew Rate B(Note 16)

(DICR D3 = 1)

6 V< V

PWR

<9 V

9 V< V

PWR

<16 V

16 V< V

PWR

<27 V

RB_FAST

0.2

V/µs

Output Falling Slow Slew Rate A (Note 15)

(DICR D3 = 0)

6 V< V

PWR

<9 V

9 V< V

PWR

<16 V

16 V< V

PWR

<27 V

RA_SLOW

0.6

V/µs

Output Falling Slow Slew Rate B (Note 16)

(DICR D3 = 0)

6 V< V

PWR

<9 V

9 V< V

PWR

<16 V

16 V< V

PWR

<27 V

RB_SLOW

0.05

V/µs

Output Falling Fast Slew Rate A (Note 15)

(DICR D3 = 1)

6 V< V

PWR

<9 V

9 V< V

PWR

<16 V

16 V< V

PWR

<27 V

RA_FAST

2.0

V/µs

Output Falling Fast Slew Rate B (Note 16)

(DICR D3=1)

6 V< V

PWR

<9 V

9 V< V

PWR

<16 V

16 V< V

PWR

<27 V

RB_FAST

0.2

V/µs

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

Output Turn-ON Delay Time (Note 17)

dly(on)

1.0

100

µs

Output Turn-OFF Delay Time (Note 18)

dly(off)

200

µs

Direct Input Switching Frequency

PWM

300

Over Current Detect Blank (OCTL [1:0]) Time

OCL0

OCL1

OCL2

OCL3

108

6.7

0.84

0.10

155

9.7

1.2

0.15

202

12.7

1.6

0.2

Over Current Hi Detect Blank Time

ILB

µs

CS to CSNS Valid Time

CNS

VAL

µs

Output Switching Delay Time (OSDR [2:0])

000

001

010

011

100

101

110

111

OSD0

OSD1

OSD2

OSD3

OSD4

OSD5

OSD6

44.8

89.6

134.4

179

224

268

313

128

192

256

320

384

448

83.2

166.4

250

333

416

500

583

Watchdog Timeout (Note 19) (WD[1:0])

WDTO0

WDTO1

WDTO2

WDTO3

496

248

2000

1000

620

310

2500

1250

806

403

3250

1625

Notes:

15.

Rise and Fall Slew Rates A measured across a 5.0

resistive load at HS output = 0.5V to V

PWR

-3 V. These parameters are guaranteed by

process monitoring.

16.

Rise and Fall Slow Slew Rates B measured across a 5.0

resistive load at HS output = 0.5V to V

PWR

-3 V. These parameters are guaranteed

by process monitoring.

17.

Turn-ON Delay time measured from rising edge of any signal (IN, SCLK, CS) that would turn the output ON to Vout=0.5V with RL=5 Ohm
resistive load.

18.

Turn-OFF delay time measured from falling edge of any signal (IN, SCLK, CS) that would turn the output OFF to Vout=VPWR-0.5V with RL=5
Ohm resistive load.

19.

Watchdog Timeout delay measured from the rising edge of WAKE to RST from a sleep state condition, to output turn-ON with the output
driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of t

is consistent for all configured watchdog

timeouts.

DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V

5.5 V, 6 V

PWR

27 V, -40

150

C, unless otherwise noted. Typical

values noted reflect the approximate parameter mean at T

= 25

C under nominal conditions, unless otherwise noted.

Power Output Timing

Characteristic

Symbol

Min

Typ

Max

Unit

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 2. Output Slew Rate and Time Delays

SPI INTERFACE CHARACTERISTICS

Characteristics noted under conditions 4.5 V

5.5 V, 6 V

PWR

27 V, -40

150

C, unless otherwise noted. Typical

values noted reflect the approximate parameter mean at T

= 25

C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Recommended Frequency of SPI Operation

SPI

3.0

MHz

Required Low State Duration for RST (Note 20)

WRST

167

Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 21)

300

Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 21)

ENBL

µS

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 21)

LEAD

167

Required High State Duration of SCLK (Required Setup Time) (Note 21)

WSCLKh

167

Required Low State Duration of SCLK (Required Setup Time) (Note 21)

WSCLKl

167

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 21)

LAG

167

SI to Falling Edge of SCLK (Required Setup Time) (Note 22)

SI(SU)

Falling Edge of SCLK to SI (Required Setup Time) (Note 22)

SI(HOLD)

SO Rise Time (CL = 200 pF)

RSO

SO Fall Time (CL = 200 pF)

fSO

SI, CS, SCLK, Incoming Signal Rise Time (Note 22)

RSI

SI, CS, SCLK, Incoming Signal Fall Time (Note 22)

RSI

Time from Falling Edge of CS to SO Low Impedance (Note 23)

SO(EN)

145

Time from Rising Edge of CS to SO High Impedance (Note 24)

SO(DIS)

145

Time from Rising Edge of SCLK to SO Data Valid (Note 25)

0.2 V

< = SO > = 0.8 V

, CL = 200 pF

VALID

105

Notes:

20.

RST low duration measured with outputs enabled and going to OFF or disabled condition.

21.

Maximum setup time required for the 33982 is the minimum guaranteed time needed from the micro.

22.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

23.

Time required for output status data to be available for use at SO. 1 k

on pull-up on CS.

24.

Time required for output status data to be terminated at SO. 1 k

on pull-up on CS.

25.

Time required to obtain valid data out from SO following the rise of SCLK.

VPWR

VPWR - 0.5V

VPWR - 3V

0.5V

Tdly(off)

SRrA

SRrB

SRfA

SRfB

Tdly

(on)

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

SYSTEM APPLICATION INFORMATION

INTRODUCTION

SPI Protocol Description

The SPI interface has a full duplex, three-wire synchronous

data transfer with four I/O lines associated with it:

· SI
· SO
· SCLK
· CS

The SI/SO pins of the 33982 device follows a first in-first out

(D7/D0) protocol with both input and output words transferring
the Most Significant Bit (MSB) first. All inputs are compatible
with 5.0 V CMOS logic levels.

The SPI lines perform the following functions:

Serial Clock

Serial clocks (SCLK) the internal Shift registers of the 33982

device. The Serial Input (SI) pin accepts data into the input shift
register on the falling edge of the SCLK signal while the serial
output pin (SO) shifts data information out of the SO line driver
on the rising edge of the SCLK signal. It is important the SCLK
pin be in a logic Low state whenever CS makes any transition.
For this reason, it is recommended the SCLK pin be in a logic[0]
whenever the device is not accessed (CS logic [1] state). SCLK
has an internal pull down L

DWN

. When CS is logic [1], signals at

the SCLK and SI pins are ignored and SO is tri-stated (high
impedance). Please see the Data Transfer Timing diagram in

Table 7

and

Table 8

Serial Interface

This is a serial interface (SI) command data input pin. SI

instruction is read on the falling edge of SCLK. An 8-bit stream
of serial data is required on the SI pin, starting with D7 to D0.
The internal registers of the 33982 are configured and
controlled using a 4-bit adressing scheme, as shown in

Table 1

The SI input has an internal pull down L

DWN

Serial Output

The Serial Output (SO) data pin is a tri-stateable output from

the shift register. The SO pin remains in a high impedance state
until the CS pin is put into a logic[0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO pin
changes states on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and Input Status descriptions are
provided in

Table 11

Chip Select Overbar

The Chip Select pin enables communication with the Master

device. When this pin is in a logic[0] state, the device is capable
of transferring information to and receiving information from the
Master. The 33982 device latches-in data from the input shift
registers to the addressed registers on the rising edge of CS.
The device transfers status information from the power output
to the shift register on the falling edge of CS. The SO output
driver is enabled when CS is logic [0]. CS should transition from
a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS
has an internal pull-up, L

Figure 7. Single 8-Bit Word SPI Communication

CSB

SCLK

OD7

OD6

OD1

OD2

OD3

OD4

OD5

NOTES:

OD0

RSTB is in a logic 1 state during the above operation.

D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS

OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out
of the device.

C S B

S I

S C L K

D 7

D 1 *

D 2 *

D 5 *

D 6 *

D 7 *

D 0

D 1

D 6

D 5

D 2

D 0 *

O D 5

O D 6

O D 7

D 6

D 7

O D 0

O D 1

O D 2

D 1

D 2

D 5

N O T E S :

D 0

S O

1 .

R S T B

i s

i n

l o g i c

s t a t e

d u r i n g

t h e

a b o v e

o p e r a t i o n .

2 .

D 0 , D 1 , D 2 , . . . , a n d

D 7

r e l a t e

t o

t h e

m o s t r e c e n t o r d e r e d

e n t r y o f d a t a

i n t o

t h e

S P S S

3 .

O D 0 , O D 1 , O D 2 , . . . , a n d

O D 7

r e l a t e

t o

t h e

f i r s t 8

b i t s o f o r d e r e d

f a u l t a n d

s t a t u s

d a t a

o u t o f t h e

d e v i c e .

4 .

O D 0 , O D 1 , O D 2 , . . . , a n d

O D 7

r e p r e s e n t t h e

f i r s t 8

b i t s

o f o r d e r e d

f a u l t a n d

s t a t u s d a t a

o u t o f t h e

S P S S

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 8. Multiple 8-Bit Word SPI Communication

Serial Input Communication

SPI communication is accomplished using 8-bit messages. A

message is transmitted by the master starting with the MSB D7
and ending with the LSB D0. Each incoming command
message on the SI pin can be interpreted using the following bit
assignment : the MSB, D7, the watchdog bit (see

Table 1

)and

in some cases, a register address bit (see

Table 1

). The next

three bits, D6-D4, are used to select the command register. The
remaining four bits D3-D0 are used to configure and control the
output and its protection features.Multiple messages can be
transmitted in succession to accomodate those applications
where daisy chaining is desirable, or to confirm transmitted
data, as long as the messages are all mutliples of eight bits. Any
attempt made to latch in a message that is not eight bits will be
ignored.

The 33982 has eight registers defined (and one more for

internal use), which are used to configure the device and to
control the state of the output. The registers are addressed via
D6-D4 of the incoming SPI word (see

Table 1

Device Register Addressing

The nine possible register addresses (D7, D6, D5, D4) and a

description of their impact on the device operation are listed
below. Also see

Table 7

· Address x000-- Status Register (STATR).This register

is used to read the device status and the various
configuration register contents without disrupting the
device operation or the register contents. The register bits
D2, D1, D0 determine the content of the first eight bits of
SO data. In addition to the device status, this feature
provides the ability to read the content of the OCR,
SOCHLR, CDTOLR, DICR, OSDR, WDR and NAR
registers. See

SO Communication section on page 18.

· Address x001-- Output Control Register (OCR) allows

the master to control the output through the SPI. Incoming
message bit D0 reflects the desired states of the high-side
output; (IN_SPI); a logic [1] enables the output switch and
a logic [0] turns it OFF. A logic [1] on message bit D1
enables the Current Sense (CSNS_EN) pin. Bits D2 and
D3 must be logic [0] .Bit D7 is used to feed the watchdog,
if enabled.

· Address x010-- Select Over Current High and Low

Register (SOCHLR) allows the Master to configure the
output over current low and high detection levels,
respectively. In addition to protecting the device, this slow
blow fuse emulation feature can be used to optimize the
load requirements to match system characteristics. Bits
D2-D0 are used to set the over current low detection level
to one of eight possible levels are shown in

Table 2

. Bit D3

is used to set the over current high detection level to one
of two levels, outlined in

Table 3

· Address x011--Current Detect Time and Open Load

Register (CDTOLR) is used by the master to determine
the amount of time the device will allow an over current
low condition before output latches OFF occurs. Bits D1-
D0 allow the master to select one of four dead times
defined in

Table 4

. Note that these timeouts apply only to

the Over Current Low Detect levels. If the selected Over
Current High level is reached, the device will latch off
within 20

µs.

Table 1. SI Message Bit Assignment

Bit Sig SI Msg

Bit

Message Bit Description

MSB

Watchdog in: toggled to satisfy watchdog
requirements; also used as a Register address bit.

Used to configure the inputs, outputs, and the
device protection features and SO status content.

LSB

Used to configure the inputs, outputs, and the
device protection features and SO status content.

Table 2. Over Current Low Detection Levels

SOCLA2

(D2)

SOCLA1

(D1)

SCOLA0

(D0)

Over Current Low Detection

50 A

45 A

40 A

35 A

30 A

25 A

20 A

15 A

Table 3. Over Current High Detection Levels

SOCH (D3)

Over Current High Detection

150 A

100 A

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

A logic [1] on bit D2 disables the Over Current Low (CD dis)

Detection timeout feature. A logic [1] on bit D3 disables the
Open Load (OL) Detection feature.

· Address x100-- Direct Input Control Register (DICR)

is used by the master to enable, disable, or configure the
direct IN pin control of the output. A logic [0] on bits D1 will
enable the output for direct control with the IN pin; a logic
[1] on D1 bit will disable the output from direct control.
While addressing this register, if the Input was enable for
direct control, a logic [1] for the D0 bit will result in a
Boolean AND of the IN pin with its corresponding D0
message bit when addressing OCR. Similarly, a logic [0]
on the D0 pin will result in a Boolean OR of the IN pin to
the corresponding message bits when addressing the
OCR. This register is especially useful if several loads are
required to be independently PWM controlled. For
example, the IN pins of several devices can be configured
to operate all of the outputs with one PWM output from the
master. If each output is then configured to be Boolean
ANDed to its respective IN pin, each output can be
individually turned OFF by SPI while controlling all of the
outputs, commanded on with the single PWM output.
A logic [1] on bit D2 is used to select the high ratio (Iout/
40000) on the CSNS pin. The default value [0] is used to
select the low ratio(Iout/6000).
A logic [1] on bit D3 is used to select the high speed slew
rate, the default value [0] corresponds to the low speed
slew rate.

· Address 0101-- Output Switching Delay Register

(OSDR) is used to configure the device with a
programmable time delay that is active during Output On
transitions that are initiated via SPI or the direct input.
Whenever the input is commanded to transition from [0] to
[1], the output will be held OFF for the time delay
configured in the OSDR Register. The programming of the
contents of this register have no effect on device fail-safe
mode operation. The default value of the OSDR register is
000, equating to no delay, since the switching delay time
is 0ms. This feature allows the user a way to minimize
inrush currents, or surges, thereby allowing loads to be
synchronously switched ON with a single command.
There are eight selectable output switching delay times
that range from 0 to 448ms.

· Address 1101-- Watchdog Register (WDR) This

register is used by the master to configure the Watchdog
timeout. The Watchdog timeout is configured using bits
D1 and D0. When D1, D0 bits are programmed for the
desired watchdog timeout period, the WDSPI bit should
be toggled as well to ensure the new timeout period is
programmed at the beginning of a new count sequence.·
Bit D2 (WDTO) of the WDR register can be read to
determine the status of the watchdog circuitry. If WDTO bit
is [1], then the watchdog has timed out and the device is
in fail-safe mode. IF WDTO is [0] then the device is in
normal mode (assuming device is powered and not in
sleep mode), with the watchdog either enabled or
disabled.

· Address x110--No Action Register (NAR) can be used

to no-operation fill SPI data packets in a daisy-chain SPI
configuration. This would allow devices not to be affected
by commands being clocked over a daisy-chained SPI
configuration, and by toggling the WD bit (D7) the
watchdog circuitry would continue to be reset while no
programming or data read back functions are being
request from the device.

· Address x111--This register is reserved for test and is

not accessible with SPI during normal operation.

Table 4. Over Current Timing

OCTL[1:0]

Over Current Timing

155 ms

9.7 ms

1.2 ms

150 µs

Table 5. Switching Delay

OSDA[2:0] (D2, D1, D0)

Timing

000

0 ms

001

64 ms

010

128 ms

011

192 ms

100

256 ms

101

320 ms

110

384 ms

111

448 ms

Table 6. WatchDog Time Out

WDA[1:0] (D1, D0)

Timing

620 ms

310 ms

2500 ms

1250 ms

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Serial Output Communication (Device Status Return Data)

When the CS pin is pulled low, the output register is loaded

and the data is clocked out MSB (OD7) first, as the new
message data is clocked into the SI pin. The first eight bits of
data that clocks out of the SO, following a CS transition, is
dependant upon the previously written SPI word. Bit OD7
reflects the state of the watchdog bit (D7) that was addressed
during the prior communication. SO data will represent
information ranging from fault status to register contents as
chosen by the user by writing to the STATR bits D2,D1,D0 .
Note that the SO data will continue to reflect the information that
was selected during the most recent STATR write until changed
with an updated STATR write.

Any bits clocked out of the SO pin after the first eight will be

representative of the initial message bits clocked into the SI pin
since the CS pin first transitioned to a logic 0; this feature is
useful for daisy chaining devices as well as message

verification.

· Previous Address 000--If the previous three MSBs are

000, the bits D6-D0 will reflect the current state of the
Fault Register (FLTR)

Note: The FS pin reports a fault and is reset by a new Switch ON
command (via SPI or direct input IN).

· Previous Address 001-- the data in bits OD1 and OD0

will contain respective CSNS_EN and IN_SPI
programmed bits.

· Previous Address 010-- the data in bits OD3, OD2,

OD1, and OD0 contains respectively the programmed
Over Current high Detection Level ( see

Table 3

)and the

Overcurrent low Detection level (see

Table 2

· Previous Address 011--Data returned in bits OD1 and

OD0 are current values for the Over Current Dead Time,
illustrated in

Table 4

. Bit OD2 reports whethe the Over

Table 7. SI Address and Configuration Bit Map

2.0 m

SI Data

D7 D6 D5 D4

STATR

SOA2

SOA1

SOA0

OCR

CSNS EN

IN_SPI

SOCHLR

SOCH

SOCLA2 SOCLA1 SOCLA0

SDTOLR

OL dis

CD dis

CDT1

CDT0

DICR

FAST

CSNS

high

IN dis

A/O

OSDR

OSDA2

OSDA1

OSDA0

WDR

WDA1

WDA0

NAR

TEST

Motorola Internal Use (Test)

Table 8. SO Output Bit Assignment

Device Status Return Format

Bit

Sig

SO Msg

Bit

Message Bit Description

MSB

0D7=0

Reflects the state of the Watchdog bit from the
previously clocked in message (See

Table 11

for

exception.)

OD6

This bit will be S0A2 as selected by the most recent
STATR command. However, when a STATR
command of 000 (SOA[2:0]) is sent, D6 will contain
the Over Temperature Fault (OTF) status.

OD5

This bit will be S0A1 as selected by the most recent
STATR command. However, when a STATR
command of 000 (SOA[2:0]) is sent, D5 will contain
the Over Current Detect Hi Fault (OCHF) status.

OD4

This bit will be S0A0 as selected by the most recent
STATR command. However, when a STATR
command of 000 (SOA[2:0]) is sent, D4 will contain
the Over Current Detect Low Fault (OCLF) status.

OD3

This bit will reflect the register contents as selected
by the most recent STATR command. A STATR
command of 000 (SOA[2:0]) will return the Open
Load Fault (OLF) status.

OD2

This bit will reflect the register contents as selected
by the most recent STATR command. A STATR
command of 000 (SOA[2:0]) will return the Under-
Voltage Fault (UVF) status.

OD1

This bit will reflect the register contents as selected
by the most recent STATR command. A STATR
command of 000 (SOA[2:0]) will return the Over
Voltage Fault (OVF) status.

LSB

OD0

This bit will reflect the register contents as selected
by the most recent STATR command. A STATR
command of 000 (SOA[2:0]) will return the Fault
(FAULT) status, which is the boolean OR of all of
the other fault bits.

Table 9. Fault Register

OTF

OCHF

OCLF

OLF

UVF

OVF

FAULT

D7. Don't Care

D6. (OTF) = Over Temperature Flag

D5. (OCHF) = Over Current High Flag. (This fault is latched)

D4. (OCLF) = Over Current Low Flag. (This fault is latched)

D3. (OLF) = Open Load Flag

D2. (UVF) = Under Voltage Flag (This fault is latched)

D1. (OVF) = Over Voltage Flag

D0. (FAULT) = This flag reports a fault and is reset by a read operation

Table 8. SO Output Bit Assignment(continued)

Device Status Return Format

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

Current Detection timeout feature is active. OD3 reports
whether the open load circuitry is active.

· Previous Address 100-- The returned data contains the

programmed values in the DICR.

· Previous Address 101--

D7=0 The returned data contains the programmed values
in the OSDR.
D7=1 The returned data contains the programmed values
in the WDR.

· Previous Address 110--OD2 to OD0 Return

respectively the state of the IN, FSI and Wake pin (see

Table 10

· Address 111--Null Data. No previous register Read Back

command received, so bits OD2, OD1, and OD0 are null,
or 000.

The

Table 11

summarize the SO register content.

General SO Communication Statements

Any bits clocked out of the SO pin after the first eight will be

representative of the initial message bits clocked into the SI pin
since the CS pin first transitioned to a logic [0]; this feature is
useful for daisy chaining devices as well as message
verification.

Following a CS transition of [0] to [1], determines if the

message was of a valid length and if so, the data is latched into
the appropriate registers. A valid message length is a multiple
of eight bits. At this time, the SO pin is tri-stated and the fault
status register is now able to accept new fault status
information.

The output status register correctly reflects the status of the

STATR selected register data at the time that the CS is pulled
to a logic [0] during SPI communication, and/or for the period of
time since the last valid SPI communication, with the following
exceptions:

· The previous SPI communication was determined to be

invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.

· Battery transients below 6.0 V resulting in an under-

voltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the master during the first SPI
communication following an under-voltage V

PWR

condition

should be ignored.

· The RST pin transition from a logic [0] to [1] while the

WAKE pin is at logic [0] may result in incorrect data loaded
into the status register. The SO data transmitted to the
master during the first SPI communication following this
condition should be ignored.

Watchdog and Fail-Safe Operation

If the FSI input is a logic [1], that is, not grounded, the

Watchdog timeout detection is active when either the WAKE or
RST input pin transitions from logic[0] to [1]. The WAKE input is
capable of being pulled up to V

PWR

with a series of limiting

resistance limiting the internal clamp current according to the
specification.

The Watchdog timeout is a multiple of an internal oscillator

and is specified in the

Table 6

. As long as the WD bit (D7) of an

incoming SPI message, is toggled within the minimum
watchdog timeout period (WDTO, based on the programmed
value of the WDR register), the device will operate normally. If
an internal watchdog timeout occurs before the WD bit, the
device will revert to a Fail-Safe mode until the device is
reinitialized.

During the Fail-Safe mode, the output will be driven ON

regardless of the state of the various direct inputs and modes.
Fail-safe mode can be detected by monitoring the WDTO bit D2
of the WDR register. This bit is logic [1] when the device is in
fail-safe mode. The device can be brought out of the Fail-Safe
mode by transitioning the WAKE and RST pins from logic [1] to
logic [0] or forcing the FSI pin to logic [0].

Table 12

summarizes

the various methods for resetting the device from the latched
Fail-Safe mode.

If the FSI pin is tied to GND, the Watchdog fail-safe operation

is disabled.

Table 10. PIN Register

IN Pin

FSI Pin

WAKE Pin

Table 11. SO Bit Map Description

Previous

STATR

D7, D2, D1, D0

SO Returned Data

D7 SO

WDin

OTF OCHF OCLF

OLF

UVF

OVF

Fault

WDin

CSNS_

IN_SPI

WDin

SOCH SOCLA2 SOCLA1 SOCLA0

WDin

OL dis

CD dis

CDT1

CDT0

WDin

Fast

CSNS

high

IN dis

A/O

OSDA2

OSDA1 OSDA0

WDTO

WDA1

WDA0

WDin

IN pin

FSI pin

WAKE

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Loss of

and Fail-Safe Mode

The external 5 V supply connected to

powers the SPI

circuitry and any other internal logic that is not active during
device fail-safe operation.

If the external 5 V supply is not within specification or even

disconnected, then the 33982 will transition to fail-safe mode, if
enabled, otherwise the output will latch off.

The 33982 uses the battery input to power the output

MOSFET, related current sense circuitry and any other internal
logic providing fail-safe device operation with no V

supplied.

Then, the watchdog, the over voltage, over temperature, and
over current circuitry are fully operational (with default values)
in the device fail-safe mode of operation regardless the state of

Default or Sleep Mode

The default mode of the 33982 is also the Sleep mode. This is
the state of the device after first applying battery voltage
(V

PWR

), prior to any I/O transitions. This is also the state of the

device when the WAKE and RST are both logic [0]. In the Sleep
mode, the output, and all unused internal circuitry, such as the
internal 5 V regulator, are off to minimize current draw. In
addition, all SPI configurable features of the device are as if set
to logic [0]. The device will transition to the normal or fail-safe
operating modes based on the Wake and Reset inputs as
defined in

Table 12

Fault Logic What Happen During Fail-Safe

This device indicates the faults below as they occur by

driving the FS pin to [0]:

· Over temperature fault
· Open load fault
· Over current fault (high and low)
· Over voltage and under voltage fault

Some of the faults are latched. See

Table 9

The FS pin will return to [1] when the fault condition is

removed. Specific fault information is retained in the fault
register and is available via the SO pin during the first valid SPI
communication after the STATR D[3:0] bits are configured to
0000.

Over Temperature Fault

The 33982 device incorporates over temperature detection

and shutdown circuitry in the output structure. Over
temperature detection occurs when the output is in the ON
state.

For the output, an over temperature fault (OTF) condition will

result in the output turning OFF until the temperature falls below
the T

LIM(hyst)

. This cycle will continue indefinitely until action is

taken by the master to shut OFF the output, or until the
offending load is removed.

When experiencing this fault, the OTF fault bit will be set in

the status register and cleared after either a valid SPI read, a
power reset of the device.

Over Voltage Fault

The 33982 shuts down the output during an over voltage

fault (OVF) condition on the V

PWR

pin. The output remains in

the OFF state, until the over voltage condition is removed.
When experiencing this fault, the OVF fault bit is set in the
status register and cleared after either a valid SPI read, a power
reset of the device.

Open Load Fault

The 33982 incorporates open load detection circuitry on the

output. output Open Load Fault (OLF) is detected and reported
as a fault condition when the output is disabled (OFF). The
open load fault is detected and latched into the status register
after the internal gate voltage is pulled low enough to turn OFF
the output. The OLF fault bit is set in the status register. If the
open load fault is removed, the status register will be cleared
after reading the register.

Table 12. Fail-Safe Operation and Transitions to Other

33982 Modes

WAKE

RST

WDTO

OUT

Comments

OFF

Device is in Sleep mode

OFF

Output is OFF,Watchdog is
alive.

Yes

Watchdog has timed out and the
device is in Fail-Safe Mode. RST
and WAKE must be transitioned
to logic 0 simultaneously to bring
the device out of the Fail-safe
mode.

Device in Normal Operating
mode

Yes

Watchdog has timed out and the
device is in Fail-Safe Mode. RST
and WAKE must be transitioned
to logic 0 simultaneously to bring
the device out of the Fail-safe
mode.

Device in Normal Operating
mode

Yes

Watchdog has timed out and the
device is in Fail-Safe Mode. RST
and WAKE must be transitioned
to logic 0 simultaneously to bring
the device out of the Fail-Safe
mode.

x = Don't care

S = State determined by SPI and /or Direct Input configurations

Assumptions: Normal operating voltage and junction temperatures
with FSI pin floating

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33982

Over Current Fault

The device has eight programmable over current low

detection levels and two programmable over current high
detection levels for maximum device protection. The two
selectable, overriding over current detection levels, defined by
IOCH0 and IOCH are illustrated in

Figure 4

. There are also

eight different over current low detect levels (IOCL0, IOCL1,
IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, & IOCL7) also
illustrated in

Figure 4

If the load current level ever reaches the selected over

current low detect level, and the over current condition exceeds
the programmed over current time period (t

OCx

) , then the

device will latch the output off.

If, at any time, the current reaches the selected IOCH level,

then the device will latch off immediately, regardless of the
selected t

OCLx

driver.

For both cases, the device output will stay off indefinitely,

until the device is commanded off and then on again.

Reverse Battery

The output survives the application of reverse voltage as low

as -16 V. Under these conditions, the output will enhance to
keep the junction temperature less than 150°C and the ON
resistance of the output will fairly be the same than in normal
mode. No additional passive component are required

Ground Disconnect Protection

In the event the 33982 ground is disconnected from load

ground, the device protects itself and safely turns OFF the
output, regardless the state of the output at the time of
disconnection.

Under Voltage Shutdown

The output latches off at some battery voltage between 5.0

V and 6.0 V. As long as the V

level stays within the normal

specified range, the internal logic states within the device will be
sustained. This ensures that when the battery level then returns
above 6.0 V, the device can be returned to the state that it was
in prior to the low V

PWR

excursion. Once the output latches

OFF, the device must be turned off and then on again to re-
enable the output.

33982

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

PACKAGE DIMENSIONS

PIN 1
INDEX AREA

2.2 2.20

0.05

0.1

0.05

SEATING PLANE

DETAIL G

VIEW ROTATED 90 CLOCKWISE

NOTES:
1.

ALL DIMENSIONS ARE IN MILLIMETERS.

DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.

THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.

COPLANARITY APPLIES TO LEADS AND
CORNER LEADS.

4.65

10X

(0.4)

0.1

0.05

A B

C A B

VIEW M-M

4.95

0.1

B C

2.0 1.95

0.00

0.1

0.9

1.075

1.90

1.65

1.85

3.55

(2)

0.7

0.5

1.18

0.98

6 PLACES

0.15

0.05

10X

(0.5)

10.65
10.35

0.1

B C

11.15
10.85

(0.75)

1.35

1.15

0.1

B C

5.45
5.15

0.1

B C

2.1
1.8

10X

(0.25)

2.45

2.15

0.1

B C

0.95

0.75

0.82

0.68

0.1

0.05

A B

10X

0.47

0.33

FC SUFFIX

PLASTIC PACKAGE

CASE 1402-01

PQFN

ISSUE A

HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217.
1-303-675-2140 or 1-800-441-2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan.
81-3-3440-3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T.,
Hong Kong. 852-26668334
TECHNICAL INFORMATION CENTER: 1-800-521-6274

MC33982/D

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do
vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer
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