This document describes part-number-specific changes to recommended operating conditions
and revised electrical specifications, as applicable, from those described in the general

MPC7457 RISC Microprocessor Hardware Specifications

(Order No. MPC7457EC). The

MPC7457 and MPC7447 are implementations of the PowerPCTM microprocessor family of
reduced instruction set computer (RISC) microprocessors.

Specifications provided in this document supersede those in the

MPC7457 RISC

Microprocessor Hardware Specifications

, Rev. 2 or later, for the part numbers listed in

Table A only. This document is primarily concerned with the MPC7457; however, unless
otherwise noted, all information herein also applies to the MPC7447 part numbers listed in
Table A. Specifications not addressed herein are unchanged. Because this document is
frequently updated, refer to http://www.motorola.com/semiconductors or to your Motorola
sales office for the latest version.

Note that headings and table numbers in this document are not consecutively numbered. They
are intended to correspond to the heading or table affected in the general hardware
specification.

Advance Information

MPC7457RXNXPNS
Rev. 2, 10/2003

MPC7457 Part Number
Specification for the
MPC74x7RXnnnnNx Series

Motorola Part
Numbers Affected:

PPC7457RX1000NB
PPC7457RX867NB
PPC7457RX733NB
PPC7457RX600NB
PPC7447RX1000NB
PPC7447RX867NB
MC7447RX1000NB
MC7447RX867NB
MC7447RX733NB
MC7447RX600NB

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MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series

MOTOROLA

Part numbers addressed in this document are listed in Table A.

Table A. Part Numbers Addressed by this Data Sheet

Motorola

Part Number

Operating Conditions

Significant Differences from

Hardware Specification

CPU

Frequency

(MHz)

(°C)

PPC7457RX1000NB

1000

1.1 V ± 50 mV

0 to 105

Modified core frequency and voltage to reduce
power consumption, modified processor bus AC
timing.

PPC7447RX1000NB

MC7447RX1000NB

PPC7457RX867NB

867

PPC7447RX867NB

MC7447RX867NB

PPC7457RX733NB

733

MC7447RX733NB

PPC7457RX600NB

600

MC7447RX600NB

Note:

The P prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP

3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may
be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the
qualification status and the fact that product changes may still occur while shipping pilot production prototypes.

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MOTOROLA

MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series

Features

1.2 Features

This section summarizes changes to the features of the MPC7457 described in the

MPC7457 RISC

Microprocessor Hardware

Specifications

Power management

-- 1.1-V processor core

1.3 General Parameters

Core power supply: 1.1 V ± 50 mV DC nominal

1.5.1 DC Electrical Characteristics

Table 4 provides the recommended operating conditions for the MPC7457 part numbers described herein.

Table 4. Recommended Operating Conditions

Characteristic

Symbol

Recommended

Value

Unit

Core supply voltage

1.1 V ± 50 mV

PLL supply voltage

1.1 V ± 50 mV

Note:

These are the recommended and tested operating conditions. Proper device operation outside of these

conditions is not guaranteed.

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MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series

MOTOROLA

General Parameters

Table 7 provides the power consumption for the MPC7457 part numbers described herein.

Table 7. Power Consumption for MPC7457

Processor (CPU) Frequency

Unit

Notes

600 MHz

733 MHz

867 MHz

1000 MHz

Full-Power Mode

Typical 5.3

6.3

7.3

8.3

Maximum 7.9

9.1

10.3

11.5

Doze Mode

Typical

Nap Mode

Typical

1.3

1, 2

Sleep Mode

Typical

1.2

1, 2

Deep Sleep Mode (PLL Disabled)

Typical

1.1

1, 3

Notes:

1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power

(OV

and GV

) or PLL supply power (AV

). OV

and GV

power is system dependent, but is typically <5%

of V

power. Worst case power consumption for AV

< 3 mW.

2. Maximum power is the maximum measured at nominal V

and maximum operating junction temperature (see

Table 4) while running an entirely cache-resident, contrived sequence of instructions which keep all the execution
units maximally busy.

3. Typical power is an average value measured at the nominal recommended V

(see Table 4) and 65

C while

running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep

mode. As a result, power consumption for this mode is not tested.

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MOTOROLA

MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series

General Parameters

Table 8 provides the clock AC timing specifications for the MPC7457 part numbers described herein.

Table 8. Clock AC Timing Specifications

At recommended operating conditions. See Table 4.

Characteristic

Symbol

Maximum Processor Core Frequency

Unit

Notes

600 MHz

733 MHz

867 MHz

1000 MHz

Min

Max

Min

Max

Min

Max

Min

Max

Processor frequency

core

500

600

500

733

500

867

500

1000

MHz

VCO frequency

VCO

1000

1200

1000

1466

1000

1733

1000

2000

MHz

SYSCLK frequency

SYSCLK

167

MHz

SYSCLK cycle time

SYSCLK

6.0

Note:

Caution

: The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)

frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 1.9.1, "PLL Configuration," for valid
PLL_CFG[0:4] settings.

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MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series

MOTOROLA

General Parameters

1.5.2.2

Processor Bus AC Specifications

Table 9 provides the processor bus AC timing specifications for the MPC7457 part numbers described
herein.

Table 9. Processor Bus AC Timing Specifications

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades

Unit

Notes

Min

Max

Input setup times:

A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

HIT, TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1], BMODE[0:1],

BMODE[0:1], BVSEL, L3VSEL

AVKH

DVKH

IVKH

MVKH

2.0
2.0
2.0

2.0

--
--
--

Input hold times:

A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,

HIT, TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1]

BMODE[0:1], BVSEL, L3VSEL

AXKH

DXKH

IXKH

MXKH

0
0
0

--
--
--

Output valid times:

A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT

KHAV

KHDV

KHOV

--
--
--

2.0
2.0
2.0

Output hold times:

A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],

GBL, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT

KHAX

KHDX

KHOX

0.5
0.5
0.5

--
--
--

SYSCLK to output enable

KHOE

0.5

SYSCLK to output high impedance (all except TS, ARTRY,
SHD0, SHD1)

KHOZ

3.5

SYSCLK to TS high impedance after precharge

KHTSPZ

SYSCLK

3, 4, 5

Maximum delay to ARTRY/SHD0/SHD1 precharge

KHARP

SYSCLK

3, 5,

6, 7

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MOTOROLA

MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series

General Parameters

SYSCLK to ARTRY/SHD0/SHD1 high impedance after
precharge

KHARPZ

SYSCLK

3, 5
6, 7

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge

of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the
midpoint of the signal in question. All output timings assume a purely resistive 50-

load (see Figure 4 in the

MPC7457 RISC Microprocessor Hardware Specifications)

. Input and output timings are measured at the pin;

time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of t

(signal)(state)(reference)(state)

for inputs and

(reference)(state)(signal)(state)

for outputs. For example, t

IVKH

symbolizes the time input signals (I) reach the valid state

(V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

KHOV

symbolizes the

time from SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read
as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) (note the position of
the reference and its state for inputs) and output hold time can be read as the time from the rising edge (KH) until
the output went invalid (OX).

3. t

SYSCLK

is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by

the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. According to the bus protocol, TS is driven only by the currently active bus master. It is asserted low then

precharged high before returning to high impedance, as shown in Figure 6 in the

MPC7457 RISC Microprocessor

Hardware Specifications

. The nominal precharge width for TS is 0.5

SYSCLK

, that is, less than the minimum

SYSCLK

period, to ensure that another master asserting TS on the following clock will not contend with the

precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for
precharge. The high-impedance behavior is guaranteed by design.

5. Guaranteed by design and not tested.
6. According to the bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately

following AACK. Bus contention is not an issue because any master asserting ARTRY will be driving it low. Any
master asserting it low in the first clock following AACK will then go to high impedance for one clock before
precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY
is 1.0 t

SYSCLK

; that is, it should be high impedance, as shown in Figure 6 in the

MPC7457 RISC Microprocessor

Hardware Specifications,

before the first opportunity for another master to assert ARTRY. Output valid and output

hold timing is tested for the signal asserted.The high-impedance behavior is guaranteed by design.

7. According to the MPX bus protocol, SHD0 and SHD1 can be driven by multiple bus masters beginning the cycle of

TS. Timing is the same as ARTRY, that is, the signal is high impedance for a fraction of a cycle, then negated for
up to an entire cycle (crossing a bus cycle boundary) before being three-stated again. The nominal precharge width
for SHD0 and SHD1 is 1.0 t

SYSCLK

. The edges of the precharge vary depending on the programmed ratio of core

to bus (PLL configurations).

8. BMODE[0:1] and BVSEL are mode select inputs and are sampled before and after HRESET negation. These

parameters represent the input setup and hold times for each sample. These values are guaranteed by design and
not tested. These inputs must remain stable after the second sample. See Figure 5 in the

MPC7457 RISC

Microprocessor Hardware Specifications

for sample timing.

Table 9. Processor Bus AC Timing Specifications

(continued)

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades

Unit

Notes

Min

Max

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MOTOROLA

MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series

Ordering Information

1.11 Ordering Information

1.11.1 Part Numbers Addressed by This Specification

Table 22 provides the ordering information for the MPC7457 parts described in this document.

Table 22. Part Marking Nomenclature

xxx

74x7

nnnn

Product

Code

Part

Identifier

Package

Processor

Frequency

Application Modifier

Revision Level

PPC

7457

RX = CBGA

1000

N: 1.1 V ± 50 mV

to 105

B: 1.1: PVR = 8002 0101

867

733

600

7447

1000

867

7447

1000

867

733

600

Notes:
1. Processor core frequencies supported by parts addressed by this specification only. Parts addressed by other

specifications may support other maximum core frequencies.

2. The P prefix in a Motorola part number designates a "Pilot Production Prototype" as defined by Motorola SOP

3-13. These parts have only preliminary reliability and characterization data. Before pilot production prototypes
may be shipped, written authorization from the customer must be on file in the applicable sales office
acknowledging the qualification status and the fact that product changes may still occur while shipping pilot
production prototypes.

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MOTOROLA MPC7457 Part Number Specification for the MPC74x7RXnnnnNx Series

Document Revision History

Table B provides a revision history for this part number specification.

Table B. Document Revision History

Rev. No.

Substantive Change(s)

Initial release.

0.1

Edited introductory paragraphs to clarify which part numbers are affected by this specification.

Corrected product code in part numbers on page 1 and in Table A.

Updated power consumption specifications in Table 7.

Corrected product code in Section 1.11 and Table 21.

Added "MC7447..." part numbers to reflect qualification status.

Table 8: Increased maximum system bus frequency (f

SYSCLK

) to 167 MHz.

Table 9: Corrected numerous errors in lists of pins associated with t

KHOV

, t

KHOX

, t

IVKH

, and t

IXKH

Updated (improved) AC timing parameters based on latest characterization data.

Added 867, 733, and 600 MHz speed grades.

Removed Tables 10, 13, and 14: devices described by this specification conform to the AC timing found
in the MPC7457 hardware specifications.

Corrected typo in Figure 29: 7447 device was incorrectly marked...RX10000NB.

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MPC7457RXNXPNS

HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:

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P.O. Box 5405, Denver, Colorado 80217
1-480-768-2130
(800) 521-6274

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Tokyo 106-8573 Japan
81-3-3440-3569

ASIA/PACIFIC:

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Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334

TECHNICAL INFORMATION CENTER:

(800) 521-6274

HOME PAGE:

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PPC7457RX1000NB

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: PPC7457RX1000NB