SG3525A
SG3527A
SEMICONDUCTOR
TECHNICAL DATA
PULSE WIDTH MODULATOR
CONTROL CIRCUITS
PIN CONNECTIONS
Order this document by SG3525A/D
N SUFFIX
PLASTIC PACKAGE
CASE 648
16
1
DW SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO16L)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(Top View)
Inv. Input
Sync
OSC. Output
RT
Discharge
SoftStart
Noninv. Input
CT
Compensation
Shutdown
Output A
VC
Output B
VCC
Vref
Ground
Device
Operating
Temperature Range
Package
ORDERING INFORMATION
SG3525AN
SG3525ADW
TA = 0
to +70
C
Plastic DIP
SO16L
SG3527AN
Plastic DIP
16
1
1
MOTOROLA ANALOG IC DEVICE DATA
Pulse Width
Modulator Control Circuits
The SG3525A, SG3527A pulse width modulator control circuits offer
improved performance and lower external parts count when implemented for
controlling all types of switching power supplies. The onchip +5.1 V
reference is trimmed to
1% and the error amplifier has an input
commonmode voltage range that includes the reference voltage, thus
eliminating the need for external divider resistors. A sync input to the
oscillator enables multiple units to be slaved or a single unit to be
synchronized to an external system clock. A wide range of deadtime can be
programmed by a single resistor connected between the CT and Discharge
pins. These devices also feature builtin softstart circuitry, requiring only an
external timing capacitor. A shutdown pin controls both the softstart circuitry
and the output stages, providing instantaneous turn off through the PWM
latch with pulsed shutdown, as well as softstart recycle with longer
shutdown commands. The under voltage lockout inhibits the outputs and the
changing of the softstart capacitor when VCC is below nominal. The output
stages are totempole design capable of sinking and sourcing in excess of
200 mA. The output stage of the SG3525A features NOR logic resulting in a
low output for an offstate while the SG3527A utilized OR logic which gives a
high output when off.
8.0 V to 35 V Operation
5.1 V
1.0% Trimmed Reference
100 Hz to 400 kHz Oscillator Range
Separate Oscillator Sync Pin
Adjustable Deadtime Control
Input Undervoltage Lockout
Latching PWM to Prevent Multiple Pulses
PulsebyPulse Shutdown
Dual Source/Sink Outputs:
400 mA Peak
Representative Block Diagram
NOR
NOR
16
15
12
4
3
6
5
7
9
1
2
8
10
Reference
Regulator
Under
Voltage
Lockout
Oscillator
Latch
F/F
Q
Q
PWM
Error
Amp
+
+
To Internal
Circuitry
VREF
Vref
VCC
Ground
OSC Output
Sync
RT
CT
Discharge
Compensation
INV. Input
Noninv. Input
CSoftStart
Shutdown
5.0k
S
R
S
50
A
VC
13
Output A
11
14
Output B
SG3525A Output Stage
13
VC
Output A
11
Output B
14
SG3527A
Output Stage
OR
OR
5.0k
Motorola, Inc. 1996
Rev 2
SG3525A SG3527A
2
MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
(Note 1)
Rating
Symbol
Value
Unit
Supply Voltage
VCC
+40
Vdc
Collector Supply Voltage
VC
+40
Vdc
Logic Inputs
0.3 to +5.5
V
Analog Inputs
0.3 to VCC
V
Output Current, Source or Sink
IO
500
mA
Reference Output Current
Iref
50
mA
Oscillator Charging Current
5.0
mA
Power Dissipation (Plastic & Ceramic Package)
TA = +25
C (Note 2)
TC = +25
C (Note 3)
PD
1000
2000
mW
Thermal Resistance JunctiontoAir
R
JA
100
C/W
Thermal Resistance JunctiontoCase
R
JC
60
C/W
Operating Junction Temperature
TJ
+150
C
Storage Temperature Range
Tstg
55 to +125
C
Lead Temperature (Soldering, 10 seconds)
TSolder
+300
C
NOTES: 1. Values beyond which damage may occur.
2. Derate at 10 mW/
C for ambient temperatures above +50
C.
3. Derate at 16 mW/
C for case temperatures above +25
C.
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
Max
Unit
Supply Voltage
VCC
8.0
35
Vdc
Collector Supply Voltage
VC
4.5
35
Vdc
Output Sink/Source Current
(Steady State)
(Peak)
IO
0
0
100
400
mA
Reference Load Current
Iref
0
20
mA
Oscillator Frequency Range
fosc
0.1
400
kHz
Oscillator Timing Resistor
RT
2.0
150
k
Oscillator Timing Capacitor
CT
0.001
0.2
F
Deadtime Resistor Range
RD
0
500
Operating Ambient Temperature Range
TA
0
+70
C
APPLICATION INFORMATION
Shutdown Options (See Block diagram, front page)
Since both the compensation and softstart terminals
(Pins 9 and 8) have current source pullups, either can
readily accept a pulldown signal which only has to sink a
maximum of 100
A to turn off the outputs. This is subject to
the added requirement of discharging whatever external
capacitance may be attached to these pins.
An alternate approach is the use of the shutdown circuitry
of Pin 10 which has been improved to enhance the available
shutdown options. Activating this circuit by applying a
positive signal on Pin 10 performs two functions: the PWM
latch is immediately set providing the fastest turnoff signal to
the outputs; and a 150
A current sink begins to discharge
the external softstart capacitor. If the shutdown command is
short, the PWM signal is terminated without significant
discharge of the softstart capacitor, thus, allowing, for
example, a convenient implementation of pulsebypulse
current limiting. Holding Pin 10 high for a longer duration,
however, will ultimately discharge this external capacitor,
recycling slow turnon upon release.
Pin 10 should not be left floating as noise pickup could
conceivably interrupt normal operation.
SG3525A SG3527A
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS
(VCC = +20 Vdc, TA = Tlow to Thigh [Note 4], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
REFERENCE SECTION
Reference Output Voltage (TJ = +25
C)
Vref
5.00
5.10
5.20
Vdc
Line Regulation (+8.0 V
VCC
+35 V)
Regline
10
20
mV
Load Regulation (0 mA
IL
20 mA)
Regload
20
50
mV
Temperature Stability
Vref/
T
20
mV
Total Output Variation
Includes Line and Load Regulation over Temperature
Vref
4.95
5.25
Vdc
Short Circuit Current
(Vref = 0 V, TJ = +25
C)
ISC
80
100
mA
Output Noise Voltage (10 Hz
f
10 kHz, TJ = +25
C)
Vn
40
200
Vrms
Long Term Stability (TJ = +125
C) (Note 5)
S
20
50
mV/khr
OSCILLATOR SECTION
(Note 6, unless otherwise noted.)
Initial Accuracy (TJ = +25
C)
2.0
6.0
%
Frequency Stability with Voltage
(+8.0 V
VCC
+35 V)
fosc
D VCC
1.0
2.0
%
Frequency Stability with Temperature
fosc
D
T
0.3
%
Minimum Frequency (RT = 150 k
, CT = 0.2
F)
fmin
50
Hz
Maximum Frequency (RT = 2.0 k
, CT = 1.0 nF)
fmax
400
kHz
Current Mirror (IRT = 2.0 mA)
1.7
2.0
2.2
mA
Clock Amplitude
3.0
3.5
V
Clock Width (TJ = +25
C)
0.3
0.5
1.0
s
Sync Threshold
1.2
2.0
2.8
V
Sync Input Current (Sync Voltage = +3.5 V)
1.0
2.5
mA
ERROR AMPLIFIER SECTION (VCM = +5.1 V)
Input Offset Voltage
VIO
2.0
10
mV
Input Bias Current
IIB
1.0
10
A
Input Offset Current
IIO
1.0
A
DC Open Loop Gain (RL
10 M
)
AVOL
60
75
dB
Low Level Output Voltage
VOL
0.2
0.5
V
High Level Output Voltage
VOH
3.8
5.6
V
Common Mode Rejection Ratio (+1.5 V
VCM
+5.2 V)
CMRR
60
75
dB
Power Supply Rejection Ratio (+8.0 V
VCC
+35 V)
PSRR
50
60
dB
PWM COMPARATOR SECTION
Minimum Duty Cycle
DCmin
0
%
Maximum Duty Cycle
DCmax
45
49
%
Input Threshold, Zero Duty Cycle (Note 6)
Vth
0.6
0.9
V
Input Threshold, Maximum Duty Cycle (Note 6)
Vth
3.3
3.6
V
Input Bias Current
IIB
0.05
1.0
A
NOTES: 4. Tlow = 0
for SG3525A, 3527A
Thigh = +70
C for SG3525A, 3527A
5. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability
from lot to lot.
6. Tested at fosc = 40 kHz (RT = 3.6 k
, CT = 0.01
F, RD = 0
).
SG3525A SG3527A
4
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (Continued)
Characteristics
Symbol
Min
Typ
Max
Unit
SOFTSTART SECTION
SoftStart Current (Vshutdown = 0 V)
25
50
80
A
SoftStart Voltage (Vshutdown = 2.0 V)
0.4
0.6
V
Shutdown Input Current (Vshutdown = 2.5 V)
0.4
1.0
mA
OUTPUT DRIVERS (Each Output, VCC = +20 V)
Output Low Level
(Isink = 20 mA)
(Isink = 100 mA)
VOL
0.2
1.0
0.4
2.0
V
Output High Level
(Isource = 20 mA)
(Isource = 100 mA)
VOH
18
17
19
18
V
Under Voltage Lockout (V8 and V9 = High)
VUL
6.0
7.0
8.0
V
Collector Leakage, VC = +35 V (Note 7)
IC(leak)
200
A
Rise Time (CL = 1.0 nF, TJ = 25
C)
tr
100
600
ns
Fall Time (CL = 1.0 nF, TJ = 25
C)
tf
50
300
ns
Shutdown Delay (VDS = +3.0 V, CS = 0, TJ = +25
C)
tds
0.2
0.5
s
Supply Current (VCC = +35 V)
ICC
14
20
mA
NOTE:
7. Applies to SG3525A only, due to polarity of output pulses.
Reference Regulator
Flip/
Flop
PWM
+
E/A
DUT
Vref
Clock
16
4
0.1
3
6
7
5
Deadtime
100
0.001
Comp
10k
9
0.01
1
2
1
2
3
1
2
3
3
2
1
3
+
1 = VIO
2 = 1(+)
3 = 1()
0.1
0.009
1.5k
1.0k
3.0k
PWM
ADJ.
Sync
RT
Ramp
50
A
5.0k
5.0k
15
13
11
VC
Out A
0.1
0.1
1.0k, 1.0W
(2)
14
Out B
Gnd
12
8
Softstart
5.0
F
10
2.0k
Shutdown
Vref
+
O
s
c
i
l
l
a
t
o
r
V/I Meter
VCC
A
1
2
B
Lab Test Fixture
SG3525A SG3527A
5
MOTOROLA ANALOG IC DEVICE DATA
R
T
, TIMING RESIST
OR
(k
)
Figure 1. Oscillator Charge Time versus RT
Figure 2. Oscillator Discharge Time versus RD
Figure 3. Error Amplifier Open Loop
Frequency Response
Figure 4. Output Saturation
Characteristics (SG3525A)
2.0
5.0 10
20
50
100 200 500 1000 2000 5000 10,000
CHARGE TIME (
s)
6
5
7
RD *
CT
RT
* RD = 0
0.2
0.5
1.0
2.0
5.0
10
20
50
100 200
DISCHARGE TIME (
s)
, DEAD
TIME RESIST
OR (
)
D
R
1.0
10
100
1.0 k
10 k
100 k
1.0 M
10 M
1
2
9
CP
RZ
f, FREQUENCY (Hz)
,
VOL
T
AGE GAIN (dB)
VOL
+
A
RZ = 20 k
Vref
RT
CT
Sync
Discharge
Gnd
16
6
5
3
7
12
Q2
Q1
Q6
Q9
2.0k
2.0k
14k
Q10
Q11
5.0pF
400
A
23k
Q4
Q7
1.0k
Q12
Q13
3.0k
250
4
Blanking
To Output
Ramp
To PWM
Q14
25k
7.4k
Q5
Q8
Q3
OSC Output
1.0k
15
Q3
VCC
9
30
Compensation
1
2
Q4
Q1
Q2
Inverting
Input
5.8V
100
A
To PWM
Comparator
200
A
Noninverting
Input
Figure 5. Oscillator Schematic (SG3525A)
0.01
0.02 0.03
0.05 0.07 0.1
0.2
0.3
0.5 0.7 1.0
IO, OUTPUT SOURCE OR SINK CURRENT (A)
, SA
TURA
TION VOL
T
AGE
(V)
sat
V
Sink Sat, (VOL)
Source Sat, (VCVOH)
VCC = +20 V
TJ = +25
C
Figure 6. Error Amplifier Schematic (SG3525A)
200
100
50
20
10
5.0
2.0
500
400
300
200
100
0
100
80
60
40
20
0
20
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
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