5-1
FAST AND LS TTL DATA
SERIAL-IN PARALLEL-OUT
SHIFT REGISTER
The SN54 / 74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Regis-
ter. Serial data is entered through a 2-Input AND gate synchronous with the
LOW to HIGH transition of the clock. The device features an asynchronous
Master Reset which clears the register setting all outputs LOW independent of
the clock. It utilizes the Schottky diode clamped process to achieve high
speeds and is fully compatible with all Motorola TTL products.
Typical Shift Frequency of 35 MHz
Asynchronous Master Reset
Gated Serial Data Input
Fully Synchronous Data Transfers
Input Clamp Diodes Limit High Speed Termination Effects
ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
14
13
12
11
10
9
1
2
3
4
5
6
8
7
VCC
Q7
Q6
Q5
Q4
MR
CP
A
B
Q0
Q1
Q2
Q3
GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES
LOADING (Note a)
HIGH
LOW
A, B
CP
MR
Q0 Q7
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
A HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS164
SERIAL-IN PARALLEL-OUT
SHIFT REGISTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
1
2
8
9
3
4
5
6 10 11 12 13
A
B
CP
LS164
8-BIT SHIFT REGISTER
MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = PIN 14
GND = PIN 7
5-2
FAST AND LS TTL DATA
SN54/74LS164
LOGIC DIAGRAM
Q6
Q7
A
B
Q0
Q1
Q3
Q2
Q5
Q4
MR
CP
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
D
Q
CD
6
3
4
5
11
12
10
13
VCC = PIN 14
GND = PIN 7
= PIN NUMBERS
1
2
8
9
FUNCTIONAL DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with seri-
al data entry and an output from each of the eight stages. Data
is entered serially through one of two inputs (A or B); either of
these inputs can be used as an active HIGH Enable for data
entry through the other input. An unused input must be tied
HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input shifts
data one place to the right and enters into Q0 the logical AND
of the two data inputs (A
B) that existed before the rising clock
edge. A LOW level on the Master Reset (MR) input overrides
all other inputs and clears the register asynchronously, forcing
all Q outputs LOW.
MODE SELECT -- TRUTH TABLE
OPERATING
MODE
INPUTS
OUTPUTS
MODE
MR
A
B
Q0
Q1Q7
Reset (Clear)
L
X
X
L
L L
H
I
I
L
q0 q6
Shift
H
I
h
L
q0 q6
H
h
I
L
q0 q6
H
h
h
H
q0 q6
L (l) = LOW Voltage Levels
H (h) = HIGH Voltage Levels
X = Don't Care
qn = Lower case letters indicate the state of the referenced input or output one
qn =
set-up time prior to the LOW to HIGH clock transition.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High
54, 74
0.4
mA
IOL
Output Current -- Low
54
74
4.0
8.0
mA
5-3
FAST AND LS TTL DATA
SN54/74LS164
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.5
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 4.0 mA
VCC = VCC MIN,
VIN = VIH or VIL
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 8.0 mA
VIN = VIH or VIL
per Truth Table
IIH
Input HIGH Current
20
A
VCC = MAX, VIN = 2.7 V
IIH
Input HIGH Current
0.1
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
20
100
mA
VCC = MAX
ICC
Power Supply Current
27
mA
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
fMAX
Maximum Clock Frequency
25
36
MHz
VCC = 5.0 V
CL = 15 pF
tPHL
Propagation Delay
MR to Output Q
24
36
ns
VCC = 5.0 V
CL = 15 pF
tPLH
tPHL
Propagation Delay
Clock to Output Q
17
21
27
32
ns
CL = 15 pF
AC SETUP REQUIREMENTS
(TA = 25
C)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tW
CP, MR Pulse Width
20
ns
VCC = 5.0 V
ts
Data Setup Time
15
ns
VCC = 5.0 V
th
Data Hold Time
5.0
ns
VCC = 5.0 V
trec
MR to Clock Recovery Time
20
ns
5-4
FAST AND LS TTL DATA
SN54/74LS164
AC WAVEFORMS
*The shaded areas indicate when the input is permitted to change for predictable output performance.
Figure 1. Clock to Output Delays
and Clock Pulse Width
Figure 2. Master Reset Pulse Width,
Master Reset to Output Delay and
Master Reset to Clock Recovery Time
Figure 3. Data Setup and Hold Times
CONDITIONS: MR = H
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
tPHL
tPLH
CP
Q
CP
Q
MR
trec
tW
tPHL
tW
I/fmax
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
CP
D
Q
ts(H)
th(H)
ts(L)
th(L)
tW
1/fmax
1.3 V
1.3 V
*
1.3 V
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