5-427
FAST AND LS TTL DATA
QUAD 2-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
The LSTTL / MSI SN54 / 74LS257B and the SN54 / 74LS258B are Quad
2-Input Multiplexers with 3-state outputs. Four bits of data from two sources
can be selected using a Common Data Select input. The four outputs present
the selected data in true (non-inverted) form. The outputs may be switched to
a high impedance state with a HIGH on the common Output Enable (EO) In-
put, allowing the outputs to interface directly with bus oriented systems. It is
fabricated with the Schottky barrier diode process for high speed and is com-
pletely compatible with all Motorola TTL families.
Schottky Process For High Speed
Multiplexer Expansion By Tying Outputs Together
Non-Inverting 3-State Outputs
Input Clamp Diodes Limit High Speed Termination Effects
Special Circuitry Ensures Glitch Free Multiplexing
ESD > 3500 Volts
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
S
E0
I0c
I1c
Zc
I1d
I0d
Zd
I0a
I1a
Za
I0b
I1b
Zb GND
CONNECTION DIAGRAM DIP (TOP VIEW)
SN54/74LS257B
SN54/74LS258B
VCC = PIN 16
GND = PIN 8
14
13
12
11
10
9
1
2
3
4
5
6
7
16
15
8
VCC
S
E0
I0c
I1c
Zc
I1d
I0d
Zd
I0a
I1a
Za
I0b
I1b
Zb GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN54/74LS257B
SN54/74LS258B
QUAD 2-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ
Ceramic
SN74LSXXXN
Plastic
SN74LSXXXD
SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
16
1
D SUFFIX
SOIC
CASE 751B-03
5-428
FAST AND LS TTL DATA
SN54/74LS257B
D
SN54/74LS258B
LOGIC DIAGRAMS
SN54 / 74LS257B
E0
I0a
I1a
I0b
I1b
I0c
I1c
I0d
I1d
S
Za
Zb
Zc
Zd
SN54 / 74LS258B
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
E0
I0a
I1a
I0b
I1b
I0c
I1c
I0d
I1d
S
Za
Zb
Zc
Zd
14
1
2
6
7
3
4
5
9
11
12
10
13
15
14
1
2
6
3
5
11
10
13
15
7
4
9
12
5-429
FAST AND LS TTL DATA
SN54/74LS257B
D
SN54/74LS258B
FUNCTIONAL DESCRIPTION
The LS257B and LS258B are Quad 2-Input Multiplexers
with 3-state outputs. They select four bits of data from two
sources each under control of a Common Data Select Input.
When the Select Input is LOW, the I0 inputs are selected and
when Select is HIGH, the I1 inputs are selected. The data on
the selected inputs appears at the outputs in true (non-
inverted) form for the LS257B and in the inverted form for the
LS258B.
The LS257B and LS258B are the logic implementation of a
4-pole, 2-position switch where the position of the switch is
determined by the logic levels supplied to the Select Input. The
logic equations for the outputs are shown below:
LS257B
Za = E0
(I1a
S + I0a
S) Zb = E0
(I1b
S + I0b
S)
Zc = E0
(I1c
S + I0c
S) Zd = E0
(I1d
S + I0d
S)
When the Output Enable Input (E0) is HIGH, the outputs are
forced to a high impedance "off" state. If the outputs are tied
together, all but one device must be in the high impedance
state to avoid high currents that would exceed the maximum
ratings. Designers should ensure that Output Enable signals
to 3-state devices whose outputs are tied together are
designed so there is no overlap.
LS258B
Za = E0
(I1a
S + I0a
S) Zb = E0
(I1b
S + I0b
S)
Zc = E0
(I1c
S + I0c
S) Zd = E0
(I1d
S + I0d
S)
TRUTH TABLE
OUTPUT
ENABLE
SELECT
INPUT
DATA
INPUTS
OUTPUTS
LS257B
OUTPUTS
LS258B
EO
S
I0
I1
Z
Z
H
X
X
X
(Z)
(Z)
L
H
X
L
L
H
L
H
X
H
H
L
L
L
L
X
L
H
L
L
H
X
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
(Z) = High Impedance (off)
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
55
0
25
25
125
70
C
IOH
Output Current -- High
54
74
1.0
2.6
mA
IOL
Output Current -- Low
54
74
12
24
mA
5-430
FAST AND LS TTL DATA
SN54/74LS257B
D
SN54/74LS258B
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54
0.7
V
Guaranteed Input LOW Voltage for
All Inputs
VIL
Input LOW Voltage
74
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
0.65
1.5
V
VCC = MIN, IIN = 18 mA
VOH
Output HIGH Voltage
54
2.4
3.4
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOH
Output HIGH Voltage
74
2.4
3.1
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
54, 74
0.25
0.4
V
IOL = 12 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VOL
Output LOW Voltage
74
0.35
0.5
V
IOL = 24 mA
VIN = VIL or VIH
per Truth Table
IOZH
Output Off Current -- HIGH
20
A
VCC = MAX, VOUT = 2.7 V
IOZL
Output Off Current -- LOW
20
A
VCC = MAX, VOUT = 0.4 V
IIH
Input HIGH Current
Other Inputs
S Inputs
20
40
A
VCC = MAX, VIN = 2.7 V
IIH
Other Inputs
S Inputs
0.1
0.2
mA
VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
All Inputs
0.4
mA
VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
30
130
mA
VCC = MAX
ICC
Power Supply Current
Total, Output HIGH
LS257B
LS258B
10
9.0
mA
VCC = MAX
ICC
Total, Output LOW
LS257B
LS258B
16
14
mA
VCC = MAX
Total, Output 3-State
LS257B
LS258B
19
16
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS
(TA = 25
C, VCC = 5.0 V) See SN54LS251 for Waveforms
Symbol
Parameter
Limits
Unit
Test Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
tPLH
tPHL
Propagation Delay, Data to Output
10
12
13
15
ns
Figures 1 & 2
CL = 45 pF
tPLH
tPHL
Propagation Delay, Select to Output
14
14
21
21
ns
Figures 1 & 2
CL = 45 pF
tPZH
Output Enable Time to HIGH Level
20
25
ns
Figures 4 & 5
CL = 45 pF
RL = 667
tPZL
Output Enable Time to LOW Level
20
25
ns
Figures 3 & 5
CL = 45 pF
RL = 667
tPLZ
Output Disable Time to LOW Level
16
25
ns
Figures 3 & 5
CL = 5.0 pF
RL = 667
tPHZ
Output Disable Time from HIGH Level
18
25
ns
Figures 4 & 5
CL = 5.0 pF
RL = 667
5-431
FAST AND LS TTL DATA
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
9.80
3.80
1.35
0.35
0.40
0.19
0.10
0
5.80
0.25
10.00
4.00
1.75
0.49
1.25
0.25
0.25
7
6.20
0.50
0.386
0.150
0.054
0.014
0.016
0.008
0.004
0
0.229
0.010
0.393
0.157
0.068
0.019
0.049
0.009
0.009
7
0.244
0.019
1.27 BSC
0.050 BSC
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. 751B 01 IS OBSOLETE, NEW STANDARD
751B 03.
1
8
9
16
-A-
-B-
P
16 PL
D
-T-
K
C
G
M
R X 45
F
J
8 PL
SEATING
PLANE
Case 751B-03 D Suffix
16-Pin Plastic
SO-16
B
0.25 (0.010)
M
M
T
0.25 (0.010)
B
A
M
S
S
Case 648-08 N Suffix
16-Pin Plastic
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
K
L
M
S
18.80
6.35
3.69
0.39
1.02
0.21
2.80
7.50
0
0.51
19.55
6.85
4.44
0.53
1.77
0.38
3.30
7.74
10
1.01
0.740
0.250
0.145
0.015
0.040
0.008
0.110
0.295
0
0.020
0.770
0.270
0.175
0.021
0.070
0.015
0.130
0.305
10
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L" TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B" DOES NOT INCLUDE MOLD
FLASH.
5. ROUNDED CORNERS OPTIONAL.
6. 648 01 THRU 07 OBSOLETE, NEW STANDARD
648 08.
2.54 BSC
1.27 BSC
0.100 BSC
0.050 BSC
-A-
B
1
8
9
16
F
H
G
D
16 PL
S
C
-T-
SEATING
PLANE
K
J
M
L
T A
0.25 (0.010)
M
M
Case 620-09 J Suffix
16-Pin Ceramic Dual In-Line
MIN
MIN
MAX
MAX
MILLIMETERS
INCHES
DIM
19.05
6.10
0.39
1.40
0.23
0
0.39
19.55
7.36
4.19
0.53
1.77
0.27
5.08
15
0.88
0.750
0.240
0.015
0.055
0.009
0
0.015
0.770
0.290
0.165
0.021
0.070
0.011
0.200
15
0.035
1.27 BSC
2.54 BSC
7.62 BSC
0.050 BSC
0.100 BSC
0.300 BSC
A
B
C
D
E
F
G
J
K
L
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
5. 620 01 THRU 08 OBSOLETE, NEW STANDARD
620 09.
-B-
-A-
16 PL
-T-
C
D
E
F
G
J
K
M
N
SEATING
PLANE
16 PL
L
16
9
1
8
0.25 (0.010)
T A
M
S
0.25 (0.010)
T B
M
S
5-432
FAST AND LS TTL DATA
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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