GENERAL DESCRIPTION

FEATURES

MTD803

3-in-1 Fast Ethernet Controller

USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188

Sales@myson.com.tw

www.myson.com.tw

Rev.1.5 January 2003

page 1 of 43

Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349

· Compliant with PCI bus interface v2.2.
· IEEE802.3 and 802.3u compliant.
· All-in-one solution for easier PCI to ethernet

implementation.

· Supports 10M/100M ethernet with auto-

negotiation capabilities.

· High performance with PCI bus master structure.
· Programmable PCI burst length for low CPU

utilization rate.

· Separate transmit and receive FIFO for best

performance.

· Transmit packet queuing capability for higher

performance.

· Supports both full-duplex and half-duplex mode

operations.

· Supports both IEEE802.3x and Xon/Xoff full

duplex flow control method.

· Contains separate transmit and receive FIFOs.
· Supports Magic packet and Microsoft wake-up

frame filtering.

· Supports ACPI and PCI power management.
· Supports CardBus STSCHG pin and status

changed registers.

· The CardBus CIS can be stored in the EEPROM

for lower cost implementation.

· Supports up to 128K bytes boot ROM or flash

memory without external latch.

· Autoload EEPROM contents after power-on.
· Programmable EEPROM interface.
· 128-pin PQFP package.
· Single 3.3V power supply.

The MTD803 is a highly integrated fast ethernet

controller for PCI interface. The chip contains a PCI
interface block, two large FIFOs (each is 2KiloBytes)
for transmit and receive DMA, IEEE802.3 and 802.3u
compliant MAC and 10M/100M integrated physical
layer (PHY).

It has the capability to auto-negotiate the link

partners for better link configurations. MTD803 has
built-in Wake-Up controller to perform ACPI function,
and the capability of sensing IEEE 802.3x frame to
support Xon/Xoff flow control protocol.

The chip also has EEPROM and BootROM

interface for no glue logic board implementation. For
CardBus applications, the MTD803 supports four
status-changed registers, an interface for accessing
CIS which is stored in EEPROM and STSCHG pin to
reflect general wake-up events.

page 3 of 43

MTD803

PIN CONNECTION DIAGRAM

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

AD2

CBE3

I
D

SEL

VCC

GND

AD2

AD1

VCC

GND

AD1

CBE2

GND

VCC

FRAM

IRDY#

RDY#

DEVSEL

PERR#

CBE1

VCC

GND

AD1

GND

I
A

GND

GDN

GND

I
P

I
N

GND

1
1

GND

BRD4

GND

BRD3

BRD2 / EECK

BRD1 / EEDO

BRD0 / EEDI

XTLP

XTLN

VCC

GND

ISOLATE#

GND

VCC

LEDACT#

LEDDPLX#

LEDSPD#

INTA#

RST#

VCC

CLK

GND

GNT#

REQ#
PME#

AD31
AD30

BRA3
BRA2
BRA1
BRA0
TEST
BRCS#
BRWR#
BRRD#
EECS
WAKE
GND
VCC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
VCC
CBE0#
AD8
AD9
AD10

MTD803F

128-pin QFP

page 4 of 43

MTD803

PIN DESCRIPTION

Name

I/O

Pin

Description

PCI Bus Interface

CLK

122

CLK provides timing reference for the MTD803 related PCI transactions. All

PCI signals except RST#, INTA# and PME# are sampled on the rising edge of

this clock.

RST#

120

When RST# is asserted, all output signals are put into tristate and all open

drain pins are floated. This signal is asynchronous to PCICLK and has to be

asserted for at least 10 active PCI clock cycles.

AD[31:0]

I/O

127-128,1-6,

11-16, 19-20,

34-41, 45-52

32-bit multiplexed address and data bus. A bus transaction consists of an

address phase followed by one or more data phases. During the first cycle in

which the FRAME# is asserted, the AD[31:0] represents the address bus

while it is considered as a data bus during subsequent cycles.

CBE#[3:0]

I/O

7, 21, 31, 42 4-bit multiplexed bus command and byte enables. During the address phase

transaction, CBE# is considered as bus command. On the data phase cycles,

CBE# represents the byte enable signals for PCI data bus.

IDSEL

Used as a chip select during access to the configuration registers.

FRAME#

I/O

Driven by the MTD803 to indicate the start and duration of a transaction. The

FRAME# is deasserted when the master is ready to complete the final data

phase in the transaction.

IRDY#

I/O

During a write transaction, the current bus master asserts IRDY# to indicate

that valid data are being driven onto the PCI bus. During a read transaction,

this signal is asserted to indicate that the master is ready to accept data from

the selected target. Wait states are inserted until both IRDY# and TRDY# are

asserted.

TRDY#

I/O

During a read transaction, the target asserts TRDY# to indicate that valid data

are being driven onto the PCI bus. During a write transaction, this signal is

asserted to indicate that the target is ready to accept data. TRDY# is used in

conjunction with IRDY#. A data phase is completed on any clock when both

IRDY# and TRDY# are asserted.

DEVSEL#

I/O

Asserted by the MTD803 to indicate that the device has decoded the address

as the target of current access. As an input, DEVSEL# indicates whether any

device on the bus has been selected.

STOP#

I/O

Asserted by the MTD803 to disconnect any further transactions. As an input,

DEVSEL# indicates whether any device on the bus or bridge has terminated

the transaction.

INTA#

O/D

119

INTA# is an asynchronous signal which is used to request an interrupt.

PAR

I/O

Encures even parity across AD[31:0] and CBE[3:0], PAR is stable and valid

for one clock after the address phase. During the data phase, PAR is stable

and valid for one clock after either IRDY# (write transaction) or TRDY# (read

transaction) is asserted.

GNT#

124

Asserted by the PCI bus arbiter to indicate that the MTD803 has granted the

bus control authority.

REQ#

O/Z

125

Asserted by the MTD803 to signal bus arbiter that it needs the dedicated

access to the PCI bus.

PERR#

I/O

PERR# is asserted when a data parity error is detected.

PME#

O/D

126

An interrupt signal for the occurence power management event. Asserted by

MTD803 to request a change in the device or system power state.

Network Interface

TXOP

TXON

TP transmit output differential pins.

page 5 of 43

MTD803

RXIP

RXIN

TP receive input differential pins.

XTLP

109

Crystal output pin.

XTLN

110

Crystal input pin.

RBIAS

Bias Resistor Input. This pin should connect to a 10K ohms resistor.

LED Status Output

LEDACT#

116

Activity LED. This signal drives the led light on when detecting activity on MII

interface. A 510 ohm pull-up resistor is required to connect to this pin.

This pin is low if the MTD803 is in link state but no transmit/receive activity.

This pin is high if the MTD803 is not linked on.

This pin flashes if the MTD803 is linked and has transmit or receive activities.

LEDSPD#

118

Pause LED. This signal drives the led light on when detecting transmission is

paused under the condition of receiving a XON frame.

This pin is low if the MTD803 is in 100Mbps mode.

This pin is high if the MTD803 is in 10Mbps mode.

LEDDPLX#

117

Pause LED. This signal drives the led light on when detecting transmission is

paused under the condition of receiving a XON frame.

This pin is low if the MTD803 is in full duplex mode.

This pin is high if the MTD803 in in half duplex mode.

EEPROM and Boot ROM Interface

EECS

Chip select signal for the external EEPROM. EEPROM is used to provide the

configuration data and Ethernet Address. A 100K pull-up resistor is connected

to this pin.

BRRD#

BootROM read signal. Read out the content of BootROM onto the memory

support data bus.

BRWR#

BootROM write signal. When flash memory is used, BRWR# is asserted low

to enable the write action.

BRCS#

Chip select signal for the external EEPROM (BootROM) or flash memory. The

BootROM contains codes that can be usually executed for a system boot

function.

BRD0/EEDI

I/O

108

A multiplexed signal for BootROM data bit 0 and Serial ROM Data input.

BRD1/EEDO

I/O

107

A multiplexed signal for BootROM data bit 1 and Serial ROM Data output.

BRD2/EECK

I/O

106

A multiplexed signal for BootROM data bit 2 and Serial ROM Clock signal.

BRD[7:3]

I/O

100-103, 105 BootROM data bus from bit 3 to bit 7.

BRA[16:0]

81-77, 74-67,

64-61

BootROM address bus from bit 0 to bit 16.

Misc. Interface

WAKEUP/

STSCHG

O/Z

Wakeup Pin/CardBus STSCHG Pin.

In PCI application, this pin is the Wakeup pin to signal the host system of an

wakeup event happened. In Card bus application, this pin is used as the

STSCHG pin to signal the system of any status changed. This pin is enabled

as STSCHG pin if the PME_Enable bit of the power management control

registeris set and the FMR.GWAKE, FMR.WAKE are both set.

ISOLATE#

113

ISOLATION pin. This pin should connect to the PCI stable power signal

(VDD). When PCI Bus is in B3 state, the power signal becomes deasserted,

the ISOLATION pin is active, however. Under this condition, the PCIRST# and

PCICLK are ignored and all the PCI output signals except PME# are isolated

from the PCI Bus.

Power Supply & Ground

Name

I/O

Pin

Description

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