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MTV312M64

8051 Embedded Monitor Controller Flash Type with ISP

sales@myson.com.tw

www.myson.com.tw

Rev. 1.2 March 2003

page 1 of 34

Myson Century, Inc.
Taiwan:
No. 2, Industry East Rd. III,
Science-Based Industrial Park, Hsin-Chu, Taiwan
Tel: 886-3-5784866 Fax: 886-3-5784349

USA:
4020 Moorpark Avenue Suite 115
San Jose, CA, 95117
Tel: 408-243-8388 Fax: 408-243-3188

GENERAL DESCRIPTIONS

The MTV312M micro-controller is an 8051 CPU core
embedded device especially tailored for CRT/LCD
Monitor applications. It includes an 8051 CPU core,
1024-byte SRAM, 14 built-in PWM DACs, VESA
DDC interface, 4-channel A/D converter, and a 64K-
byte internal program Flash-ROM.

FEATURES

· 8051 core, 12MHz operating frequency with double

CPU clock option

· 0.35um process; 5V/3.3V power supply and I/O;

3.3V core operating

· 1024-byte RAM; 64K-byte program Flash-ROM

support In System Programming (ISP)

· Maximum 14 channels of PWM DAC
· Maximum 31 I/O pins
· SYNC processor for composite

separation/insertion, H/V polarity/frequency check
and polarity adjustment

· Built-in low power reset circuit
· Built-in self-test pattern generator with four free-

running timings

· Compliant with VESA DDC1/2B/2Bi/2B+ standard
· Dual slave IIC addresses; H/W auto transfer

DDC1/DDC2x data

· Single master IIC interface for internal device

communication

· Maximum 4-channel 6-bit ADC
· Watchdog timer with programmable interval
· Flash-ROM program code protection selection
· 40-pin DIP, 42-pin SDIP or 44-pin PLCC package

BLOCK DIAGRAM

XFR

P0.0-7

P2.0-3
RD
WR
ALE
INT1

P0.0-7

P2.0-3

ALE

INT1

8051

CORE

P1.0-7

P3.0-2

P3.4-5

RST
X1
X2

ADC

AD0-3

PWM DAC

DA0-13

DDC & IIC

INTERFACE

ISCL

ISDA

HSCL

HSDA

AUXRAM &

DDCRAM

HSYNC

VSYNC

HBLANK

VBLANK

H/VSYNC

CONTROL

P6.0-7

P5.0-6

AUX

I/O

P4.0-2

MTV312M64

Page 2 of 34

PIN CONNECTION

MTV312MN

40-pin

PDIP

DA2/P5.2

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

DA1/P5.1
DA0/P5.0

VDD3

VDD

VSS

X2
X1

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P6.2/AD2/HLFHI

P1.0
P1.1

P3.2/INT0

P1.2
P1.3
P1.4
P1.5
P1.6

HSYNC
DA3/P5.3

VSYNC

DA4/P5.4

DA8/HLFHO
DA9/HALFV

DA5/P5.5

HBLANK/P4.1

DA7/HCLAMP
DA6/P5.6

VBLANK/P4.0

RST

P6.5/DA11
P6.4/DA10

P6.6/DA12

HSCL/P3.0/Rxd

P6.0/AD0
P6.1/AD1

HSDA/P3.1/Txd

P1.7

MTV312MV

44-pin

PLCC

7
8
9
10
11
12
13
14
15
16
17

39
38
37
36
35
34
33
32
31
30
29

P1.6

P1.7

P6.1/AD1

P1.5

P6.0/AD0

HSDA/P3.1/Txd

P1.1

P3.2/INT0

P1.2

P1.3

P1.4

VDD3

DA0/P5.0

DA1/P5.1

DA2/P5.2

VSYNC

HSYNC

DA3/P5.3

DA4/P5.4

DA5/P5.5

RST

VDD

VSS

X2
X1

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P6.2/AD2/HLFHI

P1.0

P6.3/AD3

P6.4/DA10
HSCL/P3.0/Rxd

P6.5/DA11

P6.6/DA12

DA8/HLFHO
DA9/HALFV
HBLANK/P4.1

DA7/HCLAMP
DA6/P5.6

VBLANK/P4.0

P6.7/DA13

MTV312MS

42-pin

SDIP

DA2/P5.2

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

DA1/P5.1
DA0/P5.0

RST

VDD

VSS

VDD3

NC
NC

HSYNC
DA3/P5.3

VSYNC

DA4/P5.4

DA8/HLFHO
DA9/HALFV

DA5/P5.5

HBLANK/P4.1

DA7/HCLAMP
DA6/P5.6

VBLANK/P4.0

42
41

ISDA/P3.4/T0

ISCL/P3.5/T1

STOUT/P4.2

P6.2/AD2/HLFHI

P1.0
P1.1

P3.2/INT0

P1.2
P1.3
P1.4

X2
X1

P6.6/DA12
P6.5/DA11

HSCL/P3.0/Rxd
HSDA/P3.1/Txd

P6.4/DA10

P6.0/AD0

P1.7
P1.6

P6.1/AD1

P1.5

MTV312M64

Page 3 of 34

PIN CONFIGURATION

A "CMOS output pin" means it can sink and drive at least 4mA current. It is not recommended to use such pin
as input function.
A "open drain pin" means it can sink at least 4mA current but only drive 10~20uA to VDD. It can be used as
input or output function and needs an external pull up resistor.
A "8051 standard pin" is a pseudo open drain pin. It can sink at least 4mA current when output is at low level,
and drives at least 4mA current for 160nS when output transits from low to high, then keeps driving at 100uA to
maintain the pin at high level. It can be used as input or output function. It needs an external pull up resistor
when driving heavy load device.

POWER CONFIGURATION

The MTV312M can work on 5V or 3.3V power supply system.
In 5V power system, the VDD pin is connected to 5V power and the VDD3 needs an external capacitor, all

output pins can swing from 0~5V, input pins can accept 0~5V input range. And
ADC conversion range is 5V. However, X1 and X2 pins must be kept below 3.3V.

In 3.3V power system, the VDD and VDD3 are connected to 3.3V power, all output pins swing from 0~3.3V,

HSYNC, VSYNC and open drain pin can accept 0~5V input range, other pins
must be kept below 3.3V. And the ADC conversion range is 3.3V.

8051 Standard Pin

4mA

Output

Data

CMOS Output Pin

Open Drain Pin

2 OSC

period

delay

4mA

10uA

Output

Data

120uA

4mA

Input

Data

No Current

4mA

Output

Data

Input

Data

3.3V

VDD

VDD3

MTV312M in
3.3V System

10u

MTV312M in

5V System

VDD

VDD3

MTV312M64

Page 4 of 34

PIN DESCRIPTION

PIN NO.

Name

40 42

Type Description

VDD3

3.3V core power

VDD

5V or 3.3V Positive Power Supply

VSS 6

Ground

X2 7

Oscillator

output

X1 8

Oscillator

input

RST

Active high reset

DA0/P5.0

I/O

PWM DAC output / General purpose I/O (CMOS)

DA1/P5.1

I/O

PWM DAC output / General purpose I/O (CMOS)

DA2/P5.2

I/O

PWM DAC output / General purpose I/O (CMOS)

DA3/P5.3

I/O

PWM DAC output / General purpose I/O (CMOS)

DA4/P5.4

I/O

PWM DAC output / General purpose I/O (CMOS)

DA5/P5.5

I/O

PWM DAC output / General purpose I/O (CMOS)

DA6/P5.6

I/O

PWM DAC output / General purpose I/O (CMOS)

DA7/HCLAMP

PWM DAC output / Hsync clamp pulse output (CMOS)

DA8/HLFHO

PWM DAC output / Hsync half freq. Output (open drain)

DA9/HALFV

PWM DAC output / Vsync half freq. Output (open drain)

HSCL/P3.0/Rxd

I/O

Slave IIC clock / General purpose I/O / Rxd (open drain)

HSDA/P3.1/Txd

I/O

Slave IIC data / General purpose I/O / Txd (open drain)

P3.2/INT0

I/O

General purpose I/O / INT0 (8051 standard)

ISDA/P3.4/T0

I/O

Master IIC data / General purpose I/O / T0 (open drain)

ISCL/P3.5/T1

I/O

Master IIC clock / General purpose I/O / T1 (open drain)

P1.0

I/O