1999,2001
MOS FIELD EFFECT TRANSISTOR
2SK3294
SWITCHING
N-CHANNEL POWER MOS FET
Document No. D14061EJ1V0DS00 (1st edition)
Date Published August 2001 NS CP (K)
Printed in Japan
DATA SHEET
DESCRIPTION
The 2SK3294 is N-channel MOS FET device that features a
low on-state resistance and excellent switching characteristics,
and designed for high voltage applications such as DC/DC
converter, actuator driver.
FEATURES
Gate voltage rating 30 V
Low on-state resistance
R
DS(on)
= 160 m
MAX. (V
GS
= 10 V, I
D
= 10 A)
Low input capacitance
C
iss
= 1500 pF TYP. (V
DS
= 10 V, V
GS
= 0 V)
Avalanche capability rated
Built-in gate protection diode
Surface mount device available
ABSOLUTE MAXIMUM RATINGS (T
A
= 25C)
Drain to Source Voltage (V
GS
= 0 V)
V
DSS
250
V
Gate to Source Voltage (V
DS
= 0 V)
V
GSS
30
V
Drain Current (DC) (T
C
= 25C)
I
D(DC)
20
A
Drain Current (Pulse)
Note1
I
D(pulse)
60
A
Total Power Dissipation (T
C
= 25C)
P
T1
100
W
Total Power Dissipation (T
A
= 25C)
P
T2
1.5
W
Channel Temperature
T
ch
150
C
Storage Temperature
T
stg
-
55 to +150
C
Single Avalanche Current
Note2
I
AS
20
A
Single Avalanche Energy
Note2
E
AS
150
mJ
Notes 1. PW
10
s, Duty Cycle
1%
2. Starting T
ch
= 25C, V
DD
= 150 V, R
G
= 25
, V
GS
= 20 V
0 V
ORDERING INFORMATION
PART NUMBER
PACKAGE
2SK3294
TO-220AB
2SK3294-S
TO-262
2SK3294-ZJ
TO-263(MP-25ZJ)
(TO-220AB)
(TO-262)
(TO-263)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Data Sheet D14061EJ1V0DS
2
2SK3294
ELECTRICAL CHARACTERISTICS (T
A
= 25C)
Characteristics
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Zero Gate Voltage Drain Current
I
DSS
V
DS
= 250 V, V
GS
= 0 V
100
A
Gate Leakage Current
I
GSS
V
GS
=
30 V, V
DS
= 0 V
10
A
Gate Cut-off Voltage
V
GS(off)
V
DS
= 10 V, I
D
= 1 mA
2.5
4.5
V
Forward Transfer Admittance
| y
fs
|
V
DS
= 10 V, I
D
= 10 A
6.0
S
Drain to Source On-state Resistance
R
DS(on)
V
GS
= 10 V, I
D
= 10 A
120
160
m
Input Capacitance
C
iss
V
DS
= 10 V
1500
pF
Output Capacitance
C
oss
V
GS
= 0 V
360
pF
Reverse Transfer Capacitance
C
rss
f = 1 MHz
220
pF
Turn-on Delay Time
t
d(on)
V
DD
= 125 V , I
D
= 10 A
24
ns
Rise Time
t
r
V
GS
= 10 V
78
ns
Turn-off Delay Time
t
d(off)
R
G
= 10
110
ns
Fall Time
t
f
60
ns
Total Gate Charge
Q
G
V
DD
= 200 V
57
nC
Gate to Source Charge
Q
GS
V
GS
= 10 V
8
nC
Gate to Drain Charge
Q
GD
I
D
= 20 A
36
nC
Body Diode Forward Voltage
V
F(S-D)
I
F
= 20 A, V
GS
= 0 V
1.0
V
Reverse Recovery Time
t
rr
I
F
= 20 A, V
GS
= 0 V
340
ns
Reverse Recovery Charge
Q
rr
di/dt = 50 A/
s
2.1
C
TEST CIRCUIT 1 AVALANCHE CAPABILITY
R
G
= 25
50
PG.
L
V
DD
V
GS
= 20 V
0 V
BV
DSS
I
AS
I
D
V
DS
Starting T
ch
V
DD
D.U.T.
TEST CIRCUIT 3 GATE CHARGE
TEST CIRCUIT 2 SWITCHING TIME
PG.
R
G
0
V
GS
D.U.T.
R
L
V
DD
= 1 s
Duty Cycle
1%
V
GS
Wave Form
I
D
Wave Form
V
GS
10%
90%
V
GS
10%
0
I
D
90%
90%
t
d(on)
t
r
t
d(off)
t
f
10%
I
D
0
t
on
t
off
PG.
50
D.U.T.
R
L
V
DD
I
G
= 2 mA
Data Sheet D14061EJ1V0DS
3
2SK3294
TYPICAL CHARACTERISTICS (T
A
= 25C)
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
V
DS
- Drain to Source Voltage - V
I
D
- Drain Current - A
20
10
20
30
40
50
60
0
15
0
5
10
V
GS
= 10 V
Pulsed
100
0
2
4
6
8
10
12
FORWARD TRANSFER CHARACTERISTICS
I
D
- Drain Current - A
V
GS
- Gate to Source Voltage - V
T
ch
= 125C
75C
25C
-
25C
V
DS
= 10 V
Pulsed
0.001
0.01
0.1
1
10
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
T
ch
- Channel Temperature - C
V
GS(off)
- Gate Cut-off Voltage - V
V
DS
=
10
V
I
D
=
1
mA
-
50
0
150
50
100
5.0
4.0
3.0
2.0
1.0
-
25
25
75
125
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
|y
fs
| - Forward Transfer Admittance - S
I
D
- Drain Current - A
1
1
10
10
100
V
DS
= 10 V
Pulsed
T
ch
=
-
25C
25C
75C
125C
0.01
0.1
100
0.01
0.1
Pulsed
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
V
GS
- Gate to Source Voltage - V
R
DS(on)
- Drain to Source On-state Resistance -m
0
8
16
20
4
12
I
D
= 20 A
10 A
500
400
300
200
100
0
4 A
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
I
D
- Drain Current - A
R
DS(on)
- Drain to Source On-state Resistance - m
500
400
300
100
10
100
0.1
0
1
200
V
GS
= 10 V
Pulsed
Data Sheet D14061EJ1V0DS
4
2SK3294
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
50
150
R
DS (on)
- Drain to Source On-state Resistance - m
0
100
-
50
T
ch
- Channel Temperature - C
V
GS
= 10 V
Pulsed
10 A
I
D
= 20 A
400
300
200
100
0
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
V
SD
- Source to Drain Voltage - V
I
SD
- Diode Forward Current - A
0.0
0.5
1.0
1.5
V
GS
= 10 V
0 V
Pulsed
100
10
1
0.1
0.01
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
V
DS
- Drain to Source Voltage - V
C
iss
, C
oss
, C
rss
- Capacitance - pF
0.1
100
1000
1
10
100
V
GS
=
0
V
f
=
1
MHz
C
iss
C
oss
C
rss
10
10000
1000
SWITCHING CHARACTERISTICS
I
D
- Drain Current - A
t
d(on)
, t
r
, t
d(off)
, t
f
- Switching Time - ns
1
10
100
1000
0.1
1
10
100
V
DD
=
125 V
V
GS
=
10 V
R
G
=
10
t
d(off)
t
d(on)
t
f
t
r
REVERSE RECOVERY TIME vs.
DRAIN CURRENT
I
D
- Drain Current - A
t
rr
- Reverse Recovery Time - ns
0.1
10
1
10
100
100
1
1000
di/dt
=
50
A/
s
V
GS
=
0
V
V
GS
- Gate to Source Voltage - V
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
Q
G
- Gate Charge - nC
V
DS
- Drain to Source Voltage - V
0
10
20
30
40
50
60
V
GS
V
DS
360
300
240
180
120
60
0
12
10
8
6
4
2
0
I
D
= 20 A
V
DD
= 200 V
125 V
50 V
Data Sheet D14061EJ1V0DS
5
2SK3294
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
T
ch
- Channel Temperature - C
dT - Percentage of Rated Power - %
0
20
40
60
80
100
120
140
160
20
40
60
80
100
0
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
T
C
- Case Temperature - C
P
T
- Total Power Dissipation - W
0
20
40
60
80
100
120
140
160
140
120
100
80
60
40
20
0
FORWARD BIAS SAFE OPERATING AREA
10
100
1000
I
D
- Drain Current - A
1
V
DS
- Drain to Source Voltage - V
100
10
1
0.1
100
s
10
ms
PW
= 10
s
R
DS
(on)
Limited
I
D(pulse)
I
D(DC)
3 ms
Po
wer Dissipation Limited
T
C
= 25C
Single Pulse
DC
1ms
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
PW - Pulse Width - sec
r
th
(t) - Transient Thermal Resistance -
C/
W
1
0.01
0.1
10
100
1 m
10 m
100 m
1
10
1000
100
100
Single Pulse
10
R
th(ch-A)
= 83.3C/W
R
th(ch-C)
= 1.25C/W
Data Sheet D14061EJ1V0DS
6
2SK3294
0.01
10
0.1
1
10
100
1
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
L - Inductive Load - mH
I
AS
- Single Avalanche Current - A
I
AS
=
20
A
E
AS
=
150 mJ
V
DD
=
150
V
V
GS
=
20
V
0
V
R
G
=
25
SINGLE AVALANCHE ENERGY
DERATING FACTOR
75
150
125
80
40
0
Starting T
ch
- Starting Channel Temperature - C
Energy Derating Factor - %
50
100
25
100
60
20
V
DD
=
150
V
R
G
=
25
V
GS
=
20
V
0
V
I
AS
20
A
Data Sheet D14061EJ1V0DS
7
2SK3294
PACKAGE DRAWINGS (Unit: mm)
1)TO-220AB (MP-25)
2)TO-262
3)TO-263 (MP-25ZJ)
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When
this device actually used, an additional protection circuit is externally required if a voltage exceeding the rated
voltage may be applied to this device.
EQUIVALENT CIRCUIT
Source
Body
Diode
Gate
Protection
Diode
Gate
Drain
4.8 MAX.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
1 2 3
10.6 MAX.
10.0 TYP.
3.60.2
4
3.00.3
1.30.2
0.750.1
2.54 TYP.
2.54 TYP.
5.9 MIN.
6.0 MAX.
15.5 MAX.
12.7 MIN.
1.30.2
0.50.2
2.80.2
4.8 MAX.
1.Gate
2.Drain
3.Source
4.Fin (Drain)
1
2
3
10 TYP.
1.30.2
0.750.3
2.54 TYP.
2.54 TYP.
8.5
0.2
12.7 MIN.
1.30.2
0.50.2
2.80.2
1.00
.
5
4
1.40.2
1.00.5
2.54 TYP.
2.54 TYP.
8.50.2
1
2
3
5.70.4
4
4.8 MAX.
1.30.2
0.50.2
1.Gate
2.Drain
3.Source
4.Fin (Drain)
0.70.2
10 TYP.
0.5R TYP.
0.8R TYP.
2.80.2
2SK3294
M8E 00. 4
The information in this document is current as of August, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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