The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
2001
Document No. M15794EJ2V0DS00 (2nd edition)
Date Published January 2002 NS CP (K)
Printed in Japan
MOS INTEGRATED CIRCUIT
PD4616112-X
16M-BIT CMOS MOBILE SPECIFIED RAM
1M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
DATA SHEET
The mark
5
shows major revised points.
Description
The
PD4616112-X is a high speed, low power, 16,777,216 bits (1,048,576 words by 16 bits) CMOS mobile
specified RAM featuring low power static RAM compatible function and pin configuration.
The
PD4616112-X is fabricated with advanced CMOS technology using one-transistor memory cell.
The
PD4616112-X is packed in 48-pin TAPE FBGA.
Features
1,048,576 words by 16 bits organization
Fast access time: 85, 95 ns (MAX.)
Byte data control: /LB (I/O0 - I/O7), /UB (I/O8 - I/O15)
Low voltage operation: V
CC
= 2.6 to 3.1 V
Operating ambient temperature: T
A
= 25 to +85 C
Output Enable input for easy application
Chip Enable input: /CS pin
Standby Mode input: MODE pin
Standby Mode1: Normal standby (Memory cell data hold valid)
Standby Mode2: Memory cell data hold invalid
Product name
Access time
Operating supply
Operating ambient
Supply current
ns (MAX.)
Voltage
temperature
At operating
At standby
C
mA (MAX.)
A (MAX.)
PD4616112-BxxLX
85, 95
2.6 to 3.1
25 to +85
35
70 / 10
Data Sheet M15794EJ2V0DS
5
PD4616112-X
Truth Table
/CS
MODE
/OE
/WE
/LB
/UB
Mode
I/O
Supply current
I/O0 - I/O7
I/O8 - I/O15
H
H
Not selected (Standby Mode 1)
High impedance
High impedance
I
SB1
H
L
Not selected (Standby Mode 2)
High impedance
High impedance
I
SB2
L
H
H
H
Output disable
High impedance
High impedance
I
CCA
L
H
L
L
Word read
D
OUT
D
OUT
L
H
Lower byte read
D
OUT
High impedance
H
L
Upper byte read
High impedance
D
OUT
H
H
Output disable
High impedance
High impedance
L
L
L
Word write
D
IN
D
IN
L
H
Lower byte write
D
IN
High impedance
H
L
Upper byte write
High impedance
D
IN
H
H
Write abort
High impedance
High impedance
Caution MODE pin must be fixed to High except Standby Mode 2.
Remark
: V
IH
or V
IL
Initialization
The
PD4616112-X is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, before turning on the power, a 200
s or longer wait time must precede any signal
toggling.
(2) After the wait time, read operation must be performed at least 3 times. After that, it can be normal operation.
Initialization Timing Chart
V
CC
V
CC
(MIN.)
V
IH
(MIN.)
V
IH
(MIN.)
t
RC
t
CP
200 s
Address (Input)
/CS (Input)
MODE (Input)
Wait Time
Power On
Read Operation 3 times
Normal
Operation
Cautions 1. Following power application, make MODE and /CS high level during the wait time interval.
2. Following power application, make MODE high level during the wait time and three read
operations.
3. The read operation must satisfy the specs described on page 10 (Read Cycle (B Version)).
4. The address is don't care (V
IH
or V
IL
) during read operation.
5. Read operation must be executed with toggled the /CS pin.
6. To prevent bus contention, it is recommended to set /OE to high level.
7. Do not input data to the I/O pins if /OE is low level during a read operation.