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1999
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4564EC727
64M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Document No.
M14461EJ2V0DS00 (2nd edition)
Date Published
February 2000 NS CP(K)
Printed in Japan
The mark
5
5
5
5
shows major revised points.
Description
The MC-4564EC727 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
128 M SDRAM:
PD45128441 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
67,108,864 words by 72 bits organization (ECC type)
Clock frequency and access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
Module type
MC-4564EC727EF-A75
CL = 3
133 MHz
5.4 ns
PC133 Registered DIMM
CL = 2
100 MHz
6.0 ns
Rev. 1.0 Compliant
MC-4564EC727PF-A75
CL = 3
133 MHz
5.4 ns
CL = 2
100 MHz
6.0 ns
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
Programmable burst-length
(1, 2, 4, 8 and Full Page)
Programmable wrap sequence (Sequential
/
Interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
All DQs have 10
10
% of series resistor
Single 3.3
V
0.3
V power supply
LVTTL compatible
4,096 refresh cycles/64
ms
Burst termination by Burst Stop command and Precharge command
168-pin dual in-line memory module (Pin pitch = 1.27
mm)
Registered type
Serial PD
Stacked monolithic technology
5
5
5
Data Sheet M14461EJ2V0DS00
3
MC-4564EC727
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
V
SS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
CB5
V
SS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
/CS1
/RAS
V
SS
A1
A3
A5
A7
A9
BA0
(A13)
A11
Vcc
CLK1
NC
V
SS
CKE0
/CS3
DQMB6
DQMB7
NC
Vcc
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
SA0
SA1
SA2
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
V
SS
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
V
SS
A0
A2
A4
A6
A8
A10
BA1(A12)
Vcc
Vcc
CLK0
V
SS
NC
/CS2
DQMB2
DQMB3
NC
Vcc
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
NC
WP
SDA
SCL
Vcc
DQ46
DQ47
CB4
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A9, A11]
BA0
(A13), BA1
(A12)
: SDRAM Bank Select
DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs
CLK0 - CLK3
: Clock Input
CKE0
: Clock Enable Input
WP
: Write Protect
/CS0 - /CS3
: Chip Select Input
/RAS
: Row Address Strobe
/CAS
: Column Address Strobe
/WE
: Write Enable
DQMB0 - DQMB7
: DQ Mask Enable
SA0 - SA2
: Address Input for EEPROM
SDA
: Serial Data I/O for PD
SCL
: Clock Input for PD
V
CC
: Power Supply
V
SS
: Ground
REGE
: Register / Buffer Enable
NC
: No Connection
/xxx indicates active low signal.
Data Sheet M14461EJ2V0DS00
5
MC-4564EC727
(2/2)
Register 1
A1
A3
A5
A7
A9
/RAS
/CAS
BA0
/CS1
DQMB4
DQMB5
REGE
R1A1: D0-D4, D9-D12, D18-D22, D27-D30
R2A1: D5-D8, D13-D17, D23-D26, D31-D35
R1A3: D0-D4, D9-D12, D18-D22, D27-D30
R2A3: D5-D8, D13-D17, D23-D26, D31-D35
R1A5: D0-D4, D9-D12, D18-D22, D27-D30
R2A5: D5-D8, D13-D17, D23-D26, D31-D35
R1A7: D0-D4, D9-D12, D18-D22, D27-D30
R2A7: D5-D8, D13-D17, D23-D26, D31-D35
R1A9: D0-D4, D9-D12, D18-D22, D27-D30
R2A9: D5-D8, D13-D17, D23-D26, D31-D35
R1RAS: D0-D4, D9-D12, D18-D22, D27-D30
R2RAS: D5-D8, D13-D17, D23-D26, D31-D35
R1CAS: D0-D4, D9-D12, D18-D22, D27-D30
R2CAS: D5-D8, D13-D17, D23-D26, D31-D35
R1BA0: D0-D4, D9-D12, D18-D22, D27-D30
RCS1
RDQMB4
RDQMB5
/LE
Register 2
A0
A2
A4
A6
A8
A10
/WE
BA0
/CS0
DQMB0
DQMB1
R1A0: D0-D4, D9-D12, D18-D22, D27-D30
R2A0: D5-D8, D13-D17, D23-D26, D31-D35
R1A2: D0-D4, D9-D12, D18-D22, D27-D30
R2A2: D5-D8, D13-D17, D23-D26, D31-D35
R1A4: D0-D4, D9-D12, D18-D22, D27-D30
R2A4: D5-D8, D13-D17, D23-D26, D31-D35
R1A6: D0-D4, D9-D12, D18-D22, D27-D30
R2A6: D5-D8, D13-D17, D23-D26, D31-D35
R1A8: D0-D4, D9-D12, D18-D22, D27-D30
R2A8: D5-D8, D13-D17, D23-D26, D31-D35
R1A10: D0-D4, D9-D12, D18-D22, D27-D30
R2A10: D5-D8, D13-D17, D23-D26, D31-D35
R1WE: D0-D4, D9-D12, D18-D22, D27-D30
R2WE: D5-D8, D13-D17, D23-D26, D31-D35
R2BA0: D5-D8, D13-D17, D23-D26, D31-D35
RCS0
RDQMB4
RDQMB5
/LE
Register 3
A11
BA1
CKE0
/CS2
/CS3
DQMB2
DQMB3
DQMB6
DQMB7
R1A11: D0-D4, D9-D12, D18-D22, D27-D30
R2A11: D5-D8, D13-D17, D23-D26, D31-D35
R1BA1: D0-D4, D9-D12, D18-D22, D27-D30
R2BA1: D5-D8, D13-D17, D23-D26, D31-D35
R1CKE0: D0-D2, D9-D10, D18-D20, D27-D28
R2CKE0: D5-D6, D14-D15, D23-D24, D32-D33
R3CKE0: D3-D4, D11-D13, D21-D22, D29-D31
R4CKE0: D7-D8, D16-D17, D23-D24, D34-D35
RCS2
RCS3
RDQMB2
RDQMB3
RDQMB6
RDQMB7
/LE
10 k
Remarks 1. The value of all resistors of DQs is 10
.
2. D0 D35:
PD45128441 (8 M words
4 bits
4 banks)
3. REGE
V
IL
: Buffer mode
REGE
V
IH
: Register mode
4. Register: SN74AVC16834DGG
PLL: HD74CDCF2510B, IDTCSP2510C
5
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