Document Outline

• COVER
• INTRODUCTION
• CHAPTER 1 GENERAL
  • 1.1 Features
  • 1.2 Applications
  • 1.3 Ordering Information
  • 1.4 Pin Configuration (Top View)
    • 1.4.1 Pin configuration of uPD789426, 789436 Subseries (Top view)
    • 1.4.2 Pin configuration of uPD789446, 789456 Subseries (Top view)
  • 1.5 78K/0S Series Lineup
  • 1.6 Block Diagram
    • 1.6.1 Block diagram of uPD789426, 789436 Subseries
    • 1.6.2 Block diagram of uPD789446, 789456 Subseries
  • 1.7 Overview of Functions
• CHAPTER 2 PIN FUNCTIONS
  • 2.1 List of Pin Functions
  • 2.2 Description of Pin Functions
    • 2.2.1 P00 to P03 (Port 0)
    • 2.2.2 P10, P11 (Port 1)
    • 2.2.3 P20 to P26 (Port 2)
    • 2.2.4 P30 to P33 (Port 3)
    • 2.2.5 P50 to P53 (Port 5)
    • 2.2.6 P60 to P65 (Port 6)
    • 2.2.7 P70 to P72 (Port 7)
    • 2.2.8 P80, P81 (Port 8)
    • 2.2.9 P90 to P97 (Port 9)
    • 2.2.10 S0 to S14
    • 2.2.11 COM0 to COM3
    • 2.2.12 VLC0 to VLC2
    • 2.2.13 CAPH, CAPL
    • 2.2.14 #RESET
    • 2.2.15 X1, X2
    • 2.2.16 XT1, XT2
    • 2.2.17 VDD
    • 2.2.18 VSS
    • 2.2.19 VPP (uPD78F9436, 78F9456 only)
    • 2.2.20 IC (mask ROM version only)
  • 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
• CHAPTER 3 CPU ARCHITECTURE
  • 3.1 Memory Space
    • 3.1.1 Internal program memory space
    • 3.1.2 Internal data memory (internal high-speed RAM) space
    • 3.1.3 Special function register (SFR) area
    • 3.1.4 Data memory addressing
  • 3.2 Processor Registers
    • 3.2.1 Control registers
    • 3.2.2 General-purpose registers
    • 3.2.3 Special function registers (SFRs)
  • 3.3 Instruction Address Addressing
    • 3.3.1 Relative addressing
    • 3.3.2 Immediate addressing
    • 3.3.3 Table indirect addressing
    • 3.3.4 Register addressing
  • 3.4 Operand Address Addressing
    • 3.4.1 Direct addressing
    • 3.4.2 Short direct addressing
    • 3.4.3 Special function register (SFR) addressing
    • 3.4.4 Register addressing
    • 3.4.5 Register indirect addressing
    • 3.4.6 Based addressing
    • 3.4.7 Stack addressing
• CHAPTER 4 PORT FUNCTIONS
  • 4.1 Port Functions
  • 4.2 Port Configuration
    • 4.2.1 Port 0
    • 4.2.2 Port 1
    • 4.2.3 Port 2
    • 4.2.4 Port 3
    • 4.2.5 Port 5
    • 4.2.6 Port 6
    • 4.2.7 Port 7
    • 4.2.8 Port 8 (uPD789426, 789436 Subseries only)
    • 4.2.9 Port 9 (uPD789426, 789436 Subseries only)
  • 4.3 Registers Controlling Port Function
  • 4.4 Port Function Operation
    • 4.4.1 Writing to I/O port
    • 4.4.2 Reading from I/O port
    • 4.4.3 Arithmetic operation of I/O port
• CHAPTER 5 CLOCK GENERATOR
  • 5.1 Clock Generator Functions
  • 5.2 Clock Generator Configuration
  • 5.3 Registers Controlling Clock Generator
  • 5.4 System Clock Oscillators
    • 5.4.1 Main system clock oscillator
    • 5.4.2 Subsystem clock oscillator
    • 5.4.3 Divider circuit
    • 5.4.4 When no subsystem clock is used
  • 5.5 Clock Generator Operation
  • 5.6 Changing Setting of System Clock and CPU Clock
    • 5.6.1 Time required for switching between system clock and CPU clock
    • 5.6.2 Switching between system clock and CPU clock
• CHAPTER 6 16-BIT TIMER
  • 6.1 16-Bit Timer Functions
  • 6.2 16-Bit Timer Configuration
  • 6.3 Registers Controlling 16-Bit Timer
  • 6.4 16-Bit Timer Operation
    • 6.4.1 Operation as timer interrupt
    • 6.4.2 Operation as timer output
    • 6.4.3 Capture operation
    • 6.4.4 16-bit timer counter 90 readout
    • 6.4.5 Buzzer output operation
  • 6.5 Notes on Using 16-Bit Timer
• CHAPTER 7 8-BIT TIMER
  • 7.1 8-Bit Timer Functions
  • 7.2 8-Bit Timer Configuration
  • 7.3 Registers Controlling 8-Bit Timer
  • 7.4 8-Bit Timer Operation
    • 7.4.1 Operation as 8-bit timer counter
    • 7.4.2 Operation as 16-bit timer counter
    • 7.4.3 Operation as carrier generator
    • 7.4.4. PWM free-running mode operation (timer 50)
    • 7.4.5 Operation as PWM output (timer 60)
  • 7.5 Notes on Using 8-Bit Timer
• CHAPTER 8 WATCH TIMER
  • 8.1 Watch Timer Functions
  • 8.2 Watch Timer Configuration
  • 8.3 Watch Timer Control Register
  • 8.4 Watch Timer Operation
    • 8.4.1 Operation as watch timer
    • 8.4.2 Operation as interval timer
• CHAPTER 9 WATCHDOG TIMER
  • 9.1 Watchdog Timer Functions
  • 9.2 Watchdog Timer Configuration
  • 9.3 Watchdog Timer Control Registers
  • 9.4 Watchdog Timer Operation
    • 9.4.1 Operation as watchdog timer
    • 9.4.2 Operation as interval timer
• CHAPTER 10 8-BIT A/D CONVERTER (uPD789426 AND 789446 SUBSERIES)
  • 10.1 8-Bit A/D Converter Functions
  • 10.2 8-Bit A/D Converter Configuration
  • 10.3 8-Bit A/D Converter Control Registers
  • 10.4 8-Bit A/D Converter Operation
    • 10.4.1 Basic operation of 8-bit A/D converter
    • 10.4.2 Input voltage and conversion result
    • 10.4.3 Operation mode of 8-bit A/D converter
  • 10.5 Cautions Related to 8-Bit A/D Converter
• CHAPTER 11 10-BIT A/D CONVERTER (uPD789436 AND 789456 SUBSERIES)
  • 11.1 10-Bit A/D Converter Functions
  • 11.2 10-Bit A/D Converter Configuration
  • 11.3 10-Bit A/D Converter Control Registers
  • 11.4 10-Bit A/D Converter Operation
    • 11.4.1 Basic operation of 10-bit A/D converter
    • 11.4.2 Input voltage and conversion result
    • 11.4.3 Operation mode of 10-bit A/D converter
  • 11.5 Cautions Related to 10-Bit A/D Converter
• CHAPTER 12 SERIAL INTERFACE 20
  • 12.1 Serial Interface 20 Functions
  • 12.2 Serial Interface 20 Configuration
  • 12.3 Serial Interface 20 Control Registers
  • 12.4 Serial Interface 20 Operation
    • 12.4.1 Operation stop mode
    • 12.4.2 Asynchronous serial interface (UART) mode
    • 12.4.3 3-wire serial I/O mode
• CHAPTER 13 LCD CONTROLLER/DRIVER
  • 13.1 LCD Controller/Driver Functions
  • 13.2 LCD Controller/Driver Configuration
  • 13.3 Registers Controlling LCD Controller/Driver
  • 13.4 Setting LCD Controller/Driver
  • 13.5 LCD Display Data Memory
  • 13.6 Common and Segment Signals
  • 13.7 Display Modes
    • 13.7.1 Three-time slot display example
    • 13.7.2 Four-time slot display example
• CHAPTER 14 INTERRUPT FUNCTIONS
  • 14.1 Interrupt Function Types
  • 14.2 Interrupt Sources and Configuration
  • 14.3 Registers Controlling Interrupt Function
  • 14.4 Interrupt Servicing Operation
    • 14.4.1 Non-maskable interrupt request acknowledgment operation
    • 14.4.2 Maskable interrupt request acknowledgment operation
    • 14.4.3 Multiple interrupt servicing
    • 14.4.4 Putting interrupt requests on hold
• CHAPTER 15 STANDBY FUNCTION
  • 15.1 Standby Function and Configuration
    • 15.1.1 Standby function
    • 15.1.2 Register controlling standby function
  • 15.2 Standby Function Operation
    • 15.2.1 HALT mode
    • 15.2.2 STOP mode
• CHAPTER 16 RESET FUNCTION
• CHAPTER 17 uPD78F9436, 78F9456
  • 17.1 Flash Memory Programming
    • 17.1.1 Selecting communication mode
    • 17.1.2 Function of flash memory programming
    • 17.1.3 Flashpro III connection example
    • 17.1.4 Example of settings for Flashpro III (PG-FP3)
• CHAPTER 18 MASK OPTIONS
• CHAPTER 19 INSTRUCTION SET
  • 19.1 Operation
    • 19.1.1 Operand identifiers and description methods
    • 19.1.2 Description of �Operation� column
    • 19.1.3 Description of �Flag� column
  • 19.2 Operation List
  • 19.3 Instructions Listed by Addressing Type
• APPENDIX A DEVELOPMENT TOOLS
  • A.1 Language Processing Software
  • A.2 Flash Memory Writing Tools
  • A.3 Debugging Tools
    • A.3.1 Hardware
    • A.3.2 Software
• APPENDIX B EMBEDDED SOFTWARE
• APPENDIX C REGISTER INDEX
  • C.1 Register Index (Alphabetic Order of Register Name)
  • C.2 Register Index (Alphabetic Order of Register Symbol)