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Электронный компонент: uPD16431AGC-7ET

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MOS INTEGRATED CIRCUIT
The
PD16431A is an LCD controller/driver that enables display of segment type LCDs of 1/2, 1/3, or 1/4 duty
cycle. This controller/driver has 56 segment output lines of which eight can also be used as LED output lines.
Because the LCD driver contained in the
PD16431A has separate logic and power supply, up to 6.5 V of LCD
drive voltage can be set. In addition, key source output lines for key scanning and key input data lines are
also provided, so that the
PD16431A is ideal for applications in the front panel of an automobile stereo system.
FEATURES
Various display modes
1/2 duty: 112 segment outputs or 96 segment outputs + 8 LED outputs
1/3 duty: 168 segment outputs or 144 segment outputs + 8 LED outputs
1/4 duty: 224 segment outputs or 192 segment outputs + 8 LED outputs
Key scan circuit (key source outputs are shared with LCD driver outputs)
Independent LCD driver power supply V
LCD
(can be set to V
DD
to 6.5 V)
Serial data input/output (SCK, STB, DATA)
On-chip oscillator incorporated
Power-ON reset circuit
ORDERING INFORMATION
Part Number
Package
PD16431AGC-7ET
80-pin plastic QFP (0.65 pitch, 14
14)
PD16431A
1/2, 1/3, 1/4-DUTY LCD CONTROLLER/DRIVER
Printed in Japan
Document No. IC-3414
(O.D. No. IC-8885)
Date Published January 1995 P
1995
DATA SHEET
PD16431A
2
BLOCK DIAGRAM
S
1
/KS
1
S
1
/KS
2
S
8
/KS
8
S
48
Segment driver
48
56
Level shifter (56)
56
Selector circuit
56
Output latch (56
4)
56
56-bit shift register
S
56
/LED
8
8
S
49
/LED
1
LED
driver
OE
8
Common
driver
COM
1
COM
4
4
4
Level
shifter
OE
LCD/LED
SYNC
Timing
generator
OSC
2
Read
address
I/O
control
Write address
Key counter
8-bit
shift
register 8
Command
decoder
Key counter
OSC
IN
OSC
OUT
key
1
key
4
Key latch S/R
KEY REQ
CLK
DATA
STB
V
DD
V
SS
V
LCD
V
LC1
V
LC2
V
LC3
PD16431A
3
PIN CONFIGURATION
SEG
36
SEG
35
SEG
34
SEG
33
SEG
32
SEG
31
SEG
30
SEG
29
SEG
28
SEG
27
SEG
26
SEG
25
SEG
24
SEG
23
SEG
22
SEG
21
SEG
20
SEG
19
SEG
18
SEG
17
SEG
16
SEG
15
SEG
14
SEG
13
SEG
12
SEG
11
SEG
10
SEG
9
SEG
8
/KS
8
SEG
7
/KS
7
SEG
6
/KS
6
SEG
5
/KS
5
SEG
4
/KS
4
SEG
3
/KS
3
SEG
2
/KS
2
SEG
1
/KS
1
COM
4
COM
3
COM
2
COM
1
40
21
41
60
V
SS
KEY
1
KEY
2
KEY
3
KEY
4
KEY REQ
SCK
DATA
STB
LCD/LED
OE
OSC
IN
OSC
OUT
SYNC
V
DD
V
LCD
V
LC1
V
LC2
V
LC3
V
EE
61
80
20
1
SEG
37
SEG
38
SEG
39
SEG
40
SEG
41
SEG
42
SEG
43
SEG
44
SEG
45
SEG
46
SEG
47
SEG
48
SEG
49
/LED
1
SEG
50
/LED
2
SEG
51
/LED
3
SEG
52
/LED
4
SEG
53
/LED
5
SEG
54
/LED
6
SEG
55
/LED
7
SEG
56
/LED
8
Note
Though V
SS
and V
EE
are internally connected, be sure to connect all the power supply pins (V
DD
, V
SS
,
V
LCD
, and V
EE
).
PD16431A
4
PIN FUNCTIONS
Symbol
SEG
1
/KS
1
to
SEG
8
/KS
8
SEG
9
to SEG
48
SEG
49
/LED
1
to
SEG
56
/LED
8
COM
1
to COM
4
SCK
DATA
STB
LCD/LED
OE
Note
OSC
IN
OSC
OUT
SYNC
KEY
1
to KEY
4
KEY REQ
V
DD
V
SS
V
LCD
V
EE
V
LC1
to V
LC3
Note
At OE = L, the key data cannot be written correctly, even when the display ON/OFF of the status
command is set to the "normal operation" (10). Also, in this state, unnecessary waveforms are
generated from between SEG
1
/KS
1
to SEG
8
/KS
8
during the key scanning period. (The display is OFF.)
Name
Segment output/key
source output
Segment output
Segment output/LED
output pins
Common output
Shift clock input
Data input/output
Strobe input
LCD/LED select
Output enable input
Oscillation input
Oscillation output
Synchronizing signal
Key data input
Key request output
Logic power supply
Logic GND
LCD drive power supply
LCD GND
Power supply for LCD
drive
No.
25 to 32
33 to 72
73 to 80
21 to 24
7
8
9
10
11
12
13
14
2 to 5
6
15
1
16
20
17 to 19
Description
These pins serve as LCD segment output pins and key
source output pins for key scanning.
LCD segment output pins
These pins can be used as LCD segment output or LED
output pins depending on the setting of the LCD/LED pin.
LCD common output pins
Data shift clock. Data is read at the rising edge, and is
output at the falling edge of this clock.
This pin inputs a command or display data, or outputs
key data.
A command or data is input at the rising edge of the shift
clock, starting from the most significant bit. Key data is
output at the falling edge of the shift clock, starting from
the most significant bit.
This pin serves as an open-drain pin in the output mode.
Data can be input when this signal goes low. When it
goes high, command processing is performed.
When this signal goes high, the SEG
n
/LED
m
pins function
as LCD segment output pins; when it goes low, they
function as LED driver output pins. The LED driver has a
drive capability of 15 mA and is N-ch open drain.
When this signal goes low, all the segment output and
LED output pins are off (SEG
n
= COM
n
= V
LCD
). Internal
data are saved.
Connect a resistor for oscillation circuit across these pins.
A synchronizing signal input pin. When two or more
PD16431A's are used, each device is wired-ORed. This
pin must be pulled up when this chip is used alone.
Key data input pins for key scanning
This signal goes high when a key is pressed (key data = H).
Read the key data only while this pin is high.
Power supply pin for internal logic
GND pin for internal logic and LED output
Power supply pin for LCD drive
GND pin for LCD drive
Power supply for driving dot matrix LCD
PD16431A
5
CONFIGURATION OF SHIFT REGISTER
Two shift registers, an 8-bit command register and a 56-bit display register, are provided. The first 8 bits
of input data are recognized as a command and are sent to the command register, and the 9th bit and those
that follow are recognized as display data and are sent to the display register.
b7
Command
8-bit shift register
b0
MSB
LSB
SEG
56
/LED
8
Display data (LCD, LED)
56-bit shift register
SEG
1
MSB
LSB
Transfer direction
The meaning of the display data is as follows:
LCD: 0
off, 1
on
LED: 0
on, 1
off
Be sure to transfer 56 bits of display data.
CONFIGURATION OF OUTPUT LATCH
SEG
56
/LED
8
SEG
1
MSB
LSB
COM
1
(latch address
Note
: 00)
SEG
56
/LED
8
SEG
1
COM
2
(latch address
Note
: 01)
SEG
56
/LED
8
SEG
1
COM
3
(latch address
Note
: 10)
SEG
56
/LED
8
SEG
1
COM
4
(latch address
Note
: 11)
Note
Bits b3 and b4 of status command (Refer to page 8.)
PD16431A
6
KEY MATRIX CONFIGURATION
An example of key matrix configurations is shown below.
1) When pressing three or more times is assumed:
A configuration example is shown below. In this configuration, 0 to 32 ON switches can be
recognized.
KEY
1
KEY
2
KEY
3
KEY
4
KS
2
KS
3
KS
4
KS
5
KS
6
KS
7
KS
8
KS
1
=
C
2) When pressing twice or more times is assumed:
A configuration example is shown below. In this configuration, 0 to 2 ON switches can be recognized.
KEY
1
KEY
2
KEY
3
KEY
4
KS
2
KS
3
KS
4
KS
5
KS
6
KS
7
KS
8
KS
1
=
Diode A
In this configuration, pressing three or more times may cause OFF switches to be determined to be ON.
For example, if SW2 to SW4 are ON and KS
1
has been selected (high level) as shown below, SW3 in which
current I
1
is running is supposed to be detected to be ON. However, since SW2 and SW4 are ON, current
I
2
runs thus resulting in SW1 to be recognized as being ON.
KEY
1
KEY
2
KEY
3
KEY
4
KS
2
KS
3
KS
4
KS
5
KS
6
KS
7
KS
8
Select
KS
1
SW3
SW4
I
1
I
2
=
SW1
SW2
PD16431A
7
If diode A is not available, not only the key data may not be read normally but the LCD display may be
affected or ICs may be damaged or deteriorated.
For example, if SW1 and SW2 are ON and KS
1
has been selected (high level) as shown below, this will
cause not only current I
1
which is supposed to run but also short-circuited current I
2
of KS
1
to KS
2
to run.
It is possible that this will then cause the following three problems:
(1)Since the level to KEY
2
is not correctly sent, the key data cannot be latched correctly.
(2)If KS
2
is used as SEG
2
as well, the LCD display may be distorted (such as causing unintended segments
to light up).
(3)Since the short-circuited current (current I
2
) of KS
2
(high level) to KS
2
(low level) runs, ICS may be
damaged or deteriorated
KEY
1
KEY
2
KEY
3
KEY
4
KS
2
KS
3
KS
4
KS
5
KS
6
KS
7
KS
8
Select
(high level)
Non Select
(low level)
KS
1
SW1
SW2
I
1
I
2
=
PD16431A
8
CONFIGURATION OF KEY DATA LATCH
The key data is latched as illustrated below and is read by a read command, starting from the most
significant bit. Key data is read once a frame and latched when coinciding with the immediadtely preceding
data. In other words, it requires at least 2 frames from the time the key is pressed till data is confirmed to
be the key data (the key request becoming H).
32-bit latch/SHIFT register
KS
1
MSB
LSB
KS
2
KS
3
KS
4
KS
5
KS
6
KS
7
KS
8
KEY
1
KEY
2
KEY
3
KEY
4
The key data is 0 when off and 1 when on.
KEY INPUT EQUIVALENT CIRCUIT
KEY n
To key latch
Pull-down
control signal
The pull-down control signal goes high only during key
source output and turns on the pull-down transistor.
The on-resistance of the pull-down transistor is several k
.
PD16431A
9
COMMAND
A command sets a display mode and a status.
The first 1 byte input after the STB pin has fallen is regarded as a command.
If the STB pin is made low while a command/data is transferred, serial communication is initialized, and
the command/data being transferred is made invalid (the command/data that has been already transferred
remains valid, however).
(1) Display setting command
This command initializes the
PD16431A and sets a duty cycle, frame frequency, drive voltage supply
method, test mode, and whether the
PD16431A operates as the master or a slave.
When this command is executed, display is forcibly turned off and key scanning is stopped. To resume
the display, the normal operation of the "status command" must be executed. Note, however, that nothing
is executed if the same mode is selected.
b0
MSB
LSB
b1
b2
b3
b4
b5
b6
0
Sets duty.
00: 1/4 duty, 1/3 bias
01: 1/3 duty, 1/3 bias
10: 1/2 duty, 1/2 bias
11: 1/2 duty, 1/2 bias
Sets frame frequency.
00: (f
OSC
/128)
n
01: (f
OSC
/256)
n
10: (f
OSC
/512)
n
11: (f
OSC
/1024)
n
n= duty (1/2, 1/3, 1/4)
Sets drive voltage supply method.
0: Internal
1: External
Sets master or slave.
0: Master
1: Slave
Sets test mode.
0: Normal operation
1: Test mode
0
Values when power is applied
0
0
0
0
0
0
PD16431A
10
(2) Status command
This command sets a data write/read mode, turns on/off display, and sets a latch address.
b0
MSB
LSB
b1
b2
b3
b4
1
Sets data write/read mode.
0: Writes display data to output latch
1: Reads key data
Turns on/off display
00: Forcibly turns off display (all segments and LEDs off).
Stops key scanning.
01: Prohibited
10: Normal operation
11: Don't care
Sets latch address.
00: COM
1
01: COM
2
10: COM
3
11: COM
4
0
Values when power is applied
0
0
0
0
: Don't Care
PD16431A
11
Top
: with internal power supply
Bottom: with external power supply
OUTPUT SELECT VOLTAGE
1. COM
+
Bias
When selected
V
LCD
GND
1/2 bias
V
LCD
GND
When not selected
1/2 V
LCD
1/2 V
LCD
V
LC2
V
LC2
When key scanned
1/2 V
LCD
1/2 V
LCD
V
LC2
V
LC2
When selected
V
LCD
GND
1/3 bias
V
LCD
GND
When not selected
1/3 V
LCD
2/3 V
LCD
V
LC3
V
LC1
When key scanned
1/2 V
LCD
1/2 V
LCD
V
LC2
V
LC2
2. SEG
+
Bias
When selected
GND
V
LCD
1/2 bias
GND
V
LCD
When not selected
V
LCD
GND
V
LCD
GND
When key scanned
GND
V
LCD
GND
V
LCD
When key not
V
LCD
GND
scanned
V
LCD
GND
When selected
GND
V
LCD
1/3 bias
GND
V
LCD
When not selected
2/3 V
LCD
1/3 V
LCD
V
LC1
V
LC3
When key scanned
GND
V
LCD
GND
V
LCD
When key not
V
LCD
GND
scanned
V
LCD
GND
PD16431A
12
OUTPUT WAVEFORM
(1) 1/2 duty (1/2 dias)
*
K
0
*
K
1
*
K
0
*
K
1
*
K
0
0
1
0
1
V
LCD
V
LC2
V
LCD
V
LC2
V
LCD
V
LC2
V
EE
V
EE
V
EE
V
LCD
V
LC2
V
EE
V
LCD
1/2V
LCD
0
-1/2V
LCD
-V
LCD
V
LCD
1/2V
LCD
0
-1/2V
LCD
-V
LCD
COM
1
COM
2
SEG
1
SEG
9
SEG
1
-COM
1
SEG
1
-COM
2
1 KEY REQ
(w/key)
2 KEY REQ
(w/key
w/o key)
3 KEY REQ
(w/o key
w/key)
*: key scan period (16/fc)
PD16431A
13
KEY SCAN PERIOD (K0) EXPANSION
1
K0
0
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
-SEG
40
= Key source output
PD16431A
14
KEY SCAN PERIOD (K1) EXPANSION
0
K1
1
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
-SEG
4,
SEG
9
-SEG
40
SEG
5
SEG
6
SEG
7
SEG
8
= Key source output
1 KEY REQ
(w/key)
2 KEY REQ
(w/key
w/o key)
3 KEY REQ
(w/o key
w/key)
PD16431A
15
(2) 1/3 duty (1/3 bias)
*
K
0
*
K
1
*
K
2
*
K
0
*
K
1
0
1
2
0
V
LCD
V
LC2
V
LCD
V
LC2
V
LCD
V
LC2
V
EE
V
EE
V
EE
V
LCD
V
LC2
V
EE
V
LC1
V
EE
COM
1
COM
2
COM
3
SEG
1
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LCD
V
LC3
V
LC2
V
LCD
1/2V
LCD
1/3V
LCD
-1/2V
LCD
-1/3V
LCD
0
SEG
1
-COM
1
-V
LCD
V
LCD
1/2V
LCD
1/3V
LCD
-1/2V
LCD
-1/3V
LCD
0
SEG
1
-COM
2
-V
LCD
SEG
9
*: key scan period (16/fc)
PD16431A
16
KEY SCAN PERIOD (K0) EXPANSION
2
K0
0
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
-SEG
8
= Key source output
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
PD16431A
17
KEY SCAN PERIOD (K1) EXPANSION
0
K1
1
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
-SEG
4,
SEG
9
-SEG
40
SEG
5
SEG
6
SEG
7
SEG
8
= Key source output
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
PD16431A
18
KEY SCAN PERIOD (K2) EXPANSION
1
K2
2
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
-SEG
40
V
LC1
V
LC3
V
LC1
V
LC3
PD16431A
19
(3) 1/4 duty (1/3 bias)
*
K
0
*
K
1
*
K
2
*
K
3
*
K
0
0
1
2
3
V
LCD
V
LC2
V
LCD
V
LC2
V
LCD
V
LC2
V
EE
V
EE
V
EE
V
LCD
V
LC2
V
EE
V
LC1
V
EE
COM
1
COM
2
COM
3
SEG
1
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LCD
V
LC3
V
LC2
V
LCD
1/2V
LCD
1/3V
LCD
-1/2V
LCD
-1/3V
LCD
0
SEG
1
-COM
1
-V
LCD
V
LCD
1/2V
LCD
1/3V
LCD
-1/2V
LCD
-1/3V
LCD
0
SEG
1
-COM
2
-V
LCD
V
LCD
V
LC2
V
EE
V
LC1
V
LC3
COM
4
*
K
1
0
2/3V
LCD
-2/3V
LCD
-2/3V
LCD
2/3V
LCD
SEG
9
*: key scan period
(16/fc)
PD16431A
20
KEY SCAN PERIOD (K0) EXPANSION
3
K0
0
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
-SEG
40
= Key source output
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
PD16431A
21
KEY SCAN PERIOD (K1) EXPANSION
0
K1
1
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
-SEG
4,
SEG
9
-SEG
40
SEG
5
SEG
6
SEG
7
SEG
8
= Key source output
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
V
LC1
V
LC3
PD16431A
22
KEY SCAN PERIOD (K2) EXPANSION
KEY SCAN PERIOD (K3) EXPANSION
1
K2
2
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
-SEG
40
V
LC1
V
LC3
V
LC1
V
LC3
2
K3
3
1
2
3
4
5
6
7
8
V
LCD
V
LC2
V
EE
V
LCD
V
LC2
V
EE
COM
1
SEG
1
-SEG
40
V
LC1
V
LC3
V
LC1
V
LC3
PD16431A
23
SERIAL COMMUNICATION FORMAT
(1) Receive (command/data write)
STB
DATA
b7
b6
b5
b2
b1
b0
SCK
1
2
3
6
7
8
If data continues
(2) Transmit (command/data read)
STB
DATA
7
6
5
SCK
1
2
3
2
1
6
7
8
7
6
1
2
3
4
3
4
5
6
5
0
Data read command set
Wait time t
WAIT
Data read
1 s
Note
Because the DATA pin is an N-ch open-drain output pin, be sure to connect an external pull-up
resistor to this pin (1 k
to 10 k
).
PD16431A
24
APPLICATION
1. Example of initial setting + display data write
Parameter
STB
Command/data
Remarks
b7 b6 b5 b4 b3 b2 b1 b0
Start
H
Set display command
L
0
0
0
0
0
0
0
0
1/4 duty, frame frequency = fosc/128
1/4, internal drive
voltage, master
H
Status command
L
1
0
0
0
0
0
0
0
Display data write, display off, latch address: COM
1
Display data 1
L
COM
1
data (7 bytes)
Display data 7
L
H
Status command
L
1
0
0
0
1
0
0
0
Display data write, display off, latch address: COM
2
Display data 1
L
COM
2
data (7 bytes)
Display data 7
L
H
Status command
L
1
0
0
1
0
0
0
0
Display data write, display off, latch address: COM
3
Display data 1
L
COM
3
data (7 bytes)
Display data 7
L
H
Status command
L
1
0
0
1
1
0
0
0
Display data write, display off, latch address: COM
4
Display data 1
L
COM
4
data (7 bytes)
Display data 7
L
H
Status command
L
1
0
0
0
0
1
0
0
Display data write, display on
End
H
PD16431A
25
2. Example of display data write (rewrite, 1/4)
Parameter
STB
Command/data
Remarks
b7 b6 b5 b4 b3 b2 b1 b0
Start
H
Status command
L
1
0
0
0
0
1
0
0
Display data write, display on, latch address: COM
1
Display data 1
L
COM
1
data (7 bytes)
Display data 7
L
H
Status command
L
1
0
0
0
1
1
0
0
Display data write, display on, latch address: COM
2
Display data 1
L
COM
2
data (7 bytes)
Display data 7
L
H
Status command
L
1
0
0
1
0
1
0
0
Display data write, display on, latch address: COM
3
Display data 1
L
COM
3
data (7 bytes)
Display data 7
L
H
Status command
L
1
0
0
1
1
1
0
0
Display data write, display on, latch address: COM
4
Display data 1
L
COM
4
data (7 bytes)
Display data 7
L
End
H
PD16431A
26
3. Example of key data read
Parameter
STB
Command/data
Remarks
b7 b6 b5 b4 b3 b2 b1 b0
KEY REQ check
KEY REQ = H: Key data exists.
Start reading.
KEY REQ = L: Key data does not exist (reading is inhibited).
Check KEY REQ again.
Start
H
Status command
L
1
0
0
0
0
1
0
1
Data read, display on
Wait time
L
1
s
Key data 1
L
4 bytes
Key data 4
L
End
H
PD16431A
27
ABSOLUTE MAXIMUM RATINGS (T
a
= 25 C, V
SS
= 0 V)
Parameter
Symbol
Ratings
Unit
Logic supply voltage
V
DD
0.3 to +7.0
V
Logic input voltage
V
IN
0.3 to V
DD
+ 0.3
V
Logic output voltage (DATA)
V
OUT
0.3 to +7.0
V
LCD drive supply voltage
V
LCD
0.3 to +7.0
V
LCD drive supply input voltage
V
LC1
to V
LC3
0.3 to V
LCD
+ 0.3
V
Driver output voltage
V
OUT2
0.3 to V
LCD
+ 0.3
V
(segment, common, LED)
LED output current
I
O
+20
mA
Operating ambient temperature
T
opt
40 to +85
C
Storage temperature
T
stg
55 to +150
C
Permissible package power
P
T
1 000
mW
dissipation
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Logic supply voltage
V
DD
2.7
5.0
5.5
V
LCD drive supply voltage
V
LCD
V
DD
5.0
6.5
V
Logic input voltage
V
IN
0
V
DD
V
Driver output voltage
V
LC1
to V
LC3
0
V
LCD
V
PD16431A
28
ELECTRICAL SPECIFICATIONS (Unless otherwise specified, T
a
= 40 to +85 C, V
DD
= V
LCD
= 5 V
10%)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Input voltage, high
V
IH
0.7 V
DD
V
DD
V
Input voltage, low
V
IL
0
0.3 V
DD
V
Input current, high
I
IH
CLK, STB, LCD/LED, OE
1
A
Input current, low
I
IL
CLK, STB, LCD/LED, OE
1
A
Output voltage, low
V
OL1
LED
1
to LED
8
. I
OL1
= 15 mA
1.0
V
Output voltage, high
V
OH2
OSC
OUT
, I
OH2
= 1 mA
0.9 V
DD
V
Output voltage, low
V
OL2
DATA, OSC
OUT
, SYNC, I
OL2
= 4 mA
0.1 V
DD
V
Leakage current, high
I
LOH2
DATA, SYNC, V
IN OUT
= V
DD
1
mA
Leakage current, low
I
LOL2
DATA, SYNC, V
IN OUT
= V
SS
1
mA
Common output ON resistance
R
COM
COM
1
to COM
4
, | I
O
| = 100
A
2.4
k
Segment output ON resistance
R
SEG
SEG
1
to SEG
56
, | I
O
| = 100
A
4.0
k
Logic current dissipation
I
DD
f
OSC
= 250 kHz
250
A
LCD drive current consumption
I
LCD
With internal bias and no load
500
A
Remark
The TYP. value is a reference value at T
a
= 25 C.
PD16431A
29
SWITCHING CHARACTERISTICS
(Unless otherwise specified, T
a
= 40 to +85 C, V
DD
= V
LCD
= 5 V
10%, R
L
= 5 k
, C
L
= 150 pF)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency
f
OSC
R = 100 k
175
250
325
kHz
Oscillation frequency
f
OSC
R = 200 k
105
150
195
kHz
Propagation delay time
t
PZL
SCK
DATA
100
ns
Propagation delay time
t
PLZ
SCK
DATA
300
ns
SYNC delay time
t
DSYNC
1.5
s
TIMING REQUIREMENTS
(Unless otherwise specified, T
a
= 40 to +85 C, V
DD
= V
LCD
= 5 V
10%, R
L
= 5 k
, C
L
= 150 pF)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Clock frequency
f
C
OSC
IN
external clock
50
325
kHz
High-level clock pulse width
t
WHC
OSC
IN
external clock
1.5
16
s
Low-level clock pulse width
t
WLC
OSC
IN
external clock
1.5
16
s
Shift clock cycle
t
CYK
SCK
900
ns
High-level shift clock pulse
t
WHK
SCK
400
ns
width
Low-level shift clock pulse
t
WLK
SCK
400
ns
width
Shift clock hold time
t
HSTBK
STB
SCK
1.5
s
Data setup time
t
DS
DATA
SCK
100
ns
Data hold time
t
DH
SCK
DATA
200
ns
STB hold time
t
DKSTB
SCK
STB
1
s
STB pulse width
t
WSTB
1
s
Wait time
t
WAIT
CLK
CLK
1
s
SYNC removal time
t
SREM
250
ns
Output Load
OUTPUT
V
DD
5 k
150 pF
PD16431A
30
V
IL
t
WLC
V
IH
t
WHC
1/f
c
CSC
IN
t
HKSTB
V
IL
STB
t
WSTB
V
IH
V
IL
SCK
t
WHK
t
WLK
t
CYK
V
IH
t
DH
t
DS
V
IH
V
IL
DATA
SYNC
f
OSC
Internal reset
t
DSYNC
t
SREM
SYNC timing (master)
SYNC timing (slave)
1 frame
1 frame
1 frame
1 frame
Switching Characteristic Waveform
PD16431A
31
Switching Characteristic Waveform
V
IL
t
PZL
SCK
V
OL2
t
PLZ
DATA
Application Circuit Example (with LED, 1/4 duty, 1/3 bias)
DATA
SCK
STB
KEY REQ
OE
LCD/LED
SYNC.
OSC
IN
OSC
OUT
KEY
n
LED
n
SEG
48
SEG
9
to
SEG
8
/KS
8
SEG
1
/KS
1
to
PD16431A
V
DD
V
SS
V
LCD
V
LC1
V
LC2
V
LC3
V
EE
COM
n
4
LCD
8
40
8
8
4
R
8
LED
R
5
R
7
R
6
R
1
R
2
R
2
R
1
GND
+6 V
+5 V GND
To microcomputer
Key matrix
8
4
R
1
: 1 k to 10 k
R
2
: 1/2 R
1
R
5
, R
6
: 1 k to 10 k
R
7
: 100 k
TYP.
R
8
: 330 to 1 k
R
1
through R
2
are not necessary when
the internal drive voltage is selected
(V
LC1
through V
LC3
are open).
V
DD
V
LCD
V
DD
PD16431A
32
Note
Example of external source circuit (when 1/2 bias)
V
DD
V
SS
V
LC0
V
LC1
V
LC2
V
LC3
V
EE
+5 V GND
+6 V
GND
R
1
R
1
R
1
= 1 k to 10 k
(approx.)
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
PD16431A
33
80 PIN PLASTIC LQFP ( 14)
ITEM
MILLIMETERS
INCHES
D
F
G
K
I
J
0.825
0.825
1.00.2
0.65 (T.P.)
0.13
16.00.2
Q
0.6300.008
0.032
0.032
0.039
0.005
0.026 (T.P.)
S80GC-65-7ET-1
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
C
14.00.1
0.551
M
0.125
0.005
0.1250.075
0.0050.003
+0.004
0.002
+0.005
0.004
A
16.00.2
0.6300.008
H
0.300.10
0.012+0.004
0.005
L
0.50.2
0.020+0.008
0.009
N
0.10
0.004
P
1.40.1
0.0550.004
S
1.7 MAX.
0.067 MAX.
+0.10
0.05
B
14.00.1
0.551+0.005
0.004
R
3
3
+7
3
+7
3
+0.009
0.008
A
F
detail of lead end
B
G
H
I
J
C
D
P
N
K
L
M
41
60
40
61
21
80
20
1
M
S
Q
R
PD16431A
34
REFERENCE
Document Name
Document No.
NEC Semiconductor Device Reliability/Quality Control System
IEI-1212
Quality grade on NEC Semiconductor Devices
IEI-1209
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11