Document Outline
- COVER
- PREFACE
- CHAPTER 1 INTRODUCTION
- 1.1 FEATURES
- 1.2 ORDERING INFORMATION
- 1.3 64-BIT ARCHITECTURE
- 1.4 VR4102 PROCESSOR
- 1.4.1 Internal Block Structure
- 1.4.2 I/O Registers
- 1.5 VR4100 CPU CORE
- 1.5.1 VR4100 CPU Core
- 1.5.2 CPU Registers
- 1.5.3 CPU Instruction Set Overview
- 1.5.4 Data Formats and Addressing
- 1.5.5 Coprocessors (CP0-CP3)
- 1.5.6 Floating-Point Unit (FPU)
- 1.5.7 Cache
- 1.6 CPU CORE MEMORY MANAGEMENT SYSTEM (MMU)
- 1.6.1 Translation Lookaside Buffer (TLB)
- 1.6.2 Operating Modes
- 1.7 INSTRUCTION PIPELINE
- 1.8 CLOCK INTERFACE
- CHAPTER 2 PIN FUNCTIONS
- 2.1 PIN CONFIGURATION
- 2.2 PIN FUNCTION DESCRIPTION
- 2.2.1 System Bus Interface Signals
- 2.2.2 Clock Interface Signals
- 2.2.3 Battery Monitor Interface Signals
- 2.2.4 Initialization Interface Signals
- 2.2.5 RS-232-C Interface Signals
- 2.2.6 IrDA Interface Signals
- 2.2.7 Debug Serial Interface Signals
- 2.2.8 Keyboard Interface Signals
- 2.2.9 Audio Interface Signals
- 2.2.10 Touch Panel/General Purpose A/D Interface Signals
- 2.2.11 General-purpose I/O Signals
- 2.2.12 HSP MODEM Interface Signals
- 2.2.13 LED Interface Signal
- 2.2.14 Dedicated VDD and GND Signals
- 2.3 PIN STATUS UPON SPECIFIC STATES
- 2.3.1 Pin Status upon Reset
- 2.3.2 Connection of Unused Pins and Pin I/O Circuits
- 2.3.3 Pin I/O Circuits
- CHAPTER 3 CPU INSTRUCTION SET SUMMARY
- 3.1 CPU INSTRUCTION FORMATS
- 3.2 INSTRUCTION CLASSES
- 3.2.1 Load and Store Instructions
- 3.2.2 Computational Instructions
- 3.2.3 Jump and Branch Instructions
- 3.2.4 Special Instructions
- 3.2.5 System Control Coprocessor (CP0) Instructions
- CHAPTER 4 VR4102 PIPELINE
- 4.1 PIPELINE STAGES
- 4.1.1 Pipeline Activities
- 4.2 BRANCH DELAY
- 4.3 LOAD DELAY
- 4.4 PIPELINE OPERATION
- 4.5 INTERLOCK AND EXCEPTION HANDLING
- 4.5.1 Exception Conditions
- 4.5.2 Stall Conditions
- 4.5.3 Slip Conditions
- 4.5.4 Bypassing
- 4.6 CODE COMPATIBILITY
- CHAPTER 5 MEMORY MANAGEMENT SYSTEM
- 5.1 TRANSLATION LOOKASIDE BUFFER (TLB)
- 5.2 VIRTUAL ADDRESS SPACE
- 5.2.1 Virtual-to-Physical Address Translation
- 5.2.2 32-bit Mode Address Translation
- 5.2.3 64-bit Mode Address Translation
- 5.2.4 Operating Modes
- 5.2.5 User Mode Virtual Addressing
- 5.2.6 Supervisor-mode Virtual Addressing
- 5.2.7 Kernel-mode Virtual Addressing
- 5.3 PHYSICAL ADDRESS SPACE
- 5.3.1 ROM Space
- 5.3.2 System Bus Space
- 5.3.3 Internal I/O Space
- 5.3.4 LCD Space
- 5.3.5 DRAM Space
- 5.4 SYSTEM CONTROL COPROCESSOR
- 5.4.1 Format of a TLB Entry
- 5.5 CP0 REGISTERS
- 5.5.1 Index Register (0)
- 5.5.2 Random Register (1)
- 5.5.3 EntryHi (10), EntryLO0 (2), EntryLO1 (3), and PageMask (5) Registers
- 5.5.4 Wired Register (6)
- 5.5.5 Processor Revision Identifier (PRId) Register (15)
- 5.5.6 Config Register (16)
- 5.5.7 Load Linked Address (LLAddr) Register (17)
- 5.5.8 Cache Tag Registers (TagLo (28) and TagHi (29))
- 5.5.9 Virtual-to-Physical Address Translation
- 5.5.10 TLB Misses
- 5.5.11 TLB Instructions
- CHAPTER 6 EXCEPTION PROCESSING
- 6.1 HOW EXCEPTION PROCESSING WORKS
- 6.2 PRECISION OF EXCEPTIONS
- 6.3 EXCEPTION PROCESSING REGISTERS
- 6.3.1 Context Register (4)
- 6.3.2 BadVAddr Register (8)
- 6.3.3 Count Register (9)
- 6.3.4 Compare Register (11)
- 6.3.5 Status Register (12)
- 6.3.6 Cause Register (13)
- 6.3.7 Exception Program Counter (EPC) Register (14)
- 6.3.8 WatchLo (18) and WatchHi (19) Registers
- 6.3.9 XContext Register (20)
- 6.3.10 Parity Error Register (26)
- 6.3.11 Cache Error Register (27)
- 6.3.12 ErrorEPC Register (30)
- 6.4 DETAILS OF EXCEPTIONS
- 6.4.1 Exception Types
- 6.4.2 Exception Vector Locations
- 6.4.3 Priority of Exceptions
- 6.4.4 Cold Reset Exception
- 6.4.5 Soft Reset Exception
- 6.4.6 NMI Exception
- 6.4.7 Address Error Exception
- 6.4.8 TLB Exceptions
- 6.4.9 Cache Error Exception
- 6.4.10 Bus Error Exception
- 6.4.11 System Call Exception
- 6.4.12 Breakpoint Exception
- 6.4.13 Coprocessor Unusable Exception
- 6.4.14 Reserved Instruction Exception
- 6.4.15 Trap Exception
- 6.4.16 Integer Overflow Exception
- 6.4.17 Watch Exception
- 6.4.18 Interrupt Exception
- 6.5 EXCEPTION PROCESSING AND SERVICING FLOWCHARTS
- CHAPTER 7 INITIALIZATION INTERFACE
- 7.1 RESET FUNCTION
- 7.1.1 RTC Reset
- 7.1.2 RSTSW
- 7.1.3 Deadman's Switch
- 7.1.4 Software Shutdown
- 7.1.5 HALTimer Shutdown
- 7.2 POWERON SEQUENCE
- 7.3 RESET OF THE CPU CORE
- 7.3.1 Cold Reset
- 7.3.2 Soft Reset
- 7.4 VR4102 PROCESSOR MODES
- 7.4.1 Power Modes
- 7.4.2 Privilege Mode
- 7.4.3 Reverse Endian
- 7.4.4 Bootstrap Exception Vector (BEV)
- 7.4.5 Cache Error Check
- 7.4.6 Parity Error Prohibit
- 7.4.7 Interrupt Enable (IE)
- CHAPTER 8 CACHE MEMORY
- 8.1 MEMORY ORGANIZATION
- 8.2 CACHE ORGANIZATION
- 8.2.1 Organization of the Instruction Cache (I-Cache)
- 8.2.2 Organization of the Data Cache (D-Cache)
- 8.2.3 Accessing the Caches
- 8.3 CACHE OPERATIONS
- 8.4 CACHE STATES
- 8.5 CACHE STATE TRANSITION DIAGRAMS
- 8.5.1 Data Cache State Transition
- 8.5.2 Instruction Cache State Transition
- 8.6 CACHE DATA INTEGRITY
- 8.7 MANIPULATION OF THE CACHES BY AN EXTERNAL AGENT
- CHAPTER 9 CPU CORE INTERRUPTS
- 9.1 NON-MASKABLE INTERRUPT (NMI)
- 9.2 ORDINARY INTERRUPTS
- 9.3 SOFTWARE INTERRUPTS GENERATED IN CPU CORE
- 9.4 TIMER INTERRUPT
- 9.5 ASSERTING INTERRUPTS
- 9.5.1 Detecting Hardware Interrupts
- 9.5.2 Masking Interrupt Signals
- CHAPTER 10 BCU (BUS CONTROL UNIT)
- 10.1 GENERAL
- 10.2 REGISTER SET
- 10.2.1 BCUCNTREG 1 (0x0B00 0000)
- 10.2.2 BCUCNTREG 2 (0x0B00 0002)
- 10.2.3 BCUSPEEDREG (0x0B00 000A)
- 10.2.4 BCUERRSTREG (0x0B00 000C)
- 10.2.5 BCURFCNTREG (0x0B00 000E)
- 10.2.6 REVIDREG (0x0B00 0010)
- 10.2.7 BCURFCOUNTREG (0x0B00 0012)
- 10.2.8 CLKSPEEDREG (0x0B00 0014)
- 10.3 CONNECTION OF ADDRESS PINS
- 10.4 NOTES ON USING BCU
- 10.4.1 CPU Core Bus Modes
- 10.4.2 Access Data Size
- 10.4.3 ROM Interface
- 10.4.4 Flash Memory Interface
- 10.4.5 LCD Control Interface
- 10.4.6 Illegal Access Notification
- 10.5 BUS OPERATIONS
- 10.5.1 ROM Access
- 10.5.2 System Bus Access
- 10.5.3 LCD Interface
- 10.5.4 DRAM Access (EDO Type)
- 10.5.5 Refresh
- 10.5.6 Bus Hold
- CHAPTER 11 DMAAU (DMA ADDRESS UNIT)
- 11.1 GENERAL
- 11.2 REGISTER SET
- 11.2.1 AIU IN DMA Base Address Registers
- 11.2.2 AIU IN DMA Address Registers
- 11.2.3 AIU OUT DMA Base Address Registers
- 11.2.4 AIU OUT DMA Address Registers
- 11.2.5 FIR DMA Base Address Registers
- 11.2.6 FIR DMA Address Registers
- CHAPTER 12 DCU (DMA CONTROL UNIT)
- 12.1 GENERAL
- 12.2 DMA PRIORITY CONTROL
- 12.3 REGISTER SET
- 12.3.1 DMARSTREG (0x0B00 0040)
- 12.3.2 DMAIDLEREG (0x0B00 0042)
- 12.3.3 DMASENREG (0x0B00 0044)
- 12.3.4 DMAMSKREG (0x0B00 0046)
- 12.3.5 DMAREQREG (0x0B00 0048)
- 12.3.6 TDREG (0x0B00 004A)
- CHAPTER 13 CMU (CLOCK MASK UNIT)
- 13.1 GENERAL
- 13.2 REGISTER SET
- 13.2.1 CMUCLKMSK (0x0B00 0060)
- CHAPTER 14 ICU (INTERRUPT CONTROL UNIT)
- 14.1 GENERAL
- 14.2 REGISTER SET
- 14.2.1 SYSINT1REG (0x0B00 0080)
- 14.2.2 PIUINTREG (0x0B00 0082)
- 14.2.3 AIUINTREG (0x0B00 0084)
- 14.2.4 KIUINTREG (0x0B00 0086)
- 14.2.5 GIUINTLREG (0x0B00 0088)
- 14.2.6 DSIUINTREG (0x0B00 008A)
- 14.2.7 MSYSINT1REG (0x0B00 008C)
- 14.2.8 MPIUINTREG (0x0B00 008E)
- 14.2.9 MAIUINTREG (0x0B00 0090)
- 14.2.10 MKIUINTREG (0x0B00 0092)
- 14.2.11 MGIUINTLREG (0x0B00 0094)
- 14.2.12 MDSIUINTREG (0x0B00 0096)
- 14.2.13 NMIREG (0x0B00 0098)
- 14.2.14 SOFTINTREG (0x0B00 009A)
- 14.2.15 SYSINT2REG (0x0B00 0200)
- 14.2.16 GIUINTHREG (0x0B00 0202)
- 14.2.17 FIRINTREG (0x0B00 0204)
- 14.2.18 MSYSINT2REG (0x0B00 0206)
- 14.2.19 MGIUINTHREG (0x0B00 0208)
- 14.2.20 MFIRINTREG (0x0B00 020A)
- 14.3 NOTES FOR REGISTER SETTING
- CHAPTER 15 PMU (POWER MANAGEMENT UNIT)
- 15.1 GENERAL
- 15.1.1 Reset Control
- 15.1.2 Shutdown Control
- 15.1.3 Power-on Control
- 15.1.4 Power Mode
- 15.2 REGISTER SET
- 15.2.1 PMUINTREG (0x0B00 00A0)
- 15.2.2 PMUCNTREG (0x0B00 00A2)
- 15.2.3 PMUINT2REG (0x0B00 00A4)
- 15.2.4 PMUCNT2REG (0x0B00 00A6)
- CHAPTER 16 RTC (REALTIME CLOCK UNIT)
- 16.1 GENERAL
- 16.2 REGISTER SET
- 16.2.1 Elapsed Time Registers
- 16.2.2 Elapsed Time Compare Registers
- 16.2.3 RTC Long 1 Registers
- 16.2.4 RTC Long 1 Count Registers
- 16.2.5 RTC Long 2 Registers
- 16.2.6 RTC Long 2 Count Registers
- 16.2.7 TClock Counter Registers
- 16.2.8 TClock Counter Count Registers
- 16.2.9 RTC Interrupt Register
- CHAPTER 17 DSU (DEADMANS SWITCH UNIT)
- 17.1 GENERAL
- 17.2 REGISTER SET
- 17.2.1 DSUCNTREG (0x0B00 00E0)
- 17.2.2 DSUSETREG (0x0B00 00E2)
- 17.2.3 DSUCLRREG (0x0B00 00E4)
- 17.2.4 DSUTIMREG (0x0B00 00E6)
- 17.3 REGISTER SETTING FLOW
- CHAPTER 18 GIU (GENERAL PURPOSE I/O UNIT)
- 18.1 GENERAL
- 18.2 REGISTER SET
- 18.2.1 GIUIOSELL (0x0B00 0100)
- 18.2.2 GIUIOSELH (0x0B00 0102)
- 18.2.3 GIUPIODL (0x0B00 0104)
- 18.2.4 GIUPIODH (0x0B00 0106)
- 18.2.5 GIUINTSTATL (0x0B00 0108)
- 18.2.6 GIUINTSTATH (0x0B00 010A)
- 18.2.7 GIUINTENL (0x0B00 010C)
- 18.2.8 GIUINTENH (0x0B00 010E)
- 18.2.9 GIUINTTYPL (0x0B00 0110)
- 18.2.10 GIUINTTYPH (0x0B00 0112)
- 18.2.11 GIUINTALSELL (0x0B00 0114)
- 18.2.12 GIUINTALSELH (0x0B00 0116)
- 18.2.13 GIUINTHTSELL (0x0B00 0118)
- 18.2.14 GIUINTHTSELH (0x0B00 011A)
- 18.2.15 GIUPODATL (0x0B00 011C)
- 18.2.16 GIUPODATH (0x0B00 011E)
- CHAPTER 19 PIU (TOUCH PANEL INTERFACE UNIT)
- 19.1 GENERAL
- 19.2 SCAN SEQUENCER STATE TRANSITION
- 19.3 REGISTER SET
- 19.3.1 PIUCNTREG (0x0B00 0122)
- 19.3.2 PIUINTREG (0x0B00 0124)
- 19.3.3 PIUSIVLREG (0x0B00 0126)
- 19.3.4 PIUSTBLREG (0x0B00 0128)
- 19.3.5 PIUCMDREG (0x0B00 012A)
- 19.3.6 PIUASCNREG (0x0B00 0130)
- 19.3.7 PIUAMSKREG (0x0B00 0132)
- 19.3.8 PIUCIVLREG (0x0B00 013E)
- 19.3.9 PIUPBnmREG (0x0B00 02A0 to 0x0B00 02AE, 0x0B00 02BC to 0x0B00 02BE)
- 19.3.10 PIUABnREG (0x0B00 02B0 to 0x0B00 02B6)
- 19.4 REGISTER SETTING FLOW
- 19.5 RELATIONSHIPS AMONG TPX, TPY, AND ADIN PINS AND STATES
- 19.6 TIMING
- 19.6.1 Touch/Release Detection Timing
- 19.6.2 A/D Port Scan Timing
- 19.7 DATA LOSS INTERRUPT CONDITIONS
- 19.8 COMPARISON OF VR4102 AND VR4101
- CHAPTER 20 AIU (AUDIO INTERFACE UNIT)
- 20.1 GENERAL
- 20.2 REGISTER SET
- 20.2.1 MDMADATREG (0x0B00 0160)
- 20.2.2 SDMADATREG (0x0B00 0162)
- 20.2.3 SODATREG (0x0B00 0166)
- 20.2.4 SCNTREG (0x0B00 0168)
- 20.2.5 SCNVRREG (0x0B00 016A)
- 20.2.6 MIDATREG (0x0B00 0170)
- 20.2.7 MCNTREG (0x0B00 0172)
- 20.2.8 MCNVRREG (0x0B00 0174)
- 20.2.9 DVALIDREG (0x0B00 0178)
- 20.2.10 SEQREG (0x0B00 017A)
- 20.2.11 INTREG (0x0B00 017C)
- 20.3 OPERATION SEQUENCE
- 20.3.1 Output (Speaker)
- 20.3.2 Input (MIC)
- CHAPTER 21 KIU (KEYBOARD INTERFACE UNIT)
- 21.1 GENERAL
- 21.2 REGISTER SET
- 21.2.1 KIUDATn (0x0B00 0180 to 0x0B00 018A)
- 21.2.2 KIUSCANREP (0x0B00 0190)
- 21.2.3 KIUSCANS (0x0B00 0192)
- 21.2.4 KIUWKS (0x0B00 0194)
- 21.2.5 KIUWKI (0x0B00 0196)
- 21.2.6 KIUINT (0x0B00 0198)
- 21.2.7 KIURST (0x0B00 019A)
- 21.2.8 KIUGPEN (0x0B00 019C)
- 21.2.9 SCANLINE (0x0B00 019E)
- CHAPTER 22 DSIU (DEBUG SERIAL INTERFACE UNIT)
- 22.1 GENERAL
- 22.2 REGISTER SET
- 22.2.1 PORTREG (0x0B00 01A0)
- 22.2.2 MODEMREG (0x0B00 01A2)
- 22.2.3 ASIM00REG (0x0B00 01A4)
- 22.2.4 ASIM01REG (0x0B00 01A6)
- 22.2.5 RXB0RREG (0x0B00 01A8)
- 22.2.6 RXB0LREG (0x0B00 01AA)
- 22.2.7 TXS0RREG (0x0B00 01AC)
- 22.2.8 TXS0LREG (0x0B00 01AE)
- 22.2.9 ASIS0REG (0x0B00 01B0)
- 22.2.10 INTR0REG (0x0B00 01B2)
- 22.2.11 BPRM0REG (0x0B00 01B6)
- 22.2.12 DSIURESETREG (0x0B00 01B8)
- 22.3 DESCRIPTION OF OPERATIONS
- 22.3.1 Data Format
- 22.3.2 Transmission
- 22.3.3 Reception
- CHAPTER 23 LED (LED CONTROL UNIT)
- 23.1 GENERAL
- 23.2 REGISTER SET
- 23.2.1 LEDHTSREG (0x0B00 0240)
- 23.2.2 LEDLTSREG (0x0B00 0242)
- 23.2.3 LEDCNTREG (0x0B00 0248)
- 23.2.4 LEDASTCREG (0x0B00 024A)
- 23.2.5 LEDINTREG (0x0B00 024C)
- 23.3 OPERATION FLOW
- CHAPTER 24 SIU (SERIAL INTERFACE UNIT)
- 24.1 GENERAL
- 24.2 REGISTER SET
- 24.2.1 SIURB (0x0C00 0000: LCR[7] = 0, Read)
- 24.2.2 SIUTH (0x0C00 0000: LCR[7] = 0, Write)
- 24.2.3 SIUDLL (0x0C00 0000: LCR[7] = 1)
- 24.2.4 SIUIE (0x0C00 0001: LCR[7] = 0)
- 24.2.5 SIUDLM (0x0C00 0001: LCR[7] = 1)
- 24.2.6 SIUIID (0x0C00 0002: Read)
- 24.2.7 SIUFC (0x0C00 0002: Write)
- 24.2.8 SIULC (0x0C00 0003)
- 24.2.9 SIUMC (0x0C00 0004)
- 24.2.10 SIULS (0x0C00 0005)
- 24.2.11 SIUMS (0x0C00 0006)
- 24.2.12 SIUSC (0x0C00 0007)
- 24.2.13 SIUIRSEL (0x0C00 0008)
- CHAPTER 25 HSP (MODEM INTERFACE UNIT)
- 25.1 GENERAL
- 25.2 REGISTER SET
- 25.2.1 HSP Initialize Register
- 25.2.2 HSP Data Register, HSP Index Register
- 25.2.3 HSP ID Register, HSP I/O Address Program Confirmation Register
- 25.2.4 HSP Signature Checking Port
- 25.3 POWER CONTROL
- CHAPTER 26 FIR (FAST IrDA INTERFACE UNIT)
- 26.1 GENERAL
- 26.2 REGISTER SET
- 26.2.1 FRSTR (0x0C00 0040)
- 26.2.2 DPINTR (0x0C00 0042)
- 26.2.3 DPCNTR (0x0C00 0044)
- 26.2.4 TDR (0x0C00 0050)
- 26.2.5 RDR (0x0C00 0052)
- 26.2.6 IMR (0x0C00 0054)
- 26.2.7 FSR (0x0C00 0056)
- 26.2.8 IRSR1 (0x0C00 0058)
- 26.2.9 CRCSR (0x0C00 005C)
- 26.2.10 FIRCR (0x0C00 005E)
- 26.2.11 MIRCR (0x0C00 0060)
- 26.2.12 DMACR (0x0C00 0062)
- 26.2.13 DMAER (0x0C00 0064)
- 26.2.14 TXIR (0x0C00 0066)
- 26.2.15 RXIR (0x0C00 0068)
- 26.2.16 IFR (0x0C00 006A)
- 26.2.17 RXSTS (0x0C00 006C)
- 26.2.18 TXFL (0x0C00 006E)
- 26.2.19 MRXF (0x0C00 0070)
- 26.2.20 RXFL (0x0C00 0074)
- CHAPTER 27 CPU INSTRUCTION SET DETAILS
- 27.1 INSTRUCTION NOTATION CONVENTIONS
- 27.2 LOAD AND STORE INSTRUCTIONS
- 27.3 JUMP AND BRANCH INSTRUCTIONS
- 27.4 SYSTEM CONTROL COPROCESSOR (CP0) INSTRUCTIONS
- 27.5 CPU INSTRUCTION
- 27.6 CPU INSTRUCTION OPCODE BIT ENCODING
- CHAPTER 28 VR4102 COPROCESSOR 0 HAZARDS
- CHAPTER 29 PLL PASSIVE COMPONENTS
- APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101
- A.1 SUMMARY OF DIFFERENCES
- A.2 DETAILS OF DIFFERENCES
- A.2.1 CPU Core
- A.2.2 Address Mapping
- A.2.3 BCU
- A.2.4 DMA
- A.2.5 ICU
- A.2.6 PMU
- A.2.7 RTC
- A.2.8 GIU
- A.2.9 PIU
- A.2.10 AIU
- A.2.11 KIU
- A.2.12 DSIU
- A.2.13 SIU
- A.2.14 Newly Added Units
- APPENDIX B INDEX
MIPS Technologies, Inc. 1996
Printed in Japan
Document No. U12739EJ2V0UM00 (2nd edition)
Date Published January 1998 N CP(K)
V
R
4102TM
64/32-bit Microprocessor
Preliminary User's Manual
1997
P
P
P
P
PD30102
2
[MEMO]
3
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
V
R
3000, V
R
4000, V
R
4100, V
R
4101, V
R
4102, V
R
4200, V
R
4400, and V
R
Series are trademarks of NEC
Corporation.
MIPS is a trademark of MIPS Technologies, Inc.
iAPX is a trademark of Intel Corp.
DEC VAX is a trademark of Digital Equipment Corp.
UNIX is a registered trademark in the United States and other countries, licensed exclusively through
X/Open Company, Ltd.
4
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M7 96. 5
Exporting this product or equipment that include this product may require a governmental license from
the U.S.A. for some countries because this product utilizes technologies limited by the export control
regulations of the U.S.A.
5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829
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