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MOS INTEGRATED CIRCUIT

PD44324085, 44324095, 44324185, 44324365

36M-BIT DDRII SRAM SEPARATE I/O

2-WORD BURST OPERATION

Document No. M16782EJ1V0DS00 (1st edition)
Date Published October 2004 NS CP(K)
Printed in Japan

PRELIMINARY DATA SHEET

2003

Description

The

PD44324085 is a 4,194,304-word by 8-bit, the

PD44324095 is a 4,194,304-word by 9-bit, the

PD44324185 is a

2,097,152-word by 18-bit and the

PD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD44324085,

PD44324095,

PD44324185 and

PD44324365 integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K
and /K.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

· 1.8 ± 0.1 V power supply and HSTL I/O
· DLL circuitry for wide output data valid window and future frequency scaling
· Separate independent read and write data ports
· DDR read or write operation initiated each cycle
· Pipelined double data rate operation
· Separate data input/output bus
· Two-tick burst for low DDR transaction size
· Two input clocks (K and /K) for precise DDR timing at clock rising edges only
· Two output clocks (C and /C) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
· Internally self-timed write control
· Clock-stop capability with

s restart

· User programmable impedance output
· Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)
· Simple control logic for easy depth expansion
· JTAG boundary scan

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Pin Configurations

××× indicates active low signal.

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[

PD44324085F5-EQ2]

1 2 3 4 5 6 7 8 9 10

A /CQ V

A R,

/NW1

/K NC /LD A A CQ

NC NC NC A NC K /NW0 A NC NC Q3

C NC NC NC V

A A A V

NC NC D3

NC D4 NC V

NC NC NC

E NC NC Q4 V

Q V

Q NC D2 Q2

F NC NC NC V

Q V

Q NC NC NC

G NC D5 Q5 V

Q V

Q NC NC NC

H /DLL V

REF

Q V

REF

J NC NC NC V

Q V

Q NC Q1 D1

K NC NC NC V

Q V

Q NC NC NC

L NC Q6 D6 V

Q V

Q NC NC Q0

M NC NC NC V

NC NC D0

NC D7 NC V

A A A V

NC NC NC

Q7 A A C A A NC

TDO

TCK A A A /C A A A

TMS

TDI

: Address inputs

TMS

: IEEE 1149.1 Test input

D0 to D7

: Data inputs

TDI

: IEEE 1149.1 Test input

Q0 to Q7

: Data outputs

TCK

: IEEE 1149.1 Clock input

/LD

: Synchronous load

TDO

: IEEE 1149.1 Test output

R, /W

: Read Write input

REF

: HSTL input reference input

/NW0, /NW1

: Nibble Write data select

: Power Supply

K, /K

: Input clock

: Power Supply

C, /C

: Output clock

Ground

CQ, /CQ

: Echo clock

: No connection

: Output impedance matching

/DLL

: DLL disable

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[

PD44324095F5-EQ2]

1 2 3 4 5 6 7 8 9 10

A /CQ V

A R,

NC /K NC /LD A A CQ

NC NC NC A NC K /BW0 A NC NC Q4

C NC NC NC V

A A A V

NC NC D4

NC D5 NC V

NC NC NC

E NC NC Q5 V

Q V

Q NC D3 Q3

F NC NC NC V

Q V

Q NC NC NC

G NC D6 Q6 V

Q V

Q NC NC NC

H /DLL V

REF

Q V

REF

J NC NC NC V

Q V

Q NC Q2 D2

K NC NC NC V

Q V

Q NC NC NC

L NC Q7 D7 V

Q V

Q NC NC Q1

M NC NC NC V

NC NC D1

NC D8 NC V

A A A V

NC NC NC

Q8 A A C A A NC

TDO

TCK A A A /C A A A

TMS

TDI

: Address inputs

TMS

: IEEE 1149.1 Test input

D0 to D8

: Data inputs

TDI

: IEEE 1149.1 Test input

Q0 to Q8

: Data outputs

TCK

: IEEE 1149.1 Clock input

/LD

: Synchronous load

TDO

: IEEE 1149.1 Test output

R, /W

: Read Write input

REF

: HSTL input reference input

/BW0

: Byte Write data select

: Power Supply

K, /K

: Input clock

: Power Supply

C, /C

: Output clock

Ground

CQ, /CQ

: Echo clock

: No connection

: Output impedance matching

/DLL

: DLL disable

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[

PD44324185F5-EQ2]

1 2 3 4 5 6 7 8 9 10

A /CQ V

A R,

/BW1

/K NC /LD A V

NC Q9 D9 A NC K /BW0 A NC NC Q8

C NC NC D10 V

A A A V

NC Q7 D8

D NC D11 Q10 V

NC NC D7

E NC NC Q11 V

Q V

Q NC D6 Q6

F NC Q12 D12 V

Q V

Q NC NC Q5

G NC D13 Q13 V

Q V

Q NC NC D5

H /DLL V

REF

Q V

REF

J NC NC D14 V

Q V

Q NC Q4 D4

K NC NC Q14 V

Q V

Q NC D3 Q3

L NC Q15 D15 V

Q V

Q NC NC Q2

M NC NC D16 V

NC Q1 D2

N NC D17 Q16 V

A A A V

NC NC D1

Q17

A A C A A NC

TDO

TCK A A A /C A A A

TMS

TDI

: Address inputs

TMS

: IEEE 1149.1 Test input

D0 to D17

: Data inputs

TDI

: IEEE 1149.1 Test input

Q0 to Q17

: Data outputs

TCK

: IEEE 1149.1 Clock input

/LD

: Synchronous load

TDO

: IEEE 1149.1 Test output

R, /W

: Read Write input

REF

: HSTL input reference input

/BW0, /BW1

: Byte Write data select

: Power Supply

K, /K

: Input clock

: Power Supply

C, /C

: Output clock

Ground

CQ, /CQ

: Echo clock

: No connection

: Output impedance matching

/DLL

: DLL disable

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 10A are expansion addresses: 10A for 72Mb and 2A for 144Mb.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[

PD44324365F5-EQ2]

1 2 3 4 5 6 7 8 9 10

A /CQ V

NC R,

/BW2 /K /BW1

/LD A V

Q27 Q18 D18 A /BW3 K /BW0 A D17 Q17 Q8

C D27 Q28 D19 V

A A A V

D16 Q7 D8

D D28 D20 Q19 V

Q16 D15 D7

E Q29 D29 Q20 V

Q V

Q Q15 D6 Q6

F Q30 Q21 D21 V

Q V

Q D14 Q14 Q5

G D30 D22 Q22 V

Q V

Q Q13 D13 D5

H /DLL V

REF

Q V

REF

J D31 Q31 D23 V

Q V

Q D12 Q4 D4

K Q32 D32 Q23 V

Q V

Q Q12 D3 Q3

L Q33 Q24 D24 V

Q V

Q D11 Q11 Q2

D33 Q34 D25 V

D10 Q1 D2

N D34 D26 Q25 V

A A A V

Q10 D9 D1

Q35

D35

Q26

A A C A A Q9

TDO

TCK A A A /C A A A

TMS

TDI

: Address inputs

TMS

: IEEE 1149.1 Test input

D0 to D35

: Data inputs

TDI

: IEEE 1149.1 Test input

Q0 to Q35

: Data outputs

TCK

: IEEE 1149.1 Clock input

/LD

: Synchronous load

TDO

: IEEE 1149.1 Test output

R, /W

: Read Write input

REF

: HSTL input reference input

/BW0 to /BW3

: Byte Write data select

: Power Supply

K, /K

: Input clock

: Power Supply

C, /C

: Output clock

Ground

CQ, /CQ

: Echo clock

: No connection

: Output impedance matching

/DLL

: DLL disable

Remarks 1. Refer to Package Drawing for the index mark.

2. 3A and 10A are expansion addresses: 3A for 72Mb and 10A for 144Mb.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Pin Identification

Symbol Description

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the
rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). These
inputs are ignored when device is deselected.

D0 to Dxx

Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and /K
during WRITE operations. See Pin Configurations for ball site location of individual signals.
x8 device uses D0 to D7.
x9 device uses D0 to D8.
x18 device uses D0 to D17.
x36 device uses D0 to D35.

Q0 to Qxx

Synchronous Data Outputs: Output data is synchronized to the respective C and /C or to K and /K rising edges
if C and /C are tied HIGH. This bus operates in response to /R commands. See Pin Configurations for ball site
location of individual signals.
x8 device uses Q0 to Q7.
x9 device uses Q0 to Q8.
x18 device uses Q0 to Q17.
x36 device uses Q0 to Q35.

/LD

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition
includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus
activity).

R, /W

Synchronous Read/Write Input: When /LD is LOW, this input designates the access type (READ when R, /W is
HIGH, WRITE when R, /W is LOW) for the loaded address. R, /W must meet the setup and hold times around
the rising edge of K.

/BWx
/NWx

Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble
to be registered and written during WRITE cycles. These signals must meet setup and hold times around the
rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations
for signal to data relationships.

K, /K

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data
on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous
inputs must meet setup and hold times around the clock rising edges.

C, /C

Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of
/C is used as the output timing reference for first output data. The rising edge of C is used as the output
reference for second output data. Ideally, /C is 180 degrees out of phase with C. C and /C may be tied HIGH to
force the use of K and /K as the output reference clocks instead of having to provide C and /C clocks. If tied
HIGH, C and /C must remain HIGH and not be toggled during device operation.

CQ, /CQ

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous
data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q
tristates.

Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus
impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to
ground. This pin cannot be connected directly to GND or left unconnected.

/DLL

DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.

TMS
TDI

IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not
used in the circuit.

TCK

IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to V

if the JTAG function is not used in the

circuit.

TDO

IEEE 1149.1 Test Output: 1.8V I/O level.

REF

HSTL Input Reference Voltage: Nominally V

Q/2. Provides a reference voltage for the input buffers.

Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.

Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics
and Operating Conditions for range.

Power Supply: Ground

No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level
applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Block Diagram

[

PD44324085]

R, /W

/NW0

/NW1

/LD

R, /W

ADDRESS

D0 to D7

Q0 to Q7

MUX

OUTPUT

DATA

REGISTRY

& LOGIC

x 16

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

OUTPUT

SELECT

OUTPUT

BUFFER

ADDRESS

REGISTRY

& LOGIC

WRITE

C, /C
OR
K, /K

CQ,
/CQ

[

PD44324095]

R, /W

/BW0

/LD

R, /W

ADDRESS

D0 to D8

Q0 to Q8

MUX

OUTPUT

DATA

REGISTRY

& LOGIC

x 18

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

OUTPUT

SELECT

OUTPUT

BUFFER

ADDRESS

REGISTRY

& LOGIC

WRITE

C, /C
OR
K, /K

CQ,
/CQ

[

PD44324185]

R, /W

/BW0

/BW1

/LD

R, /W

ADDRESS

D0 to D17

Q0 to Q17

MUX

OUTPUT

DATA

REGISTRY

& LOGIC

x 36

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

OUTPUT

SELECT

OUTPUT

BUFFER

ADDRESS

REGISTRY

& LOGIC

WRITE

C, /C
OR
K, /K

CQ,
/CQ

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

[

PD44324365]

R, /W

/BW0

/BW1

/LD

R, /W

ADDRESS

D0 to D35

Q0 to Q35

MUX

OUTPUT

DATA

REGISTRY

& LOGIC

x 72

MEMORY

ARRAY

WRITE

DRIVER

SENSE

AMPS

OUTPUT

SELECT

OUTPUT

BUFFER

ADDRESS

REGISTRY

& LOGIC

WRITE

C, /C
OR
K, /K

CQ,
/CQ

/BW2
/BW3

Power-on Sequence

The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after

Q stable and when starting the clock before V

Q stable.

1. Clock starts after V

Q stable

Q Stable (<

±0.1 V DC per 50 ns)

Clock Start

1,024 cycles or more

Stable Clock

Start
Normal Operation

Clock

2. Clock starts before V

Q stable

Q Stable (<

±0.1 V DC per 50 ns)

Clock Start

1,024 cycles or more

Stable Clock

30 ns (MIN.)

DLL Reset or DLL Off

Start
Normal Operation

Clock

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Truth Table

Operation

/LD R, /W

CLK

D or Q

WRITE cycle

Data in

Load address, input write data on two

Input data

D(A+0)

D(A+1)

consecutive K and /K rising edge

Input clock

K(t+1)

/K(t+1)

READ cycle

Data out

Load address, read data on two

Output data

Q(A+0)

Q(A+1)

consecutive C and /C rising edge

Output clock

/C(t+1)

C(t+2)

NOP (No operation)

High-Z

STANDBY(Clock stopped)

Stopped

Previous state

Remarks 1. H : High level, L : Low level,

× : don't care, : rising edge.

2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges

except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Byte Write Operation

[

PD44324085]

Operation K

/NW0

/NW1

Write D0 to D7

0 0

Write D0 to D3

0 1

Write D4 to D7

1 0

Write nothing

1 1

Remark H : High level, L : Low level,

: rising edge.

[

PD44324095]

Operation K

/BW0

Write D0 to D8

Write nothing

Remark H : High level, L : Low level,

: rising edge.

[

PD44324185]

Operation K

/BW0

/BW1

Write D0 to D17

0 0

Write D0 to D8

0 1

Write D9 to D17

1 0

Write nothing

1 1

Remark H : High level, L : Low level,

: rising edge.

[

PD44324365]

Operation

/BW0 /BW1 /BW2 /BW3

Write D0 to D35

0 0 0 0

H 0 0 0 0

Write D0 to D8

0 1 1 1

H 0 1 1 1

Write D9 to D17

1 0 1 1

H 1 0 1 1

Write D18 to D26

1 1 0 1

H 1 1 0 1

Write D27 to D35

1 1 1 0

H 1 1 1 0

Write nothing

1 1 1 1

H 1 1 1 1

Remark H : High level, L : Low level,

: rising edge.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply voltage

0.5

+2.5

Output supply voltage

0.5

Input voltage

0.5

+ 0.5 (2.5 V MAX.)

Input / Output voltage

I/O

0.5

+ 0.5 (2.5 V MAX.)

Operating ambient temperature

°C

Storage temperature

stg

+125

°C

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (T

= 0 to 70

°C)

Parameter Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Note

Supply voltage

1.7

1.9

Output supply voltage

1.4

High level input voltage

IH (DC)

REF

+ 0.1

+ 0.3

1, 2

Low level input voltage

IL (DC)

0.3

REF

0.1

1, 2

Clock input voltage

0.3

+ 0.3

1, 2

Reference voltage

REF

0.68

0.95

Notes 1. During normal operation, V

Q must not exceed V

2. Power-up: V

Q + 0.3 V and V

1.7 V and V

1.4 V for t 200 ms

Recommended AC Operating Conditions (T

= 0 to 70

°C)

Parameter Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Note

High level input voltage

IH (AC)

REF

+ 0.2

Low level input voltage

IL (AC)

REF

0.2

Note 1. Overshoot: V

IH (AC)

+ 0.7 V for t

TKHKH/2

Undershoot:

IL (AC)

0.5 V for t TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than
TKHKH (MIN.).

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

DC Characteristics (T

= 0 to 70°C, V

= 1.8 ± 0.1 V)

Parameter Symbol Test

condition

MIN.

TYP. MAX. Unit

Note

x8,

x18

x36

Input leakage current

I/O leakage current

Operating supply current

or V

, E33

750 1,050 1,200 mA

(Read Write cycle)

I/O

= 0 mA

E40

650

900 1,000

Cycle = MAX.

E50

550

750

850

Standby supply current

SB1

or V

, E33

550

(NOP)

I/O

= 0 mA

E40

500

Cycle = MAX.

E50

400

High level output voltage

OH(Low)

0.1 mA

0.2

Q V

Note1

Q/20.12 V

Q/2+0.12 V

Low level output voltage

OL(Low)

0.1 mA

0.2 V

Note2

Q/20.12 V

Q/2+0.12 V

Notes 1. Outputs are impedance-controlled. | I

| = (V

Q/2)/(RQ/5) for values of 175

RQ 350 .

2. Outputs are impedance-controlled. I

= (V

Q/2)/(RQ/5) for values of 175

RQ 350 .

3. AC load current is higher than the shown DC values.

4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.

Capacitance (T

A =

°C, f = 1MHz)

Parameter Symbol

Test

conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

= 0 V

Input / Output capacitance

I/O

= 0 V

Clock Input capacitance

clk

= 0 V

Remark These parameters are periodically sampled and not 100% tested.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Read and Write Cycle

Parameter Symbol

-E33 -E40 -E50

Unit Note

(300 MHz)

(250 MHz)

(200 MHz)

MIN. MAX. MIN. MAX. MIN. MAX.

Clock

Average Clock cycle time (K, /K, C, /C) TKHKH

3.3 8.4 4.0 8.4 5.0 8.4

ns 1

Clock phase jitter (K, /K, C, /C)

TKC var

0.2 0.2 0.2

ns 2

Clock HIGH time (K, /K, C, /C)

TKHKL

1.32 1.6 2.0

Clock LOW time (K, /K, C, /C)

TKLKH

1.32 1.6 2.0

Clock to /clock (K

/K., C/C.) TKH

/KH

1.49 1.8 2.2

Clock to /clock (/K

K., /CC.) T

/KHKH

1.49 1.8 2.2

Clock to data clock 250 to 300 MHz

TKHCH

1.45

C., /K/C.)

200 to 250 MHz

0 1.8 0 1.8

167 to 200 MHz

0 2.3 0 2.3 0 2.3

133 to 167 MHz

0 2.8 0 2.8 0 2.8

< 133 MHz

0 3.55 0 3.55 0 3.55

DLL lock time (K, C)

TKC lock

1,024 1,024 1,024

Cycle

K static to DLL reset

TKC reset

30 30 30

Output Times

C, /C HIGH to output valid

TCHQV

0.45 0.45 0.45

C, /C HIGH to output hold

TCHQX

0.45

C, /C HIGH to echo clock valid

TCHCQV

0.45 0.45 0.45

C, /C HIGH to echo clock hold

TCHCQX

0.45

CQ, /CQ HIGH to output valid

TCQHQV

0.27 0.3 0.35

ns 4

CQ, /CQ HIGH to output hold

TCQHQX

0.27

0.3

0.35

ns 4

C HIGH to output High-Z

TCHQZ

0.45 0.45 0.45

C HIGH to output Low-Z

TCHQX1

0.45

Setup Times

Address valid to K rising edge

TAVKH

0.4 0.5 0.6

ns 5

Synchronous load input (/LD),

TIVKH

0.4 0.5 0.6

ns 5

read write input (R, /W) valid to

K rising edge

Data inputs and write data select

TDVKH

0.3 0.35 0.4 ns 5

inputs (/BWx, /NWx) valid to

K, /K rising edge

Hold Times

K rising edge to address hold

TKHAX

0.4 0.5 0.6

ns 5

K rising edge to

TKHIX

0.4 0.5 0.6

ns 5

synchronous load input (/LD),

read write input (R, /W) hold

K, /K rising edge to data inputs and

TKHDX

0.3 0.35 0.4 ns 5

write data select inputs (/BWx, /NWx)

hold

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.).

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

3. V

slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.

DLL lock time begins once V

and input clock are stable.

It is recommended that the device is kept inactive during these cycles.

4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a

± 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

5. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions

unless otherwise noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.

Q is 1.5 V DC.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Read and Write Timing

Address

Data in

TKH/KH

TKHCH

NOP

READ

(burst of 2)

WRITE

(burst of 2)

TKHKL

TKLKH

Q01

Q11

Data out

Q02

Q12

/LD

R, /W

TKHCH

TKHKL

TKLKH

TKH/KH T/KHKH

TCHQX1

TCHQX

TCHQZ

D21

D31

D22

D32

TDVKH

TKHDX

TDVKH

TKHDX

TKHKH

TIVKH

TKHIX

TAVKH TKHAX

/CQ

TCQHQV

TCHQV

TCHCQX

TCHCQV

TCHCQX

TCHCQV

READ

(burst of 2)

READ

(burst of 2)

NOP

Qx2

Q41

Q42

TCHQX

TCHQV

WRITE

(burst of 2)

T/KHKH

TKHKH

Remarks 1. Q01 refers to output from address A0+0.

Q02 refers to output from the next internal burst address following A0, i.e., A0+1.

2. Outputs are disable (high impedance) one clock cycle after a NOP.

3. In this example, if address A3=A4, data Q41=D31, Q42=D32.

Write data is forwarded immediately as read results.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

Pin assignments

Description

TCK 2R

Test Clock Input. All input are captured on the rising edge of TCK and all outputs
propagate from the falling edge of TCK.

TMS 10R

Test Mode Select. This is the command input for the TAP controller state machine.

TDI

11R

Test Data Input. This is the input side of the serial registers placed between TDI and
TDO. The register placed between TDI and TDO is determined by the state of the TAP
controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO

Test Data Output. Output changes in response to the falling edge of TCK. This is the
output side of the serial registers placed between TDI and TDO.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (T

= 0 to 70°C, V

= 1.8 ± 0.1 V, unless otherwise noted)

Parameter Symbol Conditions MIN.

TYP.

MAX.

Unit

Note

JTAG Input leakage current

5.0

+5.0

JTAG I/O leakage current

Q, 5.0

+5.0

Outputs

disabled

JTAG input high voltage

1.3

+0.3 V

JTAG input low voltage

0.3

+0.5 V

JTAG output high voltage

OH1

OHC

| = 100

A 1.6

OH2

OHT

| = 2 mA

1.4

JTAG output low voltage

OL1

OLC

= 100

0.2

OL2

OLT

= 2 mA

0.4

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Scan Register Definition (1)

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller when it is
moved into the run-test/idle or the various data register state. The register can be loaded when it is
placed between the TDI and TDO pins. The instruction register is automatically preloaded with the
IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial
test data to be passed through the RAMs TAP to another device in the scan chain with as little delay
as possible.

ID register

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when
the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.
The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR
state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents of the
RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to
activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary register
location. The first column defines the bit's position in the boundary register. The second column is
the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Bit size

Unit

Instruction register

bit

Bypass register

bit

ID register

bit

Boundary register

109

bit

ID Register Definition

Part number

Organization ID [31:28] vendor revision no.

ID [27:12] part no.

ID [11:1] vendor ID no.

ID [0] fix bit

PD44324085

4M x 8

XXXX

0000 0000 0100 0101

00000010000

PD44324095

4M x 9

XXXX

0000 0000 0100 0110

00000010000

PD44324185

2M x 18

XXXX

0000 0000 0100 0111

00000010000

PD44324365

1M x 36

XXXX

0000 0000 0100 1000

00000010000

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

SCAN Exit Order

Bit Signal

name

Bump

Bit Signal

name Bump

Bit

Signal

name Bump

no. x8 x9 x18 x36 ID no. x8 X9 x18 x36 ID no. x8 X9 x18 x36 ID

6R 37 NC NC NC D15 10D

73 NC NC NC Q28 2C

6P 38 NC NC NC Q15

9E 74 Q4 Q5 Q11 Q20 3E

6N 39 NC NC Q7 Q7 10C

75 D4 D5 D11 D20 2D

7P 40 NC NC D7 D7 11D

76 NC NC NC D29 2E

7N 41 NC NC NC D16

9C 77 NC NC NC Q29 1E

7R 42 NC NC NC Q16

9D 78 NC NC Q12

Q21 2F

8R 43 Q3 Q4 Q8 Q8 11B

79 NC NC D12 D21 3F

8P 44 D3 D4 D8 D8 11C

80 NC NC NC D30 1G

9R 45 NC NC NC D17

9B 81 NC NC NC Q30 1F

10 NC Q0 Q0 Q0 11P 46 NC NC NC Q17 10B

82 Q5 Q6 Q13 Q22 3G

11 NC D0 D0 D0 10P 47

11A

83 D5 D6 D13 D22 2G

12 NC NC NC D9 10N 48 A A V

10A

/DLL

13 NC NC NC Q9 9P 49

9A 85 NC NC NC D31 1J

14 NC NC Q1 Q1

10M 50

8B 86 NC NC NC Q31 2J

15 NC NC D1 D1 11N 51

7C 87 NC NC Q14

Q23 3K

16 NC NC NC

D10

9M 52

6C 88 NC NC D14 D23 3J

17 NC NC NC

Q10

9N 53

/LD

8A 89 NC NC NC D32 2K

18 Q0 Q1 Q2 Q2 11L 54 NC NC NC /BW1 7A 90 NC NC NC Q32 1K

19 D0 D1 D2 D2 11M 55 /NW0 /BW0 /BW0 /BW0 7B 91 Q6 Q7 Q15 Q24 2L

20 NC NC NC

D11 9L 56

6B 92 D6 D7 D15 D24 3L

21 NC NC NC

Q11

10L 57

6A 93 NC NC NC D33 1M

22 NC NC Q3 Q3 11K 58 NC NC NC

/BW3 5B 94 NC NC NC Q33 1L

23 NC NC D3 D3 10K 59

/NW1 NC

/BW1 /BW2 5A 95 NC NC Q16

Q25 3N

24 NC NC NC

D12 9J 60

4A 96 NC NC D16 D25 3M

25 NC NC NC

Q12 9K 61

5C 97 NC NC NC D34 1N

26 Q1 Q2 Q4 Q4 10J 62

4B 98 NC NC NC Q34 2M

27 D1 D2 D4 D4 11J 63 A A A NC 3A 99 Q7 Q8 Q17

Q26 3P

28 ZQ 11H

64 V

100

D17

D26

29 NC NC NC D13

10G 65

/CQ

1A 101 NC NC NC D35 2P

30 NC NC NC Q13 9G 66 NC NC Q9 Q18

2B 102 NC NC NC Q35 1P

31 NC NC Q5 Q5 11F 67 NC NC D9 D18

3B 103

32 NC NC D5 D5 11G 68 NC NC NC D27

1C 104

33 NC NC NC D14 9F 69 NC NC NC Q27

1B 105

34 NC NC NC Q14 10F 70 NC NC Q10 Q19

3D 106

35 Q2 Q3 Q6 Q6 11E 71 NC NC D10 D19

3C 107

36 D2 D3 D6 D6 10E 72 NC NC NC D28

1D 108

109

Internal

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

JTAG Instructions

Instructions Description

EXTEST

The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-
scan register cells at output pins are used to apply test vectors, while those at input pins capture test
results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,
the output drive is turned on and the PRELOAD data is driven onto the output pins.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is
placed in the test-logic-reset state.

BYPASS

The BYPASS instruction is loaded in the instruction register when the bypass register is placed
between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This
allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /

PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-
DR state loads the data in the RAMs input and Q pins into the boundary scan register. Because the
RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to
capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).
Although allowing the TAP to sample metastable input will not harm the device, repeatable results
cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input
data capture setup plus hold time (t

plus t

). The RAMs clock inputs need not be paused for any

other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving
the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced to an
inactive drive state (high impedance) and the boundary register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2 IR1 IR0 Instruction Note

0 0 0 EXTEST

0 0 1 IDCODE

0 1 0 SAMPLE-Z 1

0 1 1 RESERVED

SAMPLE / PRELOAD

1 0 1 RESERVED

1 1 0 RESERVED

1 1 1 BYPASS

Note 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

TAP Controller State Diagram

Test-Logic-Reset

Run-Test / Idle

Select-DR-Scan

Capture-DR

Capture-IR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Update-IR

Exit2-IR

Pause-IR

Exit1-IR

Shift-IR

Select-IR-Scan

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to V

to preclude mid level inputs.

TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and

may be left unconnected. But they may also be tied to V

through a 1 k

resistor.

TDO should be left unconnected.

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

Revision History

Edition/ Page

Type

of Location

Description

Date This

revision

(Previous

edition

This edition)

edition

1st edition/

Throughout Throughout

Modification

Preliminary Product Information

Oct. 2004

Preliminary Data sheet

Package

Code

F5-EQ1

F5-EQ2

Deletion

-E60 (167MHz)

p.2

Addition

Ordering

Information

"Note Under development" has been added to

-E33.

pp.3-6

Pin Configurations

Remark 2 has been added

p.9

Power-on Sequence

Power-on sequence has been added

p.14

Modification DC Characteristics I

(MAX.)

MAX.

Unit

MAX.

Unit

x8, x9 x18

x36

x8, x9 x18 x36

-E33 760 780 810

-E33 750 1,050

1,200 mA

-E40 650 670 700

-E40 650 900 1,000

-E50 550 570 600

-E50 550 750 850

DC Characteristics I

SB1

(MAX.)

MAX.

Unit

MAX.

Unit

x8, x9 x18

x36

x8, x9 x18 x36

-E33

290

-E33 550 mA

-E40

250

-E40 500

-E50

210

-E50 400

Preliminary Data Sheet

M16782EJ1V0DS

PD44324085, 44324095, 44324185, 44324365

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

(MAX) and V

(MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MAX) and

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

PD44324085, 44324095, 44324185, 44324365

The information in this document is current as of October, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
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circuits, software and information in the design of a customer's equipment shall be done under the full
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

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defined above).

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