The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1999
MOS INTEGRATED CIRCUIT
PD444016L
4M-BIT CMOS FAST SRAM
256K-WORD BY 16-BIT
DATA SHEET
Document No. M14431EJ3V0DS00 (3rd edition)
Date Published January 2001 NS CP(K)
Printed in Japan
The mark
shows major revised points.
Description
The
PD444016L is a high speed, low power, 4,194,304 bits (262,144 words by 16 bits) CMOS static RAM.
Operating supply voltage is 3.3 V
0.3 V.
The
PD444016L is packaged in 44-pin plastic SOJ and 44-pin plastic TSOP (II).
Features
262,144 words by 16 bits organization
Fast access time : 8, 10, 12 ns (MAX.)
Byte data control : /LB (I/O1 - I/O8), /UB (I/O9 - I/O16)
Output Enable input for easy application
Single +3.3 V power supply
Ordering Information
Part number
Package
Access time
Supply current mA (MAX.)
ns (MAX.)
At operating
At standby
PD444016LLE-A8
44-pin plastic SOJ
8
210
5
PD444016LLE-A10
(10.16 mm (400))
10
190
PD444016LLE-A12
12
180
PD444016LG5-A8-7JF
44-pin plastic TSOP (II)
8
210
PD444016LG5-A10-7JF
(10.16 mm (400))
10
190
PD444016LG5-A12-7JF
(Normal bent)
12
180
2
PD444016L
Data Sheet M14431EJ3V0DS
Pin Configuration (Marking Side)
/
indicates active low signal.
44-pin plastic SOJ (10.16 mm (400))
[
PD444016LLE ]
44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)
[
PD444016LG5-
-7JF ]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
A3
A4
/CS
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
/WE
A5
A6
A7
A8
A9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
/OE
/UB
/LB
I/O16
I/O15
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
A0 - A17
: Address Inputs
I/O1 - I/O16 : Data Inputs / Outputs
/CS
: Chip Select
/WE
: Write Enable
/OE
: Output Enable
/LB, /UB
: Byte data select
V
CC
: Power supply
GND
: Ground
NC
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
3
PD444016L
Data Sheet M14431EJ3V0DS
Block Diagram
GND
V
CC
/WE
/OE
/CS
Input data
controller
Sense amplifier /
Switching circuit
Column decoder
Address buffer
A0
|
A17
Address buffer
Row decoder
Memory cell array
4,194,304 bits
Output data
controller
/LB
/UB
I/O9 - I/O16
I/O1 - I/O8
Truth Table
/CS
/OE
/WE
/LB
/UB
Mode
I/O
Supply current
I/O1 - I/O8
I/O9 - I/O16
H
Not selected
High impedance
High impedance
I
SB
L
L
H
L
L
Read
D
OUT
D
OUT
I
CC
L
H
D
OUT
High impedance
H
L
High impedance
D
OUT
L
L
L
L
Write
D
IN
D
IN
L
H
D
IN
High impedance
H
L
High impedance
D
IN
L
H
H
Output disable
High impedance
High impedance
L
H
H
High impedance
High impedance
Remark
: Don't care
4
PD444016L
Data Sheet M14431EJ3V0DS
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Supply voltage
V
CC
0.5
Note
to +4.0
V
Input / Output voltage
V
T
0.5
Note
to +4.0
V
Operating ambient temperature
T
A
0 to 70
C
Storage temperature
T
stg
55 to +125
C
Note 2.0 V (MIN.) (pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Supply voltage
V
CC
3.0
3.3
3.6
V
High level input voltage
V
IH
2.0
V
CC
+0.3
V
Low level input voltage
V
IL
0.3
Note
+0.8
V
Operating ambient temperature
T
A
0
70
C
Note 2.0 V (MIN.) (pulse width : 2 ns)
5
PD444016L
Data Sheet M14431EJ3V0DS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input leakage current
I
LI
V
IN
= 0 V to V
CC
2
+2
A
Output leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CS = V
IH
or /OE = V
IH
2
+2
A
or /WE = V
IL
or /LB = V
IH
or /UB = V
IH
Operating supply current
I
CC
/CS = V
IL
,
Cycle time : 8 ns
210
mA
I
I/O
= 0 mA,
Cycle time : 10 ns
190
Minimum cycle time
Cycle time : 12 ns
180
Standby supply current
I
SB
/CS = V
IH
, V
IN
= V
IH
or V
IL
40
mA
I
SB1
/CS
V
CC
0.2 V,
5
V
IN
0.2 V or V
IN
V
CC
0.2 V
High level output voltage
V
OH
I
OH
= 4.0 mA
2.4
V
Low level output voltage
V
OL
I
OL
= +8.0 mA
0.4
V
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Capacitance (T
A
=
25
C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
6
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
8
pF
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
6
PD444016L
Data Sheet M14431EJ3V0DS
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time
3 ns)
Test Points
GND
3.0 V
1.5 V
1.5 V
Output Waveform
Test Points
1.5 V
1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or
Figure 2.
Figure 1
Figure 2
(t
AA
, t
ACS
, t
OE
, t
ABD
, t
OH
)
(t
CLZ
, t
OLZ
, t
BLZ
, t
CHZ
, t
OHZ
, t
BHZ
, t
WHZ
, t
OW
)
V
TT
= +1.5 V
I/O (Output)
50
Z
O
= 50
30 pF
C
L
+3.3 V
I/O (Output)
317
5 pF
C
L
351
Remark C
L
includes capacitances of the probe and jig, and stray capacitances.
7
PD444016L
Data Sheet M14431EJ3V0DS
Read Cycle
Parameter
Symbol
PD444016L-A8
PD444016L-A10
PD444016L-A12
Unit
Notes
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
8
10
12
ns
Address access time
t
AA
8
10
12
ns
1
/CS access time
t
ACS
8
10
12
ns
/OE access time
t
OE
4
5
6
ns
/LB, /UB access time
t
ABD
4
5
6
ns
Output hold from address change
t
OH
3
3
3
ns
/CS to output in low impedance
t
CLZ
3
3
3
ns
2, 3
/OE to output in low impedance
t
OLZ
0
0
0
ns
/LB, /UB to output in low impedance
t
BLZ
0
0
0
ns
/CS to output in high impedance
t
CHZ
4
5
6
ns
/OE to output hold in high impedance
t
OHZ
4
5
6
ns
/LB, /UB to output hold in high impedance
t
BHZ
4
5
6
ns
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at
200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Remark These AC characteristics are in common regardless of package types.
Read Cycle Timing Chart 1 (Address Access)
t
OH
t
RC
t
AA
Address (Input)
I/O (Output)
Previous data out
Data out
Remarks 1. In read cycle, /WE should be fixed to high level.
2. /CS = /OE = /LB (or /UB) = V
IL
8
PD444016L
Data Sheet M14431EJ3V0DS
Read Cycle Timing Chart 2 (/CS Access)
Address (Input)
t
RC
t
AA
t
OLZ
/CS (Input)
I/O (Output)
Data out
t
OHZ
High impedance
t
ACS
/OE (Input)
t
OE
t
CLZ
t
CHZ
High impedance
/LB, /UB (Input)
t
BLZ
t
ABD
t
BHZ
Caution
Address valid prior to or coincident with /CS low level input.
Remark
In read cycle, /WE should be fixed to high level.
9
PD444016L
Data Sheet M14431EJ3V0DS
Write Cycle
Parameter
Symbol
PD444016L-A8
PD444016L-A10
PD444016L-A12
Unit
Notes
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
8
10
12
ns
/CS to end of write
t
CW
6
7
8
ns
Address valid to end of write
t
AW
6
7
8
ns
Write pulse width
t
WP
6
7
8
ns
/LB, /UB to end of write
t
BW
6
7
8
ns
Data valid to end of write
t
DW
4
5
6
ns
Data hold time
t
DH
0
0
0
ns
Address setup time
t
AS
0
0
0
ns
Write recovery time
t
WR
0
0
0
ns
/WE to output in high impedance
t
WHZ
4
5
6
ns
1, 2
Output active from end of write
t
OW
3
3
3
ns
Notes 1. Transition is measured at
200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Remark These AC characteristics are in common regardless of package types.
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
WP
t
WR
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input / Output)
t
DH
t
WHZ
t
AW
High
impe-
dance
High
impe-
dance
t
OW
Indefinite data out
Data in
Indefinite data out
t
DW
t
AS
/LB, /UB (Input)
t
BW
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB
(or low level /UB).
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
10
PD444016L
Data Sheet M14431EJ3V0DS
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
AW
t
WP
t
WR
t
DW
t
DH
Address (Input)
/CS (Input)
/WE (Input)
/LB, /UB (Input)
High impedance
Data in
High impedance
t
BW
I/O (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remark
Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB
(or low level /UB).
11
PD444016L
Data Sheet M14431EJ3V0DS
Write Cycle Timing Chart 3 (/LB, /UB Controlled)
t
WC
t
AS
t
BW
t
WR
t
DW
t
DH
Address (Input)
/LB, /UB (Input)
/WE (Input)
/CS (Input)
High impedance
Data in
High impedance
t
CW
I/O (Input)
t
AW
t
WP
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remark
Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB
(or low level /UB).
12
PD444016L
Data Sheet M14431EJ3V0DS
Package Drawings
ITEM
MILLIMETERS
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
G
K
M
B
F
H
M
I
E
C
D
J
T
N
U
C
D
11.18
0.20
10.16
B
28.73
+
0.20
-
0.35
44-PIN PLASTIC SOJ (10.16 mm (400))
F
G
I
3.5
0.2
0.8 MIN.
0.74
E
1.03
0.15
H
2.3
0.2
K
0.12
1.27 (T.P.)
N
P
P44LE-400A-1
M
0.40
0.10
9.4
0.20
J
2.6
0.10
Q
T
R 0.85
U
0.20
+
0.10
-
0.05
44
23
1
22
S
P
S
Q
13
PD444016L
Data Sheet M14431EJ3V0DS
44-PIN PLASTIC TSOP (
II
) (10.16 mm (400))
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
C
18.63 MAX.
0.93 MAX.
0.1
0.05
E
F
B
0.8 (T.P.)
1.2 MAX.
G
0.97
H
11.76
0.2
I
10.16
0.1
J
0.8
0.2
D
0.32
+
0.08
-
0.07
M
0.13
N
0.10
L
0.5
0.1
K
0.145
+
0.025
-
0.015
P
3
+
7
-
3
S44G5-80-7JF5-1
M
44
23
1
22
S
N
S
K
L
F
E
P
J
G
D
M
C
A
B
H
I
detail of lead end
14
PD444016L
Data Sheet M14431EJ3V0DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD444016L.
Types of Surface Mount Device
PD444016LLE
: 44-pin plastic SOJ (10.16 mm (400))
PD444016LG5-7JF : 44-pin plastic TSOP (II) (10.16 mm (400)) (Normal bent)
15
PD444016L
Data Sheet M14431EJ3V0DS
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD444016L
M8E 00. 4
The information in this document is current as of January, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special":
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
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