Document Outline
- COVER
- Features
- Ordering Information
- Pin Configurations
- Block Diagrams
- Electrical Specifications
- Package Drawing
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MOS INTEGRATED CIRCUIT
PD4482161, 4482181, 4482321, 4482361
8M-BIT CMOS SYNCHRONOUS FAST SRAM
FLOW THROUGH OPERATION
Document No. M14521EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2000
Description
The
PD4482161 is a 524,288-word by 16-bit, the PD4482181 is a 524,288-word by 18-bit, the PD4482321 is a
262,144-word by 32-bit and the
PD4482361 is a 262,144-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using Full-CMOS six-transistor memory cell.
The
PD4482161, PD4482181, PD4482321 and PD4482361 integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The
PD4482161, PD4482181, PD4482321 and PD4482361 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep"). In
the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The
PD4482161, PD4482181, PD4482321 and PD4482361 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
3.3 V or 2.5 V core supply
Synchronous operation
Operating temperature : T
A
= 0 to 70
C (-A65, -A75, -A85, -C75, -C85)
T
A
=
-40 to +85 C (-A65Y, -A75Y, -A85Y, -C75Y, -C85Y)
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs for flow through operation
All registers triggered off positive clock edge
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4, /BWE (
PD4482321, PD4482361)
/BW1, /BW2, /BWE (
PD4482161, PD4482181)
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
2
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Ordering Information
(1/2)
Part number
Access
Clock
Core Supply
I/O Interface
Operating
Package
Time
Frequency
Voltage
Temperature
ns
MHz
V
C
PD4482161GF-A65
6.5
133
3.3 0.165
3.3 V LVTTL
Note
0 to 70
100-pin PLASTIC
PD4482161GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
LQFP (14
20)
PD4482161GF-A85
8.5
100
PD4482181GF-A65
6.5
133
3.3 V LVTTL
Note
PD4482181GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
PD4482181GF-A85
8.5
100
PD4482321GF-A65
6.5
133
3.3 V LVTTL
Note
PD4482321GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
PD4482321GF-A85
8.5
100
PD4482361GF-A65
6.5
133
3.3 V LVTTL
Note
PD4482361GF-A75
7.5
117
3.3 V or 2.5 V LVTTL
PD4482361GF-A85
8.5
100
PD4482161GF-C75
7.5
117
2.5 0.125
2.5 V LVTTL
PD4482161GF-C85
8.5
100
PD4482181GF-C75
7.5
117
PD4482181GF-C85
8.5
100
PD4482321GF-C75
7.5
117
PD4482321GF-C85
8.5
100
PD4482361GF-C75
7.5
117
PD4482361GF-C85
8.5
100
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75 (117 MHz).
3
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
(2/2)
Part number
Access
Clock
Core Supply
I/O Interface
Operating
Package
Time
Frequency
Voltage
Temperature
ns
MHz
V
C
PD4482161GF-A65Y
6.5
133
3.3 0.165
3.3 V LVTTL
Note
-40 to +85 100-pin PLASTIC
PD4482161GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
LQFP (14
20)
PD4482161GF-A85Y
8.5
100
PD4482181GF-A65Y
6.5
133
3.3 V LVTTL
Note
PD4482181GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
PD4482181GF-A85Y
8.5
100
PD4482321GF-A65Y
6.5
133
3.3 V LVTTL
Note
PD4482321GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
PD4482321GF-A85Y
8.5
100
PD4482361GF-A65Y
6.5
133
3.3 V LVTTL
Note
PD4482361GF-A75Y
7.5
117
3.3 V or 2.5 V LVTTL
PD4482361GF-A85Y
8.5
100
PD4482161GF-C75Y
7.5
117
2.5 0.125
2.5 V LVTTL
PD4482161GF-C85Y
8.5
100
PD4482181GF-C75Y
7.5
117
PD4482181GF-C85Y
8.5
100
PD4482321GF-C75Y
7.5
117
PD4482321GF-C85Y
8.5
100
PD4482361GF-C75Y
7.5
117
PD4482361GF-C85Y
8.5
100
Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A75Y (117 MHz).
4
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Pin Configurations
/
indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[
PD4482161GF,
PD4482181GF]
Marking Side
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
NC
V
DD
NC
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
NC
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
NC
NC
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for the 1-pin index mark.
5
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Pin Identification (
PD4482161GF, PD4482181GF)
Symbol
Pin No.
Description
A0 to A18
37, 36, 35, 34, 33, 32, 100, 99, 82,
Synchronous Address Input
81, 44, 45, 46, 47, 48, 49, 50, 43, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9,
Synchronous Data In,
12, 13, 18, 19, 22, 23
Synchronous / Asynchronous Data Out
I/OP1, NC
Note
74
Synchronous Data In (Parity),
I/OP2, NC
Note
24
Synchronous / Asynchronous Data Out (Parity)
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1, /BW2, /BWE
93, 94, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,
No Connection
38, 39, 42, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Note NC (No Connection) is used in the
PD4482161GF.
I/OP1 and I/OP2 are used in the
PD4482181GF.
6
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
100-pin PLASTIC LQFP (14 x 20)
[
PD4482321GF, PD4482361GF]
Marking Side
I/OP3, NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1, NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
/BW4
/BW3
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for the 1-pin index mark.
7
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Pin Identification (
PD4482321GF, PD4482361GF)
Symbol
Pin No.
Description
A0 to A17
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input
45, 46, 47, 48, 49, 50, 43
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72,
Synchronous Data In,
73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13,
Synchronous / Asynchronous Data Out
18, 19, 22, 23, 24, 25, 28, 29
I/OP1, NC
Note
51
Synchronous Data In (Parity),
I/OP2, NC
Note
80
Synchronous / Asynchronous Data Out (Parity)
I/OP3, NC
Note
1
I/OP4, NC
Note
30
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1 to /BW4, /BWE
93, 94, 95, 96, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
14, 16, 38, 39, 42, 66
No Connection
Note NC (No Connection) is used in the
PD4482321GF.
I/OP1 to I/OP4 are used in the
PD4482361GF.
8
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Block Diagrams
[
PD4482161,
PD4482181]
Address
register
Binary
counter
and logic
CLR
Q0
Q1
Byte 1
Write register
Byte 1
Write driver
8/9
Byte 2
Write register
Byte 2
Write driver
8/9
Enable
register
Row and column
Input
register
Output
buffer
19
19
17
19
A0, A1
A1'
A0'
2
16/18
A0 to A18
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O16
I/OP1 to I/OP2
ZZ
Power down control
16/18
16/18
Memory cell array
1,024 rows
512
16 columns
(8,388,608 bits)
512
18 columns
(9,437,184 bits)
decoders
Burst Sequence
[
PD4482161,
PD4482181]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A18 to A2, A1, A0
1st Burst Address
A18 to A2, A1, /A0
2nd Burst Address
A18 to A2, /A1, A0
3rd Burst Address
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE =
V
SS
)
External Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
1st Burst Address
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
2nd Burst Address
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
3rd Burst Address
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
9
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
[
PD4482321, PD4482361]
Address
register
Binary
counter
and logic
CLR
Q0
Q1
Byte 1
Write register
Byte 1
Write driver
8/9
Byte 2
Write register
Byte 2
Write driver
8/9
Byte 3
Write register
Byte 3
Write driver
8/9
Byte 4
Write register
Byte 4
Write driver
8/9
Enable
register
Row and column
Input
register
Output
buffer
32/36
18
18
16
18
A0, A1
A1'
A0'
32/36
4
32/36
A0 to A17
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O32
I/OP1 to I/OP4
ZZ
Power down control
Memory cell array
1,024 rows
256
32 columns
(8,388,608 bits)
256
36 columns
(9,437,184 bits)
decoders
Burst Sequence
[
PD4482321, PD4482361]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A17 to A2, A1, A0
1st Burst Address
A17 to A2, A1, /A0
2nd Burst Address
A17 to A2, /A1, A0
3rd Burst Address
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE =
V
SS
)
External Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
1st Burst Address
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
2nd Burst Address
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
3rd Burst Address
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
10
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Asynchronous Truth Table
Operation
/G
I/O
Read Cycle
L
Dout
Read Cycle
H
High-Z
Write Cycle
High-Z, Din
Deselected
High-Z
Remark
: don't care
Synchronous Truth Table
Operation
/CE
CE2
/CE2
/AP
/AC
/ADV
/WRITE
CLK
Address
Deselected
Note
H
L
L
H
None
Deselected
Note
L
L
L
L
H
None
Deselected
Note
L
H
L
L
H
None
Deselected
Note
L
L
H
L
L
H
None
Deselected
Note
L
H
H
L
L
H
None
Read Cycle / Begin Burst
L
H
L
L
L
H
External
Read Cycle / Begin Burst
L
H
L
H
L
H
L
H
External
Read Cycle / Continue Burst
H
H
L
H
L
H
Next
Read Cycle / Continue Burst
H
H
L
H
L
H
Next
Read Cycle / Suspend Burst
H
H
H
H
L
H
Current
Read Cycle / Suspend Burst
H
H
H
H
L
H
Current
Write Cycle / Begin Burst
L
H
L
H
L
L
L
H
External
Write Cycle / Continue Burst
H
H
L
L
L
H
Next
Write Cycle / Continue Burst
H
H
L
L
L
H
Next
Write Cycle / Suspend Burst
H
H
H
L
L
H
Current
Write Cycle / Suspend Burst
H
H
H
L
L
H
Current
Note Deselect status is held until new "Begin Burst" entry.
Remarks 1.
: don't care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW
or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1 to /BW4 and /GW are HIGH, and /BWE is LOW.
11
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Partial Truth Table for Write Enables
[
PD4482161,
PD4482181]
Operation
/GW
/BWE
/BW1
/BW2
Read Cycle
H
H
Read Cycle
H
L
H
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
H
L
L
H
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
H
L
H
L
Write Cycle / All Bytes
H
L
L
L
Write Cycle / All Bytes
L
Remark
: don't care
[
PD4482321, PD4482361]
Operation
/GW
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
H
H
Read Cycle
H
L
H
H
H
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
H
L
L
H
H
H
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
H
L
H
L
H
H
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
H
L
H
H
L
H
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
H
L
H
H
H
L
Write Cycle / All Bytes
H
L
L
L
L
L
Write Cycle / All Bytes
L
Remark
: don't care
ZZ (Sleep) Truth Table
ZZ
Chip Status
0.2 V
Active
Open
Active
V
DD
- 0.2 V
Sleep
12
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Notes
Supply voltage
V
DD
-A65, -A75, -A85
0.5
+4.0
V
-A65Y, -A75Y, -A85Y
-C75, -C85
0.5
+3.0
V
-C75Y, -C85Y
Output supply voltage
V
DD
Q
0.5
V
DD
V
Input voltage
V
IN
0.5
V
DD
+ 0.5
V
1, 2
Input / Output voltage
V
I/O
0.5
V
DD
Q
+ 0.5
V
1, 2
Operating ambient
T
A
-A65, -A75, -A85, -C75, -C85
0
70
C
temperature
-A65Y, -A75Y, -A85Y, -C75Y, -C85Y
40
+85
Storage temperature
T
stg
55
+125
C
Notes 1. 2.0 V (MIN.)(Pulse width : 2 ns)
2. V
DD
Q + 2.3 V (MAX.)(Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
(1/2)
Parameter
Symbol
Conditions
-A65, -A75, -A85
Unit
-A65Y, -A75Y, -A85Y
MIN.
TYP.
MAX.
Supply voltage
V
DD
3.135
3.3
3.465
V
2.5 V LVTTL interface
Output supply voltage
V
DD
Q
2.375
2.5
2.9
V
High level input voltage
V
IH
1.7
V
DD
Q
+ 0.3
V
Low level input voltage
V
IL
0.3
Note
+0.7
V
3.3 V LVTTL interface
Output supply voltage
V
DD
Q
3.135
3.3
3.465
V
High level input voltage
V
IH
2.0
V
DD
Q
+ 0.3
V
Low level input voltage
V
IL
0.3
Note
+0.8
V
Note 0.8 V (MIN.)(Pulse width : 2 ns)
Recommended DC Operating Conditions
(2/2)
Parameter
Symbol
Conditions
-C75, -C85
Unit
-C75Y, -C85Y
MIN.
TYP.
MAX.
Supply voltage
V
DD
2.375
2.5
2.625
V
Output supply voltage
V
DD
Q
2.375
2.5
2.625
V
High level input voltage
V
IH
1.7
V
DD
Q
+ 0.3
V
Low level input voltage
V
IL
0.3
Note
+0.7
V
Note 0.8 V (MIN.)(Pulse width : 2 ns)
13
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Note
Input leakage current
I
LI
V
IN
(except ZZ, MODE) = 0 V to V
DD
2
+2
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
DD
Q, Outputs are disabled.
2
+2
A
Operating supply current
I
DD
Device selected,
-A65
250
mA
Cycle = MAX.
-A65Y
V
IN
V
IL
or V
IN
V
IH
,
-A75, -C75
225
I
I/O
= 0 mA
-A75Y, -C75Y
-A85, -C85
200
-A85Y, -C85Y
I
DD1
Suspend cycle, Cycle = MAX.
150
/AC, /AP, /ADV, /GW, /BWEs
V
IH
V
IN
V
IL
or V
IN
V
IH
, I
I/O
= 0 mA
Standby supply current
I
SB
Device deselected, Cycle = 0 MHz
30
mA
V
IN
V
IL
or V
IN
V
IH
, All inputs are static.
I
SB1
Device deselected, Cycle = 0 MHz
15
V
IN
0.2 V or V
IN
V
DD
0.2 V
V
I/O
0.2 V, All inputs are static.
I
SB2
Device deselected, Cycle = MAX.
110
V
IN
V
IL
or V
IN
V
IH
Power down supply current
I
SBZZ
ZZ
V
DD
0.2 V, V
I/O
V
DD
Q + 0.2 V
15
mA
2.5 V LVTTL interface
High level output voltage
V
OH
I
OH
= 2.0 mA
1.7
V
I
OH
= 1.0 mA
2.1
Low level output voltage
V
OL
I
OL
= +2.0 mA
0.7
V
I
OL
= +1.0 mA
0.4
3.3 V LVTTL interface
High level output voltage
V
OH
I
OH
= 4.0 mA
2.4
V
Low level output voltage
V
OL
I
OL
= +8.0 mA
0.4
V
Capacitance (T
A
= 25 C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
6.0
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
8.0
pF
Clock input capacitance
C
clk
V
clk
= 0 V
6.0
pF
Remark These parameters are periodically sampled and not 100
% tested.
14
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
2.5 V LVTTL interface
Input waveform (Rise / Fall time
2.4 ns)
Test points
V
SS
2.4 V
1.2 V
1.2 V
Output waveform
Test points
1.2 V
1.2 V
3.3
V LVTTL interface
Input waveform (Rise / Fall time
3.0 ns)
Test points
V
SS
3.0 V
1.5 V
1.5 V
Output waveform
Test points
1.5 V
1.5 V
Output load condition
C
L
: 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
External load at test
V
T
= +1.2 V / +1.5 V
I/O (Output)
50
Z
O
= 50
C
L
Remark C
L
includes capacitances of the probe and jig, and stray capacitances.
15
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Read and Write Cycle (2.5 V LVTTL Interface)
Parameter
Symbol
-A65, -A75, -C75
-A85, -C85
Unit Note
-A65Y, -A75Y, -C75Y
-A85Y, -C85Y
(117 MHz)
(100MHz)
Standard
Alias
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TCYC
8.6
10.0
ns
Clock access time
TKHQV
TCD
7.5
8.5
ns
Output enable access time
TGLQV
TOE
3.5
3.5
ns
Clock high to output active
TKHQX1
TDC1
2.5
2.5
ns
Clock high to output change
TKHQX2
TDC2
2.5
2.5
ns
Output enable to output active
TGLQX
TOLZ
0
0
ns
Output disable to output High-Z TGHQZ
TOHZ
0
3.5
0
3.5
ns
Clock high to output High-Z
TKHQZ
TCZ
2.5
5.0
2.5
5.0
ns
Clock high pulse width
TKHKL
TCH
2.5
2.5
ns
Clock low pulse width
TKLKH
TCL
2.5
2.5
ns
Setup times Address
TAVKH
TAS
1.5
2.0
ns
Address status
TADSVKH
TSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Address advance TADVVKH
Chip enable
TEVKH
Hold times
Address
TKHAX
TAH
0.5
0.5
ns
Address status
TKHADSX
TSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Address advance TKHADVX
Chip enable
TKHEX
Power down entry time
TZZE
TZZE
8.6
10.0
ns
Power down recovery time
TZZR
TZZR
8.6
10.0
ns
16
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Read and Write Cycle (3.3 V LVTTL Interface)
Parameter
Symbol
-A65
-A75
-A85
Unit Note
-A65Y
-A75Y
-A85Y
(133 MHz)
(117 MHz)
(100MHz)
Standard
Alias
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TCYC
7.5
8.6
10.0
ns
Clock access time
TKHQV
TCD
6.5
7.5
8.5
ns
Output enable access time
TGLQV
TOE
3.5
3.5
3.5
ns
Clock high to output active
TKHQX1
TDC1
2.5
2.5
2.5
ns
Clock high to output change
TKHQX2
TDC2
2.5
2.5
2.5
ns
Output enable to output active
TGLQX
TOLZ
0
0
0
ns
Output disable to output High-Z TGHQZ
TOHZ
0
3.5
0
3.5
0
3.5
ns
Clock high to output High-Z
TKHQZ
TCZ
2.5
5.0
2.5
5.0
2.5
5.0
ns
Clock high pulse width
TKHKL
TCH
2.5
2.5
2.5
ns
Clock low pulse width
TKLKH
TCL
2.5
2.5
2.5
ns
Setup times Address
TAVKH
TAS
1.5
1.5
2.0
ns
Address status
TADSVKH
TSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Address advance TADVVKH
Chip enable
TEVKH
Hold times
Address
TKHAX
TAH
0.5
0.5
0.5
ns
Address status
TKHADSX
TSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Address advance TKHADVX
Chip enable
TKHEX
Power down entry time
TZZE
TZZE
7.5
8.6
10.0
ns
Power down recovery time
TZZR
TZZR
7.5
8.6
10.0
ns
17
PD4482161, 4482181
, 4482321
, 4482361
Data S
h
e
e
t
M1
45
21E
J
3
V
0
DS
TKHKH
TKLKH
TKHAX
TWVKH
TKHWX
TKHEX
TGLQV
TGLQX
TKHQX2
TKHQZ
Q1(A1)
Q1(A2)
Q2(A2)
Q3(A2)
Q4(A2)
Q1(A3)
A1
A2
A3
CLK
/AP
/AC
Address
/ADV
/CEs
Note
/G
Data In
/BWE
/BWs
TGHQZ
TKHQV
TKHKL
TKHADSX
TADSVKH
TAVKH
TEVKH
TADSVKH
TKHADSX
TADVVKH
TKHADVX
TWVKH
TKHWX
/GW
Data Out
READ CYCLE
Remark Qn(A2) refers to output from address A2. Q1 to Q4 refer to outputs according to burst sequence.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Note
Q1(A2)
High-Z
High-Z
High-Z
High-Z
18
PD4482161, 4482181
, 4482321
, 4482361
Data S
h
e
e
t
M1
45
21E
J
3
V
0
DS
TKHKH
TAVKH
TKHAX
TEVKH
TKHEX
D1(A1)
D1(A2)
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
TKHKL
TKLKH
A1
A2
A3
TDVKH
TKHDX
TKHADSX
TWVKH
TKHWX
CLK
/AP
/AC
Address
/ADV
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
TADVVKH
TWVKH
TKHADVX
TKHWX
TADSVKH TKHADSX
TADSVKH
WRITE CYCLE
Notes
2.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
TGHQZ
High-Z
High-Z
19
PD4482161, 4482181
, 4482321
, 4482361
Data S
h
e
e
t
M1
45
21E
J
3
V
0
DS
TKHKH
TKLKH
TKHKL
TAVKH
TEVKH
TKHEX
TKHQV
TGLQX
Q1(A1)
Q1(A3)
Q2(A3)
Q3(A3)
A3
A2
A1
TGHQZ
TKHQX1
TDVKH
TKHDX
D1(A2)
TADSVKH TKHADSX
TKHAX
TADSVKH TKHADSX
CLK
/AP
/AC
Address
/ADV
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
TWVKH
TKHWX
TWVKH
TKHWX
Q4(A3)
TADVVKH
TKHADVX
Notes
2.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
READ / WRITE CYCLE
High-Z
High-Z
High-Z
High-Z
High-Z
20
PD4482161, 4482181
, 4482321
, 4482361
Data S
h
e
e
t
M1
45
21E
J
3
V
0
DS
TKHKH
TKLKH
TKHKL
TWVKH TKHWX
TAVKH
TEVKH
TKHEX
TGHQZ
High-Z
Q1(A1)
Q1(A2)
Q1(A3)
Q1(A4)
A3
A2
TDVKH TKHDX
TWVKH TKHWX
TKHAX
TADSVKH TKHADSX
CLK
/AC
Address
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
Notes
2.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
SINGLE READ / WRITE CYCLE
A4
A5
A6
A7
A1
A8
A9
Q1(A8)
Q1(A9)
D1(A5)
D1(A6)
D1(A7)
TGLQX
TKHQV
TGLQV
TKHQZ
Remark /AP is HIGH and /ADV is don't care.
Note3
3. Outputs are disabled within one clock cycle after deselect.
High-Z
High-Z
High-Z
21
PD4482161, 4482181
, 4482321
, 4482361
Data S
h
e
e
t
M1
45
21E
J
3
V
0
DS
TKHKH
ZZ
TKLKH
A1
A2
TZZE
TZZR
Power Down (I
SBZZ
) State
Q2(A2)
TKHKL
CLK
/AP
/AC
Address
/ADV
/CEs
/G
/BWE
/BWs
/GW
Data Out
POWER DOWN (ZZ) CYCLE
Q1(A2)
Q1(A1)
High-Z
High-Z
22
PD4482161, 4482181
, 4482321
, 4482361
Data S
h
e
e
t
M1
45
21E
J
3
V
0
DS
TKHKH
Data Out
TKHKL
TKLKH
A1
A2
Power Down State (I
SB1
)
Note
Q1(A1)
Q1(A2)
Data In
CLK
/AP
/AC
Address
/ADV
/CE
/G
/BWE
/BWs
/GW
Q2(A2)
STOP CLOCK CYCLE
Note V
IN
0.2 V or V
IN
V
DD
-
0.2 V, V
I/O
0.2 V
High-Z
High-Z
High-Z
High-Z
23
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Package Drawing
100-PIN PLASTIC LQFP (14x20)
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
22.0
0.2
20.0
0.2
0.65 (T.P.)
0.575
J
16.0
0.2
K
C
14.0
0.2
I
0.13
1.0
0.2
L
0.5
0.2
F
0.825
N
P
Q
0.10
1.4
0.125
0.075
S100GF-65-8ET-1
S
1.7 MAX.
H
0.32
+
0.08
-
0.07
M
0.17
+
0.06
-
0.05
R
3
+
7
-
3
M
80
81
51
50
30
31
100
1
S
S
N
J
detail of lead end
C
D
A
B
R
K
M
L
P
I
S
Q
G
F
H
24
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the
PD4482161, 4482181, 4482321 and 4482361.
Types of Surface Mount Devices
PD4482161GF : 100-pin PLASTIC LQFP (14 x 20)
PD4482181GF : 100-pin PLASTIC LQFP (14 x 20)
PD4482321GF
:
100-pin PLASTIC LQFP (14 x 20)
PD4482361GF : 100-pin PLASTIC LQFP (14 x 20)
25
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Revision History
Edition/
Page
Type of
Location
Description
Date
This
Previous
revision
(Previous edition
This edition)
edition
edition
3rd edition/
Throughout Throughout Modification
-
Preliminary Data Sheet
Data Sheet
Dec. 2002
Addition
-
Extended operating temperature products
(T
A
=
-40 to +85 C)
p.20
-
Addition
Timing Chart
SINGLE READ / WRITE CYCLE
26
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
[MEMO]
27
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD4482161, 4482181, 4482321, 4482361
The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special":
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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