Document Outline
- COVER
- Features
- Ordering Information
- Pin Configurations
- Block Diagram
- 1. Initialization
- 2. Partial Refresh
- 2.1 Standby Mode
- 2.2 Density Switching
- 2.3 Standby Mode Status Transition
- 2.4 Addresses for Which Partial Refresh Is Supported
- 3. Page Read Operation
- 3.1 Features of Page Read Operation
- 3.2 Page Length
- 3.3 Page-Corresponding Addresses
- 3.4 Page Start Address
- 3.5 Page Direction
- 3.6 Interrupt during Page Read Operation
- 3.7 When page read is not used
- 4. Mode Register Settings
- 4.1 Mode Register Setting Method
- 4.2 Cautions for Setting Mode Register
- 5. Electrical Specifications
- 6. Timing Charts
- 7. Package Drawing
- 8. Recommended Soldering Conditions
- 9. Revision History
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
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Document No. M15874EJ5V0DS00 (5th edition)
Date Published January 2003 NS CP (K)
Printed in Japan
MOS INTEGRATED CIRCUIT
PD4632312A-X
32M-BIT CMOS MOBILE SPECIFIED RAM
2M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
PRELIMINARY DATA SHEET
The mark
# shows major revised points.
2001
Description
The
PD4632312A-X is a high speed, low power, 33,554,432 bits (2,097,152 words by 16 bits) CMOS Mobile
Specified RAM featuring Low Power Static RAM compatible function and pin configuration.
The
PD4632312A-X is fabricated with advanced CMOS technology using one-transistor memory cell.
The
PD4632312A-X is packed in 48-pin TAPE FBGA.
Features
2,097,152 words by 16 bits organization
Fast access time: 60, 65, 75, 85 ns (MAX.)
Fast page access time: 18, 25, 30 ns (MAX.)
Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)
Low voltage operation: 2.7 to 3.1 V (-B60X, -B65X)
2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X, -BE85X)
Operating ambient temperature: T
A
= 25 to +85 C
Output Enable input for easy application
Chip Enable input: /CS pin
Standby Mode input: MODE pin
Standby Mode1: Normal standby (Memory cell data hold valid)
Standby Mode2: Density of memory cell data hold is variable
PD4632312A
Access
Operating supply
Operating
Supply current
time
voltage
ambient
At operating
At standby
A (MAX.)
ns (MAX.)
V
temperature mA (MAX.)
Density of data hold
Chip
I/O
C
32M bits 16M bits 8M bits 4M bits 0M bit
-B60X
Note
, -B65X
60, 65
2.7 to 3.1
25 to +85
50
100
70
60
50
30
-BE75X
Note
, -BE85X
Note
75, 85
2.7 to 3.1 1.65 to 2.1
45
Note Under development
Preliminary Data Sheet M15874EJ5V0DS
2
PD4632312A-X
Ordering Information
Part number
Package
Access time
Operating supply voltage
Operating
ns (MAX.)
V
temperature
Chip
I/O
C
PD4632312AF9-B60X-BC2
Note
48-pin TAPE FBGA (8 x 6)
60
2.7 to 3.1
25 to +85
PD4632312AF9-B65X-BC2
65
PD4632312AF9-BE75X-BC2
Note
75
2.7 to 3.1
1.65 to 2.1
PD4632312AF9-BE85X-BC2
Note
85
Note Under development
Preliminary Data Sheet M15874EJ5V0DS
3
PD4632312A-X
Pin Configurations
/xxx indicates active low signal.
48-pin TAPE FBGA (8 x 6)
[
PD4632312AF9-B60X-BC2 ]
[
PD4632312AF9-B65X-BC2 ]
A
B
C
D
E
F
G
H
1
2
3
4
5
6
Bottom View
6
5
4
3
2
1
Top View
1
2
3
4
5
6
6
5
4
3
2
1
A
/LB
/OE
A0
A1
A2
MODE
A
MODE
A2
A1
A0
/OE
/LB
B
I/O8
/UB
A3
A4
/CS
I/O0
B
I/O0
/CS
A4
A3
/UB
I/O8
C
I/O9
I/O10
A5
A6
I/O1
I/O2
C
I/O2
I/O1
A6
A5
I/O10
I/O9
D
GND
I/O11
A17
A7
I/O3
V
CC
D
V
CC
I/O3
A7
A17
I/O11
GND
E
V
CC
I/O12
NC
A16
I/O4
GND
E
GND
I/O4
A16
NC
I/O12
V
CC
F
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O6
I/O5
A15
A14
I/O13
I/O14
G
I/O15
A19
A12
A13
/WE
I/O7
G
I/O7
/WE
A13
A12
A19
I/O15
H
A18
A8
A9
A10
A11
A20
H
A20
A11
A10
A9
A8
A18
Note Some signals can be applied because this pin is not internally connected.
Remark Refer to Package Drawing for the index mark.
A0 to A20
: Address inputs
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip select
MODE
: Standby mode
/WE
: Write enable
/OE
: Output enable
/LB, /UB
: Byte data select
V
CC
: Power supply
GND
: Ground
NC
Note
: No connection
Preliminary Data Sheet M15874EJ5V0DS
4
PD4632312A-X
48-pin TAPE FBGA (8 x 6)
[
PD4632312AF9-BE75X-BC2 ]
[
PD4632312AF9-BE85X-BC2 ]
A
B
C
D
E
F
G
H
1
2
3
4
5
6
Bottom View
6
5
4
3
2
1
Top View
1
2
3
4
5
6
6
5
4
3
2
1
A
/LB
/OE
A0
A1
A2
MODE
A
MODE
A2
A1
A0
/OE
/LB
B
I/O8
/UB
A3
A4
/CS
I/O0
B
I/O0
/CS
A4
A3
/UB
I/O8
C
I/O9
I/O10
A5
A6
I/O1
I/O2
C
I/O2
I/O1
A6
A5
I/O10
I/O9
D
GND
I/O11
A17
A7
I/O3
V
CC
D
V
CC
I/O3
A7
A17
I/O11
GND
E
V
CC
Q
I/O12
NC
A16
I/O4
GND
E
GND
I/O4
A16
NC
I/O12
V
CC
Q
F
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O6
I/O5
A15
A14
I/O13
I/O14
G
I/O15
A19
A12
A13
/WE
I/O7
G
I/O7
/WE
A13
A12
A19
I/O15
H
A18
A8
A9
A10
A11
A20
H
A20
A11
A10
A9
A8
A18
Note Some signals can be applied because this pin is not internally connected.
Remark Refer to Package Drawing for the index mark.
A0 to A20
: Address inputs
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip Select
MODE
: Standby mode
/WE
: Write enable
/OE
: Output enable
/LB, /UB
: Byte data select
V
CC
: Power supply
V
CC
Q
: Input / Output power supply
GND
: Ground
NC
Note
: No connection
Preliminary Data Sheet M15874EJ5V0DS
5
PD4632312A-X
Block Diagram
A0
A20
I/O8 to I/O15
/WE
/OE
/UB
/LB
I/O0 to I/O7
V
CC
V
CC
Q
GND
MODE
Refresh
counter
Refresh
control
Standby mode control
Address buffer
Address
buffer
Row
decoder
Memory cell array
33,554,432 bits
Input data
controller
Sense amplifier /
Switching circuit
Column decoder
Output data
controller
/CS
Remark V
CC
Q is the input / output power supply for -BE75X and -BE85X.
Preliminary Data Sheet M15874EJ5V0DS
6
PD4632312A-X
Truth Table
/CS
MODE
/OE
/WE
/LB
/UB
Mode
I/O
Supply
I/O0 to I/O7
I/O8 to I/O15
current
H
H
Not selected (Standby Mode 1)
High-Z
High-Z
I
SB1
H
H
H
Not selected (Standby Mode 1)
High-Z
High-Z
L
Not selected (Standby Mode 2)
Note
High-Z
High-Z
I
SB2
L
H
H
H
Output disable
High-Z
High-Z
I
CCA
L
H
L
L
Word read
D
OUT
D
OUT
L
H
Lower byte read
D
OUT
High-Z
H
L
Upper byte read
High-Z
D
OUT
H
L
L
L
Word write
D
IN
D
IN
L
H
Lower byte write
D
IN
High-Z
H
L
Upper byte write
High-Z
D
IN
Note MODE pin must be fixed to high level except Standby Mode 2. (refer to 2.3 Standby Mode Status Transition).
Remark
: V
IH
or V
IL
, H: V
IH
, L: V
IL
Preliminary Data Sheet M15874EJ5V0DS
7
PD4632312A-X
CONTENTS
1. Initialization .................................................................................................................................................................... 8
2. Partial Refresh ............................................................................................................................................................... 9
2.1 Standby Mode........................................................................................................................................................... 9
2.2 Density Switching...................................................................................................................................................... 9
2.3 Standby Mode Status Transition............................................................................................................................... 9
2.4 Addresses for Which Partial Refresh Is Supported ................................................................................................ 10
3. Page Read Operation .................................................................................................................................................. 11
3.1 Features of Page Read Operation.......................................................................................................................... 11
3.2 Page Length ........................................................................................................................................................... 11
3.3 Page-Corresponding Addresses............................................................................................................................. 11
3.4 Page Start Address................................................................................................................................................. 11
3.5 Page Direction ........................................................................................................................................................ 11
3.6 Interrupt during Page Read Operation.................................................................................................................... 11
3.7 When page read is not used................................................................................................................................... 11
4. Mode Register Settings................................................................................................................................................ 12
4.1 Mode Register Setting Method ............................................................................................................................... 12
4.2 Cautions for Setting Mode Register ........................................................................................................................ 13
5. Electrical Specifications ............................................................................................................................................... 14
6. Timing Charts............................................................................................................................................................... 19
7. Package Drawing......................................................................................................................................................... 29
8. Recommended Soldering Conditions .......................................................................................................................... 30
9. Revision History ........................................................................................................................................................... 31
Preliminary Data Sheet M15874EJ5V0DS
8
PD4632312A-X
1. Initialization
Initialize the
PD4632312A-X at power application using the following sequence to stabilize internal circuits.
(1) Following power application, make MODE high level after fixing MODE to low level for the period of t
VHMH
. Make
/CS high level before making MODE high level.
(2) /CS and MODE are fixed to high level for the period of t
MHCL
.
Normal operation is possible after the completion of initialization.
Figure1-1. Initialization Timing Chart
/CS (Input)
V
CC
MODE (Input)
t
MHCL
Initialization
t
CHMH
t
VHMH
V
CC
(MIN.)
Normal Operation
Cautions 1. Make MODE low level when starting the power supply.
2. t
VHMH
is specified from when the power supply voltage reaches the prescribed minimum value (V
CC
(MIN.)).
Initialization Timing
Parameter
Symbol
MIN.
MAX.
Unit
Power application to MODE low level hold
t
VHMH
50
s
/CS high level to MODE high level
t
CHMH
0
ns
Following power application MODE high level hold to /CS low level
t
MHCL
200
s
Preliminary Data Sheet M15874EJ5V0DS
9
PD4632312A-X
2. Partial Refresh
2.1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 32M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
2.2 Density Switching
In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit.
The density for performing refresh can be set with the mode register. Once the refresh density has been set in the
mode register, these settings are retained until they are set again, while applying the power supply. However, the mode
register setting will become undefined if the power is turned off, so set the mode register again after power application.
(For how to perform mode register settings, refer to section 4. Mode Register Settings.)
2.3 Standby Mode Status Transition
In Standby Mode 1, MODE and /CS are high level, or MODE, /LB and /UB are high level. In Standby Mode 2, MODE is
low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after
applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 16M bits,
8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from
Standby Mode 2.
For the timing charts, refer to Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit
Timing Chart, Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart.
Preliminary Data Sheet M15874EJ5V0DS
10
PD4632312A-X
Figure 2-1. Standby Mode State Machine
Power On
Active
MODE = V
IH
MODE = V
IL
MODE = V
IL
/CS = V
IL
,
MODE = V
IH
Standby
Mode 1
Standby Mode 2
(16M bits / 8M bits
/ 4M bits)
/CS = V
IL
Initial State
Initialization
Standby Mode 2
(Data not held)
/CS = V
IL
,
MODE = V
IH
MODE = V
IL
MODE = V
IL
MODE = V
IH
,
/CS = V
IH
or
/LB, /UB = V
IH
2.4 Addresses for Which Partial Refresh Is Supported
Data hold density
Correspondence address
16M bits
000000H to 0FFFFFH
8M bits
000000H to 07FFFFH
4M bits
000000H to 03FFFFH
Preliminary Data Sheet M15874EJ5V0DS
11
PD4632312A-X
3. Page Read Operation
3.1 Features of Page Read Operation
Features
8 Words Mode
Page length
8 words
Page read-corresponding addresses
A2, A1, A0
Page read start address
Don't care
Page direction
Don't care
Interrupt during page read operation
Enabled
Note
Note An interrupt is output when /CS = H or in case A3 or a higher address changes.
3.2 Page Length
8 words is supported as the page lengths.
3.3 Page-Corresponding Addresses
The page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during page read
operation.
3.4 Page Start Address
Since random page read is supported, any address (A2, A1, A0) can be used as the page read start address.
3.5 Page Direction
Since random page read is possible, there is not restriction on the page direction.
3.6 Interrupt during Page Read Operation
When generating an interrupt during page read, either make /CS high level or change A3 and higher addresses.
3.7 When page read is not used
Since random page read is supported, even when not using page read, random access is possible as usual.
Preliminary Data Sheet M15874EJ5V0DS
12
PD4632312A-X
4. Mode Register Settings
The partial refresh density can be set using the mode register. Since the initial value of the mode register at power
application is undefined, be sure to set the mode register after initialization at power application. When setting the
density of partial refresh, data before entering the partial refresh mode is not guaranteed. (This is the same for re-
setup.) However, since partial refresh mode is not entered unless MODE = L when partial refresh is not used, it is not
necessary to set the mode register. Moreover, when using page read without using partial refresh, it is not necessary to
set the mode register.
4.1 Mode Register Setting Method
The mode register setting mode can be entered by successively writing two specific data after two continuous reads of
the highest address (1FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two
write cycles).
Commands are written to the command register. The command register is used to latch the addresses and data
required for executing commands, and it does not have an exclusive memory area.
For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode
Register Setting Flow Chart.
Table 4-1. shows the commands and command sequences.
Table 4-1. Command sequence
Command sequence
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
(Read cycle)
(Read cycle)
(Write cycle)
(Write cycle)
Partial refresh density
Address
Data
Address
Data
Address
Data
Address
Data
16M bits
1FFFFFH
1FFFFFH
1FFFFFH
00H
1FFFFFH
04H
8M bits
1FFFFFH
1FFFFFH
1FFFFFH
00H
1FFFFFH
05H
4M bits
1FFFFFH
1FFFFFH
1FFFFFH
00H
1FFFFFH
06H
0M bit
1FFFFFH
1FFFFFH
1FFFFFH
00H
1FFFFFH
07H
4th bus cycle (Write cycle)
I/O
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register setting
0
0
0
0
0
0
0
0
0
0
0
0
0
PL
PD
Page length
1
8 words
I/O1 I/O0
Density
Partial refresh
0
0
16M bits
density
0
1
8M bits
1
0
4M bits
1
1
0M bit
Preliminary Data Sheet M15874EJ5V0DS
13
PD4632312A-X
4.2 Cautions for Setting Mode Register
Since, for the mode register setting, the internal counter status is judged by toggling /CS and /OE, toggle /CS at every
cycle during entry (read cycle twice, write cycle twice), and toggle /OE like /CS at the first and second read cycles.
If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the
mode register are not performed correctly.
When the highest address (1FFFFFH) is read consecutively three or more times, the mode register setting entries are
cancelled.
Once the refresh density has been set in the mode register, these settings are retained until they are set again, while
applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set
the mode register again after power application.
For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode
Register Setting Flow Chart.
Preliminary Data Sheet M15874EJ5V0DS
14
PD4632312A-X
5. Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol Condition
Rating
Unit
-B60X, -B65X
-BE75X, -BE85X
Supply voltage
V
CC
0.5
Note
to +4.0
0.5
Note
to +4.0
V
Input / Output supply voltage
V
CC
Q
0.5
Note
to +4.0
V
Input / Output voltage
V
T
0.5
Note
to V
CC
+ 0.4 (4.0 V MAX.) 0.5
Note
to V
CC
Q + 0.4 (4.0 V MAX.)
V
Operating ambient temperature
T
A
25 to +85
25 to +85
C
Storage temperature
T
stg
55 to +125
55 to +125
C
Note 1.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
-B60X, -B65X
-BE75X, -BE85X
Unit
MIN.
MAX.
MIN.
MAX.
Supply voltage
V
CC
2.7
3.1
2.7
3.1
V
Input / Output supply voltage
V
CC
Q
1.65
2.1
V
High level input voltage
V
IH
0.8V
CC
V
CC
+0.3
0.8V
CC
Q
V
CC
Q+0.3
V
Low level input voltage
V
IL
0.3
Note
0.2V
CC
0.3
Note
0.2V
CC
Q
V
Operating ambient temperature
T
A
25
+85
25
+85
C
Note 0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (T
A
= 25
C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
8
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
10
pF
Remarks 1. V
IN
: Input voltage, V
I/O
: Input / Output voltage
2. These parameters are not 100% tested.
Preliminary Data Sheet M15874EJ5V0DS
15
PD4632312A-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
Density of
-B60X, -B65X
Unit
data hold
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CS = V
IH
or
1.0
+1.0
A
/WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA
/CS = V
IL
, Minimum cycle time, I
I/O
= 0 mA
50
mA
Standby supply current
I
SB1
/CS
V
CC
- 0.2 V, MODE V
CC
- 0.2 V
32M bits
100
A
I
SB2
/CS
V
CC
- 0.2 V, MODE 0.2 V
16M bits
70
8M bits
60
4M bits
50
0M bit
30
High level output voltage
V
OH
I
OH
= 0.5 mA
0.8V
CC
V
Low level output voltage
V
OL
I
OL
= 1 mA
0.2V
CC
V
Remark V
IN
: Input voltage, V
I/O
: Input / Output voltage
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
Density of
-BE75X, -BE85X
Unit
data hold
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
Q
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
Q, /CS = V
IH
or
1.0
+1.0
A
/WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA
/CS = V
IL
, Minimum cycle time, I
I/O
= 0 mA
45
mA
Standby supply current
I
SB1
/CS
V
CC
Q
- 0.2 V, MODE V
CC
Q
- 0.2 V
32M bits
100
A
I
SB2
/CS
V
CC
Q
- 0.2 V, MODE 0.2 V
16M bits
70
8M bits
60
4M bits
50
0M bit
30
High level output voltage
V
OH
I
OH
= 0.5 mA
0.8V
CC
Q
V
Low level output voltage
V
OL
I
OL
= 1 mA
0.2V
CC
Q
V
Remark V
IN
: Input voltage, V
I/O
: Input / Output voltage
Preliminary Data Sheet M15874EJ5V0DS
16
PD4632312A-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ -B60X, -B65X ]
Input Waveform (Rise and Fall Time
5 ns)
Test points
0.2Vcc
0.8Vcc
Vcc / 2
Vcc / 2
Vcc
GND
5ns
Output Waveform
Test points
Vcc / 2
Vcc / 2
[ -BE75X, -BE85X ]
Input Waveform (Rise and Fall Time
5 ns)
Test points
0.2VccQ
0.8VccQ
VccQ / 2
VccQ / 2
VccQ
GND
5ns
Output Waveform
Test points
VccQ / 2
VccQ / 2
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 5-1, Figure 5-2
.
Figure 5-1.
Figure 5-2.
[ -B60X, -B65X ]
[ -BE75X, -BE85X ]
C
L
: 30 pF
C
L
: 30 pF
5 pF (t
CLZ
, t
OLZ
, t
BLZ
, t
CHZ
, t
OHZ
, t
BHZ
)
5 pF (t
CLZ
, t
OLZ
, t
BLZ
, t
CHZ
, t
OHZ
, t
BHZ
)
I/O (Output)
50
Z
O
= 50
C
L
V
CC
/ 2
I/O (Output)
50
Z
O
= 50
C
L
V
CC
Q
/ 2
Remark C
L
includes capacitance of the probe and jig, and stray capacitance.
Preliminary Data Sheet M15874EJ5V0DS
17
PD4632312A-X
Read Cycle
Parameter
Symbol
-B60X
-B65X
-BE75X
-BE85X
Unit
Note
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
65
65
75
85
ns
1
Address access time
t
AA
60
65
75
85
ns
/CS access time
t
ACS
63
65
75
85
ns
/OE to output valid
t
OE
45
45
50
55
ns
/LB, /UB to output valid
t
BA
63
65
75
85
ns
Output hold from address change
t
OH
5
5
5
5
ns
Page read cycle time
t
PRC
18
18
25
30
ns
Page access time
t
PAA
18
18
25
30
ns
/CS to output in low impedance
t
CLZ
10
10
10
10
ns
2
/OE to output in low impedance
t
OLZ
5
5
5
5
ns
/LB, /UB to output in low impedance
t
BLZ
5
5
5
5
ns
/CS to output in high impedance
t
CHZ
25
25
25
25
ns
/OE to output in high impedance
t
OHZ
25
25
25
25
ns
/LB, /UB to output in high impedance
t
BHZ
25
25
25
25
ns
Address set to /OE low level
t
ASO
0
0
0
0
ns
/OE high level to address hold
t
OHAH
5
5
5
5
ns
/CS high level to address hold
t
CHAH
0
0
0
0
ns
3
/LB, /UB high level to address hold
t
BHAH
0
0
0
0
ns
3, 4
/CS low level to /OE low level
t
CLOL
0
10,000
0
10,000
0
10,000
0
10,000
ns
5
/OE low level to /CS high level
t
OLCH
45
45
50
55
ns
/CS high level pulse width
t
CP
10
10
10
10
ns
/LB, /UB high level pulse width
t
BP
10
10
10
10
ns
/OE high level pulse width
t
OP
2
10,000
2
10,000
2
10,000
2
10,000
ns
5
Notes 1. Output load: 30 pF
2. Output load: 5 pF
3. When t
ASO
| t
CHAH
|, | t
BHAH
|, t
CHAH
and t
BHAH
(MIN.) are 15 ns.
t
CHAH
, t
BHAH
t
ASO
/LB, /UB, /CS (Input)
Address (Input)
/OE (Input)
4. t
BHAH
is specified from when both /LB and /UB become high level.
5. t
CLOL
and t
OP
(MAX.) are applied while /CS is being hold at low level.
Preliminary Data Sheet M15874EJ5V0DS
18
PD4632312A-X
Write Cycle
Parameter
Symbol
-B60X
-B65X
-BE75X
-BE85X
Unit
Note
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
65
65
75
85
ns
/CS to end of write
t
CW
55
55
60
70
ns
Address valid to end of write
t
AW
55
55
60
70
ns
/LB, /UB to end of write
t
BW
55
55
60
70
ns
Write pulse width
t
WP
50
50
55
60
ns
Write recovery time
t
WR
0
0
0
0
ns
/CS pulse width
t
CP
10
10
10
10
ns
/LB, /UB high level pulse width
t
BP
10
10
10
10
ns
/WE high level pulse width
t
WHP
10
10
10
10
ns
Address setup time
t
AS
0
0
0
0
ns
/OE high level to address hold
t
OHAH
5
5
5
5
ns
/CS high level to address hold
t
CHAH
0
0
0
0
ns
1
/LB, /UB high level to address hold
t
BHAH
0
0
0
0
ns
1, 2
Data valid to end of write
t
DW
30
30
35
35
ns
Data hold time
t
DH
0
0
0
0
ns
/OE high level to /WE set
t
OES
0
10,000
0
10,000
0
10,000
0
10,000
ns
3
/WE high level to /OE set
t
OEH
10
10,000
10
10,000
10
10,000
10
10,000
ns
Notes 1. When t
AS
| t
CHAH
|, | t
BHAH
| and t
CP
18 ns, t
CHAH
and t
BHAH
(MIN.) are 15 ns.
t
CHAH
, t
BHAH
t
AS
/LB, /UB, /CS (Input)
Address (Input)
/WE (Input)
2. t
BHAH
is specified from when both /LB and /UB become high level.
3. t
OES
and t
OEH
(MAX.) are applied while /CS is being hold at low level.
Preliminary Data Sheet M15874EJ5V0DS
19
PD4632312A-X
6. Timing Charts
Figure 6-1. Read Cycle Timing Chart 1 (/CS Controlled)
/CS (Input)
Address (Input)
Data Out
Q2
I/O (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
L
L
Data Out
Q1
t
RC
t
ACS
t
ACS
t
CP
A1
A2
A3
t
CP
t
CLZ
t
CLZ
t
CHZ
t
CHZ
t
CHAH
t
CHAH
/LB, /UB (Input)
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-2. Read Cycle Timing Chart 2 (/OE Controlled)
/CS (Input)
Address (Input)
Data Out Q2
I/O (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
t
ASO
Data Out Q1
t
OE
t
RC
t
AA
t
ASO
t
OE
t
ASO
t
OP
t
OP
A1
A2
A3
t
OHZ
t
OLZ
t
OHZ
t
OLZ
t
OHAH
t
OHAH
t
AA
/LB, /UB (Input)
t
BHAH
t
BHAH
L
Remark In read cycle, MODE and /WE should be fixed to high level.
Preliminary Data Sheet M15874EJ5V0DS
20
PD4632312A-X
Figure 6-3. Read Cycle Timing Chart 3 (/CS, /OE Controlled)
/CS (Input)
Address (Input)
Data Out Q2
I/O (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
Data Out Q1
t
RC
t
ACS
t
AA
t
OLCH
A1
A2
A3
t
CLZ
t
OE
t
OHZ
t
CHZ
t
OHAH
t
CHAH
/LB, /UB (Input)
t
CLOL
t
OLZ
t
OHZ
t
OHAH
t
ASO
t
OLZ
t
OE
t
BHAH
t
BHAH
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-4. Read Cycle Timing Chart 4 (Address Controlled)
/CS (Input)
Address (Input)
Data Out
Q2
I/O (Output)
t
RC
/OE (Input)
Data Out
Q1
t
AA
A1
A2
A3
t
RC
t
AA
t
OH
t
OH
t
OH
/LB, /UB (Input)
L
L
L
Remark In read cycle, MODE and /WE should be fixed to high level.
Preliminary Data Sheet M15874EJ5V0DS
21
PD4632312A-X
Figure 6-5. Read Cycle Timing Chart 5 (/LB, /UB Controlled)
/CS (Input)
Address (Input)
I/O (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
t
RC
A1
A2
A3
t
BHAH
t
BHAH
/LB, /UB (Input)
t
BA
t
BHZ
Data Out
Q1
t
BLZ
t
BA
t
BHZ
Data Out
Q2
t
BLZ
t
BP
t
BP
L
L
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-6. Page Read Cycle Timing Chart
I/O (Output)
Address
(A3 to A20) (Input)
Page Address
(A0 to A2) (Input)
/CS (Input)
/OE (Input)
t
PRC
t
PRC
t
PRC
t
RC
t
PAA
t
OH
t
PAA
t
OH
t
PAA
t
OH
t
AA
t
OE
t
OH
A
N+1
A
N+2
A
N+3
A
N+7
Q
N
Q
N+1
Q
N+2
Q
N+3
Q
N+7
t
CHZ
t
OHZ
A
N
t
PAA
t
OH
t
PRC
t
PAA
t
OH
t
PRC
t
PAA
t
OH
t
PRC
t
PAA
t
OH
Q
N+4
Q
N+5
Q
N+6
A
N+4
A
N+5
A
N+6
t
PRC
High-Z
Remarks 1. In read cycle, MODE and /WE should be fixed to high level.
2. /LB and /UB are low level.
Preliminary Data Sheet M15874EJ5V0DS
22
PD4632312A-X
Figure 6-7. Write Cycle Timing Chart 1 (/CS Controlled)
t
WC
t
AS
t
WC
t
AS
t
AS
A1
A2
A3
t
CW
t
CW
t
WR
t
WR
t
CP
t
CP
/CS (Input)
Address (Input)
/WE (Input)
/LB, /UB (Input)
Data In D2
Data In D1
t
DW
t
DH
t
DW
t
DH
/OE (Input)
t
ASO
t
OHAH
t
OES
t
OEH
I/O (Input)
High-Z
High-Z
High-Z
L
L
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15874EJ5V0DS
23
PD4632312A-X
Figure 6-8. Write Cycle Timing Chart 2 (/WE Controlled)
Data In D2
t
WC
t
AS
Data In D1
t
WC
t
AS
t
WHP
A1
A2
A3
t
CW
t
WR
t
CW
t
DW
t
DH
t
DW
t
DH
t
WP
t
WP
/OE (Input)
t
CP
t
ASO
t
OHAH
t
OES
t
OEH
t
BHAH
t
BHAH
t
WR
t
CP
t
CHAH
t
CHAH
/CS (Input)
Address (Input)
I/O (Input)
High-Z
High-Z
High-Z
/WE (Input)
/LB, /UB (Input)
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15874EJ5V0DS
24
PD4632312A-X
Figure 6-9. Write Cycle Timing Chart 3 (/WE Controlled)
t
WC
t
AS
t
WC
t
AS
t
ASO
A1
A2
A3
t
WR
t
WR
/OE (Input)
t
OHAH
t
OES
t
OEH
t
WHP
t
AW
t
AW
t
DW
t
DH
t
DW
t
DH
t
WP
t
WP
t
BHAH
t
BHAH
/CS (Input)
Address (Input)
Data In D2
I/O (Input)
High-Z
High-Z
High-Z
/WE (Input)
Data In D1
/LB, /UB (Input)
L
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15874EJ5V0DS
25
PD4632312A-X
Figure 6-10. Write Cycle Timing Chart 4 (/LB, /UB Controlled)
t
WC
t
AS
t
WC
t
AS
A1
A2
A3
t
WR
t
WR
t
DW
t
DH
t
DW
t
DH
t
BW
t
BW
t
BP
t
BP
t
ASO
/OE (Input)
t
OHAH
t
OES
t
OEH
/CS (Input)
Address (Input)
Data In D2
I/O (Input)
High-Z
High-Z
High-Z
/WE (Input)
Data In D1
/LB, /UB (Input)
L
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15874EJ5V0DS
26
PD4632312A-X
Figure 6-11. Write Cycle Timing Chart 5 (/LB, /UB Independent Controlled)
t
WC
t
AS
t
WC
t
AS
A1
A2
A3
t
WR
t
WR
t
DW
t
DH
t
DW
t
DH
t
BW
t
BW
t
ASO
/OE (Input)
t
OHAH
t
OES
t
OEH
t
BP
/CS (Input)
Address (Input)
Data In D2
I/O0 to I/O7 (Input)
High-Z
High-Z
High-Z
High-Z
/WE (Input)
Data In
D1
/LB (Input)
/UB (Input)
I/O8 to I/O15 (Input)
L
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15874EJ5V0DS
27
PD4632312A-X
Figure 6-12. Mode Register Setting Timing Chart
/LB, /UB (Input)
/WE (Input)
/CS (Input)
Address (Input)
/OE (Input)
I/O (Input)
t
RC
t
RC
t
WC
t
WC
1FFFFFH
t
WP
t
WR
t
WP
t
WR
t
DW
t
DH
t
DW
t
DH
1FFFFFH
1FFFFFH
1FFFFFH
xxxxH
xxxxH
Mode Register Setting
High-Z
High-Z
High-Z
Figure 6-13. Mode Register Setting Flow Chart
Start
End
Address= 1FFFFFH
Read with toggled the /CS, /OE
Address = 1FFFFFH
Write
Data = 00H?
No
Mode register setting exit
Fail
Address = 1FFFFFH
Write
Data = xxH?
No
Note
Note xxH = 04H, 05H, 06H, 07H
No
No
No
No
Address= 1FFFFFH
Read with toggled the /CS, /OE
Preliminary Data Sheet M15874EJ5V0DS
28
PD4632312A-X
Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart
/CS (Input)
t
CHML
t
MHCL1
MODE (Input)
Standby
mode 1
Standby mode 2
(Data hold: 16M bits / 8M bits / 4M bits)
Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart
/CS (Input)
t
CHML
t
MHCL2
MODE (Input)
Standby
mode 1
Standby mode 2
(Data not held)
Standby Mode 2 Entry / Exit Timing
Parameter
Symbol
MIN.
MAX.
Unit
Note
Standby mode 2 entry
t
CHML
0
ns
/CS high level to MODE low level
Standby mode 2 exit to normal operation
t
MHCL1
30
ns
1
MODE high level to /CS low level
Standby mode 2 exit to normal operation
t
MHCL2
200
s
2
MODE high level to /CS low level
Notes 1. This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 16M bits / 8M bits / 4M
bits).
2. This is the time it takes to return to normal operation from Standby Mode 2 (data not held).
Preliminary Data Sheet M15874EJ5V0DS
29
PD4632312A-X
7. Package Drawing
S
w
B
S
w
A
6
5
4
3
2
1
A
B
A
B
C
D
E
F
G
H
S
y
S
y1
M
S
b
x
A B
S
48-PIN TAPE FBGA (8x6)
ITEM
MILLIMETERS
D
E
8.0
0.1
6.0
0.1
w
A
0.2
0.94
0.10
b
x
0.08
y
0.1
e
0.75
A1
0.24
0.05
A2
0.70
0.40
0.05
INDEX MARK
INDEX MARK
A
A2
A1
ZE
ZD
y1
0.2
ZD
1.125
ZE
1.375
P48F9-75-BC2
e
E
D
Preliminary Data Sheet M15874EJ5V0DS
30
PD4632312A-X
8. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD4632312A-X.
Type of Surface Mount Device
PD4632312AF9-BC2: 48-pin TAPE FBGA (8 x 6)
Preliminary Data Sheet M15874EJ5V0DS
31
PD4632312A-X
9. Revision History
Edition/
Page
Type of
Location
Description
Date
This
Previous
revision
(Previous edition
This edition)
edition
edition
5th edition/ pp.1, 2
pp.1, 2
Addition
Features, Ordering Information -B60X: The note under development was added.
Jan. 2003
pp.1, 15
pp.1, 15
Modification Features, DC Characteristics
Operating supply current (MAX.):
-B65X: 45 mA
50 mA
-BE75X, -BE85X: 40 mA
45 mA
Standby supply current (MAX.):
Density of data hold 32M bits: 70
A 100 A
16M bits: 50
A 70 A
8M bits: 45
A 60 A
4M bits: 42
A 50 A
0M bit : 10
A 30 A
p.17
p.17
Modification Read Cycle
t
OLCH
(MIN.):
-BE75X: 45 ns
50 ns
-BE85X: 45 ns
55 ns
Preliminary Data Sheet M15874EJ5V0DS
32
PD4632312A-X
[MEMO]
Preliminary Data Sheet M15874EJ5V0DS
33
PD4632312A-X
[MEMO]
Preliminary Data Sheet M15874EJ5V0DS
34
PD4632312A-X
[MEMO]
Preliminary Data Sheet M15874EJ5V0DS
35
PD4632312A-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD4632312A-X
The information in this document is current as of January, 2003. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
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property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
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