Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- PIN CONFIGURATION (Top Vew)
- INTERNAL BLOCK DIAGRAM
- 1. PIN FUNCTIONS
- 1.1 Port Pins
- 1.2 Non-port Pins
- 2. INSTRUCTION SETS
- 2.1 Instructions Added to uPD70108/70116
- 2.2 Instruction Set Operation
- 2.3 Instruction Set Table
- 3. ELECTRICAL SPECIFICATIONS
- 4. CHARACTERISTIC CURVES
- 5. PACKAGE DRAWINGS
- 6. RECOMMENDED SOLDERING CONDITIONS
1996
DATA SHEET
The
PD70320 (V25) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA
controller, interrupt controller, etc. are all integrated. The
PD70320 is compatible with the 8/16-bit microprocessor
PD70108/ 70116 (V20
TM
/V30
TM
) on the software level.
The details of the functions are described in the following User's Manuals. Be sure to read it before starting
design.
V25, V35
TM
User's Manual -- Hardware
: IEM-1220
V25, V35 Family User's Manual -- Instructions : U12120J (Japanese version)
FEATURES
Internal 16-bit architecture and external 8-bit data bus
Compatible with
PD70108/ 70116 (in native mode) on software level (some instructions added)
Minimum instruction cycle : 400 ns/5 MHz (
PD70320)
250 ns/8 MHz (
PD70320-8)
On-chip RAM : 256 words
8 bits
Input port (port T) with comparator : 8 bits
I/O lines (input port : 4 bits, input/output port : 20 bits)
Serial interface (internal dedicated baud rate generator) : 2 channels
Asynchronous mode and I/O interface mode
Interrupt controller
Programmable priority (8 levels)
Vectored interrupt function
Register bank switching function
Macro service function
DRAM and pseudo SRAM refreshing functions
DMA controller : 2 channels
16-bit timer : 2 channels
Time base counter
On-chip clock generator
Programmable wait function
Standby function (STOP/HALT)
MOS INTEGRATED CIRCUIT
V25
TM
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The information in this document is subject to change without notice.
The mark shows major revised points.
PD70320
1995
Document No. U10090EJ8V0DS00 (8th edition)
Date Published November 1997 N
Printed in Japan
2
PD70320
ORDERING INFORMATION
Part Number
Package
Max. Operating Frequency (MHz)
PD70320L
84-pin plastic QFJ (1150
1150 mils)
5
PD70320L-8
84-pin plastic QFJ (1150
1150 mils)
8
PD70320GJ-5BG
94-pin plastic QFP (20
20 mm)
5
PD70320GJ-8-5BG
94-pin plastic QFP (20
20 mm)
8
Remark
The plastic QFJ is a new name of the PLCC.
3
PD70320
PIN CONFIGURATION (Top View)
84-Pin Plastic QFJ (1150
1150 mils)
PD70320L
PD70320L-8
Cautions 1. Connect IC pin individually to V
DD
via a resistor (3 to 10 k
).
2
Connect EA pin to GND via a resistor (3 to 10 k
).
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P07/CLKOUT
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
A12
A13
A14
A15
A16
A17
A18
A19
RxD0
GND
CTS0
TxD0
RxD1
CTS1
TxD1
P20/DMARQ0
IC
V
DD
P21/DMAAK0
P22/
TC0
IC
PT7
PT6
PT5
PT4
PT3
PT2
PT1
PT0
P17/READY
P16/SCK0
P15/TOUT
P14/INT/POLL
P13/INTP2/INTAK
P12/INTP1
P11/INTP0
P10/NMI
P27/HLDRQ
P26/HLDAK
P25/TC1
P24/DMAAK1
P23/DMARQ1
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
P06
P05
IC
P04
P03
P02
P01
P00
EA
MREQ
IOSTB
MSTB
R/W
REFRQ
RESET
V
DD
X2
X1
GND
V
TH
IC
IC: Internally Connected
4
PD70320
94-Pin Plastic QFP (20
20 mm)
PD70320GJ-5BG
PD70320GJ-8-5BG
Cautions 1. Connect IC pin individually to V
DD
via a resistor (3 to 10 k
).
2. Connect EA pin to GND via a resistor (3 to 10 k
).
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75
A11
NC
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
P07/CLKOUT
P06
NC: Non-Connection
74 73 72
32
31
30
29
28
27
26
25
24
IC
P23/DMARQ1
P24/DMAAK1
P25/
TC1
P26/HLDAK
P27/HLDRQ
P10/NMI
P11/INTP0
P12/INTP1
P13/INTP2/INTAK
P14/INT/POLL
P15/
TOUT
P16/SCK0
P17/READY
PT0
PT1
PT2
PT3
PT4
PT5
NC
PT6
PT7
IC
A12
NC
A13
A14
A15
A16
A17
A18
A19
RxD0
GND
CTS0
TxD0
RxD1
CTS1
TxD1
P20/DMARQ0
IC
V
DD
V
DD
P21/DMAAK0
NC
P22/TC0
P05
NC
IC
P04
P03
P02
P01
P00
EA
MREQ
IOSTB
MSTB
R/W
REFRQ
RESET
V
DD
V
DD
X2
X1
GND
GND
NC
NC
V
TH
IC: Internally Connected
5
PD70320
INTERNAL BLOCK DIAGRAM
Note Not user-accessible.
P20/DMARQ0
P21/DMAAK0
P22/TC0
P23/DMARQ1
P24/DMAAK1
P25/TC1
TxD0
RxD0
P16/SCK0
CTS0
TxD1
RxD1
CTS1
P10/NMI
P11/INTP0
P12/INTP1
P13/INTP2/INTAK
P14/INT/POLL
A0 to A19
RESET
HLDAK/P26
HLDRQ/P27
READY/P17
MREQ
MSTB
R/W
IOSTB
POLL/INT/P14
EA
D0 to D7
X1
X2
V
DD
GND
BUS CONTROL LOGIC
STAGING LATCH
STAGING LATCH
PROGRAMMABLE
DMA
CONTROLLER
SERIAL
INTERFACE
BAUD RATE
GENERATOR
PROGRAMMABLE
INTERRUPT
CONTROLLER
INSTRUCTION DECODER
MICRO SEQUENSER
MICRO ROM
ALU
LC
etc.
PSW
PC
TA
TB
TC
INTERNAL RAM
256 byte
GR
MACRO SERVICE
CHANNEL
QUEUE
(6 byte)
16-BIT TIMER
TIME BASE
COUNTER
PORT
PORT with
COMPARATOR
CG
TOUT/P15
CLKOUT/PO7
P0
P1
P2
PT0 to 7
V
TH
REFRQ
ADM
INTERNAL ROM
Note
8 Kbyte
(reserved)
PFP
INC
6
PD70320
CONTENTS
1.
PIN FUNCTIONS .................................................................................................................................. 7
1.1
Port Pins ....................................................................................................................................................... 7
1.2
Non-port Pins ............................................................................................................................................... 8
2.
INSTRUCTION SETS ........................................................................................................................... 9
2.1
Instructions Added to
PD70108/70116 .................................................................................................... 9
2.2
Instruction Set Operation ......................................................................................................................... 11
2.3
Instruction Set Table ................................................................................................................................. 15
3.
ELECTRICAL SPECIFICATIONS ...................................................................................................... 47
4.
CHARACTERISTIC CURVES ............................................................................................................ 66
5.
PACKAGE DRAWINGS ..................................................................................................................... 69
6.
RECOMMENDED SOLDERING CONDITIONS ................................................................................ 71
7
PD70320
1. PIN FUNCTIONS
1.1 Port Pins
Pin Name
Input/Output
Port Function
Control Function
P00 to P06
Input & output
8-bit input/output ports, each to
--
P07/CLKOUT
Input & output/output
be specified bit-by-bit
System clock output
P10/NMI
Input
Used as non-maskable interrupt
--
request input (input port)
P11/INTP0
Used as both external interrupt
P12/INTP1
request input and input port
P13/INTP2/INTAK
Input/input/output
INT acknowledge signal output
P14/POLL/INT
Input & output/input/input
Used as both specifiable input/
External interrupt request input
output port and POLL input
P15/ TOUT
Input & output/output
Input/output port specifiable
Timer output
P16/SCK0
bit-by-bit
Serial clock output
P17/READY
Input & output/input
READY input
P20/DMARQ0
Input & output/input
8-bit input/output port specifiable DMA request input (CH0)
P21/DMAAK0
Input & output/output
bit-by-bit
DMA acknowledge output (CH0)
P22/TC0
DMA end output (CH0)
P23/DMARQ1
Input & output/input
DMA request input (CH1)
P24/DMAAK1
Input & output/output
DMA acknowledge output (CH1)
P25/TC1
DMA end output (CH1)
P26/HLDAK
Input & output/output
HOLD acknowledge output
P27/HLDRQ
Input & output/input
HOLD input
PT0 to PT7
Input
8-bit input port with comparator
--
Remark
All port pins become input ports after reset is released.
When using P13/INTP2/INTAK as a INTAK pin, be sure to pull up the pin to avoid a malfunction of external
interrupt controller after reset is released.
8
PD70320
1.2 Non-port Pins
Pin Name
Input/Output
Function
TxD0
Output
Serial data output
TxD1
RxD0
Input
Serial data input
RxD1
CTS0
Input & output
CTS input in asynchronous mode, receive clock input/output in I/O interface mode
CTS1
Input
CTS input
REFRQ
Output
DRAM refresh pulse output
V
TH
Input
Comparator reference voltage input
RESET
Reset signal input
EA
External memory access (connect to GND via a resistor (3 to 10 k
))
X1
Input
Used to connect crystal resonator/ceramic resonator for oscillating system clock.
X2
External clock is entered by entering reverse phase clock to both X1 and X2 pins.
D0 to D7
Input & output
8-bit data bus
A0 to A19
Output
20-bit address output
MREQ
Output used to indicate that memory bus cycle has been started
MSTB
Memory read/memory write strobe output
R/ W
Read cycle/write cycle ID signal output
IOSTB
I/O read /I/O write strobe output
V
DD
Positive power supply pins (all pins should be connected)
GND
GND pins (all pins should be connected)
IC
Internally connected (connect individually to V
DD
via a resistor (3 to 10 k
))
9
PD70320
2. INSTRUCTION SETS
The
PD70320 instruction sets are upward-compatible with those of
PD70108/ 70116 in native mode.
2.1 Instructions Added to
PD70108/70116
The following instructions are newly added to the
PD70108/ 70116.
(1) Conditional branch instruction
BTCLR Bit test instruction used for special function registers
If, when this BTCLR is executed, the target special function register bit status is "1", the bit is
reset (0) and the program is branched to short-label described in the operand. If the target bit
status is "0", the program is moved to the next instruction. PSW is not changed in this instruction.
(Descriptive format)
Operand
Mnemonic
Special Function
Special Function
Register Address
Register Bit
Branch Address
BTCLR
sfr
imm3
short-label
(2) Interrupt instructions
RETRBI Return instruction used for register banks
This instruction is used to return the program from the interrupt service routine in which the
register bank switching function is used. It cannot be used for returning from vectored interrupt
servicing.
(Descriptive format)
Mnemonic
Operand
RETRBI
None
FINT This instruction is used to report the interrupt controller that interrupt servicing has ended.
If an interrupt other than NMI, INT, and software interrupt is used, this instruction must be
executed prior to the instruction for returning from interrupt servicing. It should not be used for
NMI, INT and software interrupts.
(Descriptive format)
(3) CPU instruction
STOP Instruction for transition to STOP state
(Descriptive format)
Mnemonic
Operand
FINT
None
Mnemonic
Operand
STOP
None
10
PD70320
(4) Register bank switch instructions
BRKCS Used to switch register banks
A register bank is switched to the register bank indicated by the lower 3 bits in the 16-bit register
described in the operand. The program is also branched with this instruction to the address
obtained from the PS stored in advance in the new register bank and the vector PC.
The RETRBI instruction is used to return the program from the new register bank.
(Descriptive format)
TSKSW Used to switch register banks
Just like the BRKCS instruction, this instruction is also executed to select a register bank. The
program is branched to the address obtained from the PS stored in advance in the new register
bank and the address obtained from the PC save area.
(Descriptive format)
(5) Data transfer instructions
MOVSPA Used to transfer SS and SP values
This instruction is executed to transfer both SS and SP values before the register bank is switched
to SS and SP of the current (post-switching) register bank.
(Descriptive format)
MOVSPB Used to transfer SS and SP values
This instruction is executed to transfer the SS and SP values of the current (pre-switching)
register bank to the SS and SP of the new register bank indicated by the lower 3 bits in the 16-
bit register described in the operand.
(Descriptive format)
Some
PD70108/ 70116 instructions should be much cared as shown below when used for the
PD70320.
I/O instruction, primitive I/O instruction
If PSW IBRK flag is reset (0), an interrupt is generated without executing this instruction. Be sure to set (1)
the IBRK flag when using the I/O instruction.
FPO instruction
An interrupt is generated without executing this instruction.
Mnemonic
Operand
BRKCS
reg16
Mnemonic
Operand
TSKSW
reg16
Mnemonic
Operand
MOVSPA
None
Mnemonic
Operand
MOVSPB
reg16
11
PD70320
2.2 Instruction Set Operation
Table 2-1. Operand Identifier
Identifier
Description
reg
8-/16-bit general register
reg8
8-bit general register
reg16
16-bit general register
dmem
8-/16-bit memory location
mem
8-/16-bit memory location
mem8
8-bit memory location
mem16
16-bit memory location
mem32
32-bit memory location
sfr
8-bit special function register location
imm
Constant within 0 to FFFFH
imm3
Constant within 0 to 7
imm4
Constant within 0 to FH
imm8
Constant within 0 to FFH
imm16
Constant within 0 to FFFFH
acc
Register AW or AL
sreg
Segment register
src-table
256-byte conversion table name
src-block
Register IX-addressed block name
dst-block
Register IY-addressed block name
near-proc
Procedure in the current program segment
far-proc
Procedure in another program segment
near-label
Label in the current program segment
short-label
Label within end of instruction to 128 to +127 bytes
far-label
Label in another program segment
memptr16
Word including location offset in the current program segment to which control is to be passed
memptr32
Double-word including location offset in another program segment to which control is to be passed
and segment base address
regptr16
16-bit general register including location offset in another program segment to which control is to be
passed
pop-value
Number of bytes to be abandoned from stack (0 to 64K, normally even number)
fp-op
Immediate value to judge instruction code of external floating point operation chip
R
Register set
12
PD70320
Identifier
Description
W
Byte/word specification bit (0: byte, 1: word). However, when s = 1, the sign extended byte data
should be 16-bit operand even when W is 1.
reg
Register field (000 to 111)
mem
Memory field (000 to 111)
mod
Mode field (00 to 10)
s
Sign extension specification bit (0: Sign is not extended, 1: Sign is extended)
X, XXX, YYY, ZZZ
Data used to judge instruction code of external floating-point operation chip
Table 2-2. Operation Code Identifier
Table 2-3. Operation Identifier (1/2)
Identifier
Description
AW
Accumulator (16 bits)
AH
Accumulator (upper byte)
AL
Accumulator (lower byte)
BW
Register BW (16 bits)
CW
Register CW (16 bits)
CL
Register CW (lower byte)
DW
Register DW (16 bits)
SP
Stack pointer (16 bits)
PC
Program counter (16 bits)
PSW
Program status word (16 bits)
IX
Index register (source) (16 bits)
IY
Index register (destination) (16 bits)
PS
Program segment register (16 bits)
DS1
Data segment 1 register (16 bits)
DS0
Data segment 0 register (16 bits)
SS
Stack segment register (16 bits)
AC
Auxiliary carry flag
CY
Carry flag
P
Parity flag
S
Sign flag
Z
Zero flag
DIR
Direction flag
IE
Interrupt enable flag
V
Overflow flag
BRK
Break flag
MD
Mode flag
()
Contents in memory shown in ( )
disp
Displacement (8/16 bits)
ext-disp8
16 bits obtained by extending sign of 8-bit displacement
13
PD70320
Table 2-3. Operation Identifier (2/2)
Identifier
Description
temp
Temporary register (8/16/32 bits)
tmpcy
Temporary carry flag (1 bit)
seg
Immediate segment data (16 bits)
offset
Immediate offset data (16 bits)
Transfer direction
+
Addition
Subtraction
Multiplication
Division
%
Modulo
AND
OR
Exclusive OR
H
2-digit hexadecimal number
H
4-digit hexadecimal number
Identifier
Description
(Blank)
No change
0
Cleared to 0
1
Set to 1
Set or cleared according to the result
U
Not defined
R
The previously saved value is restored.
Table 2-5. 8/16-Bit General Register Selection
reg
W = 0
W = 1
000
AL
AW
001
CL
CW
010
DL
DW
011
BL
BW
100
AH
SP
101
CH
BP
110
DH
IX
111
BH
IY
Table 2-4. Flag Operation Identifier
14
PD70320
Table 2-6. Segment Register Selection
sreg
00
DS1
01
PS
10
SS
11
DS0
The number of clocks, for memory operand, differs among addressing modes. So, use the following values for
"EA" items shown in Table 2-8 Number of Clocks.
Table 2-7. Number of Clocks for Each Memory Addressing
mod
mem
00
Clocks
01
Clocks
10
Clocks
000
BW + IX
3
BW + IX + disp8
3
BW + IX + disp16
4
001
BW + IY
3
BW + IY + disp8
3
BW + IY + disp16
4
010
BP + IX
3
BP + IX + disp8
3
BP + IX + disp16
4
011
BP + IY
3
BP + IY + disp8
3
BP + IY + disp16
4
100
IX
3
IX + disp8
3
IX + disp16
4
101
IY
3
IY + disp8
3
IY + disp16
4
110
Direct address
3
BP + disp8
3
BP + disp16
4
111
BW
3
BW + disp8
3
BW + disp16
4
"T" indicates the number of wait states. Use any number of waits starting at "0" (no wait).
The instruction fetch cycle is not counted as the number of clocks.
There are some branch instructions for which such description as the example below is provided.
The description indicates as follows:
Example 15/8 15: the number of clock cycles when branched
8: the number of clock cycles when not branched
15
PD70320
2.3
Instruction Set Table
Data
transfer
MOV
LDEA
TRANS
XCH
MOVSPA
Note
MOVSPB
Note
reg,reg
mem,reg
reg,mem
mem,imm
reg,imm
acc,dmem
dmem,acc
sreg,reg16
sreg,mem16
reg16,sreg
mem16,sreg
DS0,reg16,
mem32
DS1,reg16,
mem32
AH,PSW
PSW,AH
reg16,mem16
src-table
reg,reg
mem,reg
reg,mem
AW,reg16
reg16,AW
reg16
Operation Code
1 0 0 0 1 0 1 W
1 0 0 0 1 0 0 W
1 0 0 0 1 0 1 W
1 1 0 0 0 1 1 W
1 0 1 1 W reg
1 0 1 0 0 0 0 W
1 0 1 0 0 0 1 W
1 0 0 0 1 1 1 0
1 0 0 0 1 1 1 0
1 0 0 0 1 1 0 0
1 0 0 0 1 1 0 0
1 1 0 0 0 1 0 1
1 1 0 0 0 1 0 0
1 0 0 1 1 1 1 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 0 1
1 1 0 1 0 1 1 1
1 0 0 0 0 1 1 W
1 0 0 0 0 1 1 W
1 0 0 1 0 reg
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
1 1 1 1 1 reg
7 6 5 4 3 2 1 0
1 1 reg reg
mod reg mem
mod reg mem
mod 0 0 0 mem
1 1 0 sreg reg
mod 0 sreg mem
1 1 0 sreg reg
mod 0 sreg mem
mod reg mem
mod reg mem
mod reg mem
1 1 reg reg
mod reg mem
0 0 1 0 0 1 0 1
1 0 0 1 0 1 0 1
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2 to 4
3 to 6
2 to 3
3
3
2
2 to 4
2
2 to 4
2 to 4
2 to 4
1
1
2 to 4
1
2
2 to 4
1
2
3
Bytes
Flags
AC CY V
P
S
Z
reg
reg
(mem)
reg
reg
(mem)
(mem)
imm
reg
imm
When W = 0, AL
(dmem)
When W = 1, AH
(dmem + 1), AL
(dmem)
When W = 0, (dmem)
AL
When W = 1, (dmem + 1)
AH, (dmem)
AL
sreg
reg16
sreg
(mem16)
reg16
sreg
(mem16)
sreg
reg16
(mem32)
DS0
(mem32 + 2)
reg16
(mem32)
DS1
(mem32 + 2)
AH
S, Z, F1, AC, F0, P, IBRK, CY
S, Z, F1, AC, F0, P, IBRK, CY
AH
reg16
mem16
AL
(BW + AL)
reg
reg
(mem)
reg
AW
reg16
New register bank SS and SP
old register bank SS and SP
SS and SP of reg16-indicated new register bank
old register bank
SS and SP
Operation
sreg : SS, DS0, DS1
sreg : SS, DS0, DS1
Note These instructions are newly added to the PD70108/70116.
16
PD70320
REPC
REPNC
REP
REPE
REPZ
REPNE
REPNZ
MOVBK
CMPBK
CMPM
LDM
STM
dst-block,
src-block
src-block,
dst-block
dst-block
src-block
dst-block
Operation Code
0 1 1 0 0 1 0 1
0 1 1 0 0 1 0 0
1 1 1 1 0 0 1 1
1 1 1 1 0 0 1 0
1 0 1 0 0 1 0 W
1 0 1 0 0 1 1 W
1 0 1 0 1 1 1 W
1 0 1 0 1 1 0 W
1 0 1 0 1 0 1 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
1
1
1
1
1
1
1
1
1
Bytes
Flags
AC CY V
P
S
Z
Executes the primitive block transfer instruction in the continued
byte while CW
0, and decrements CW by one. If any interruption
is held at this time, it is processed. The program exits the loop
when CY
1.
Same as above.
The program exits the loop when CY
0.
Executes the primitive block transfer instruction in the continued
byte while CW
0, and decrements CW by one. If any interruption
is held at this time, it is processed. The program exits the loop
when the primitive block transfer instruction is CMPBK or CMPM,
and when Z
1.
Same as above.
The program exits the loop when Z
0.
When W = 0, (IY)
(IX)
DIR = 0: IX
IX + 1, IY
IY + 1
DIR = 1: IX
IX 1, IY
IY 1
When W = 1, (IY + 1, IY)
(IX + 1, IX)
DIR = 0: IX
IX + 2, IY
IY + 2
DIR = 1: IX
IX 2, IY
IY 2
When W = 0, (IX) (IY)
DIR = 0: IX
IX + 1, IY
IY + 1
DIR = 1: IX
IX 1, IY
IY 1
When W = 1, (IX + 1, IX) (IY + 1, IY)
DIR = 0: IX
IX + 2, IY
IY + 2
DIR = 1: IX
IX 2, IY
IY 2
When W = 0, AL (IY)
DIR = 0: IY
IY + 1; DIR = 1: IY
IY 1
When W = 1, AW (IY + 1, IY)
DIR = 0: IY
IY + 2; DIR = 1: IY
IY 2
When W = 0, AL
(IX)
DIR = 0: IX
IX + 1; DIR = 1: IX
IX 1
When W = 1, AW
(IX + 1, IX)
DIR = 0: IX + 2; DIR = 1: IX
IX 2
When W = 0, (IY)
AL
DIR = 0: IY
IY + 1; DIR = 1: IY
IY 1
When W = 1, (IY + 1, IY)
AW
DIR = 0: IY
IY + 2; DIR = 1: IY
IY 2
Operation
Repeat
prefix
Primitive
block
transfer
17
PD70320
INS
EXT
IN
OUT
INM
OUTM
reg8,reg8
reg8,imm4
reg8,reg8
reg8,imm4
acc,imm8
acc,DW
imm8,acc
DW,acc
dst-block,DW
DW,src-block
Operation Code
0 0 0 0 1 1 1 1
1 1 reg reg
0 0 0 0 1 1 1 1
1 1 0 0 0 reg
0 0 0 0 1 1 1 1
1 1 reg reg
0 0 0 0 1 1 1 1
1 1 0 0 0 reg
1 1 1 0 0 1 0 W
1 1 1 0 1 1 0 W
1 1 1 0 0 1 1 W
1 1 1 0 1 1 1 W
0 1 1 0 1 1 0 W
0 1 1 0 1 1 1 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
3
4
3
4
2
1
2
1
1
1
Bytes
Flags
AC CY V
P
S
Z
16-bit field
AW
16-bit field
AW
AW
16-bit field
AW
16-bit field
When W = 0, AL
(imm8)
When W = 1, AH
(imm8 + 1), AL
(imm8)
When W = 0, AL
(DW)
When W = 1, AH
(DW + 1), AL
(DW)
When W = 0, (imm8)
AL
When W = 1, (imm8 + 1)
AH, (imm8)
AL
When W = 0, (DW)
AL
When W = 1, (DW + 1)
AH, (DW)
AL
When W = 0, (IY)
(DW)
DIR = 0: IY
IY + 1; DIR = 1: IY
IY 1
When W = 1, (IY + 1, IY)
(DW + 1, DW)
DIR = 0: IY
IY + 2; DIR = 1: IY
IY 2
When W = 0, (DW)
(IX)
DIR = 0: IX
IX + 1; DIR = 1: IX
IX 1
When W = 1, (DW + 1, DW)
(IX + 1, IX)
DIR = 0: IX
IX + 2; DIR = 1: IX
IX 2
Operation
Bit field
opera-
tion
I/O
0 0 1 1 0 0 0 1
0 0 1 1 1 0 0 1
0 0 1 1 0 0 1 1
0 0 1 1 1 0 1 1
Note
Note
Note
Note
Primitive
I/O
Note When IBRK = 0, a software interrupt is generated automatically and the instruction is not executed.
18
PD70320
ADD
ADDC
SUB
SUBC
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
Operation Code
0 0 0 0 0 0 1 W
0 0 0 0 0 0 0 W
0 0 0 0 0 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 0 0 0 1 0 W
0 0 0 1 0 0 1 W
0 0 0 1 0 0 0 W
0 0 0 1 0 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 0 1 0 1 0 W
0 0 1 0 1 0 1 W
0 0 1 0 1 0 0 W
0 0 1 0 1 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 1 0 1 1 0 W
0 0 0 1 1 0 1 W
0 0 0 1 1 0 0 W
0 0 0 1 1 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 0 1 1 1 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2 to 4
3 to 4
3 to 6
2 to 3
2
2 to 4
2 to 4
3 to 4
3 to 6
2 to 3
2
2 to 4
2 to 4
3 to 4
3 to 6
2 to 3
2
2 to 4
2 to 4
3 to 4
3 to 6
2 to 3
Bytes
Flags
AC CY V
P
S
Z
reg
reg + reg
(mem)
(mem) + reg
reg
reg + (mem)
reg
reg + imm
(mem)
(mem) + imm
When W = 0, AL
AL + imm
When W = 1, AW
AW + imm
reg
reg + reg + CY
(mem)
(mem) + reg + CY
reg
reg + (mem) + CY
reg
reg + imm + CY
(mem)
(mem) + imm + CY
When W = 0, AL
AL + imm + CY
When W = 1, AW
AW + imm + CY
reg
reg reg
(mem)
(mem) reg
reg
reg (mem)
reg
reg imm
(mem)
(mem) imm
When W = 0, AL
AL imm
When W = 1, AW
AW imm
reg
reg reg CY
(mem)
(mem) reg CY
reg
reg (mem) CY
reg
reg imm CY
(mem)
(mem) imm CY
When W = 0, AL
AL imm CY
When W = 1, AW
AW imm CY
Operation
Addi-
tion/
subtrac-
tion
1 1 reg reg
mod reg mem
mod reg mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 reg reg
mod reg mem
mod reg mem
1 1 0 1 0 reg
mod 0 1 0 mem
1 1 reg reg
mod reg mem
mod reg mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 reg reg
mod reg mem
mod reg mem
1 1 0 1 1 reg
mod 0 1 1 mem
19
PD70320
ADD4S
SUB4S
CMP4S
ROL4
ROR4
INC
DEC
reg8
mem8
reg8
mem8
reg8
mem
reg16
reg8
mem
reg16
Operation Code
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
1 1 0 0 0 reg
0 0 0 0 1 1 1 1
mod 0 0 0 mem
0 0 0 0 1 1 1 1
1 1 0 0 0 reg
0 0 0 0 1 1 1 1
mod 0 0 0 mem
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 W
0 1 0 0 0 reg
1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 W
0 1 0 0 1 reg
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2
2
3
3 to 5
3
3 to 5
2
2 to 4
1
2
2 to 4
1
Bytes
Flags
AC CY V
P
S
Z
dst BCD string
dst BCD string + src BCD string
dst BCD string
dst BCD string src BCD string
dst BCD string src BCD string
reg8
reg8 + 1
(mem)
(mem) + 1
reg16
reg16 + 1
reg8
reg8 1
(mem)
(mem) 1
reg16
reg16 1
Operation
BCD
opera-
tion
0 0 1 0 0 0 0 0
0 0 1 0 0 0 1 0
0 0 1 0 0 1 1 0
0 0 1 0 1 0 0 0
0 0 1 0 1 0 0 0
0 0 1 0 1 0 1 0
0 0 1 0 1 0 1 0
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 1 reg
mod 0 0 1 mem
U
U
U
U
U
U
U
U
U
U
U
U
Note
Note
Note
Incre-
ment/
decre-
ment
AL
L
Upper
Byte
Lower
Byte
reg
AL
L
Upper
Byte
Lower
Byte
mem
AL
L
Upper
Byte
Lower
Byte
reg
AL
L
Upper
Byte
Lower
Byte
mem
n: 1/2 of the number of BCD digits
Note The number of BCD digits is given in the CL register. The value can be set within 1 to 254.
20
PD70320
MULU
MUL
reg8
mem8
reg16
mem16
reg8
mem8
reg16
mem16
reg16,
(reg16,)
Note
imm8
reg16,
mem16,
imm8
reg16,
(reg16,)
Note
imm16
reg16,
mem16,
imm16
Operation Code
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
0 1 1 0 1 0 1 1
0 1 1 0 1 0 1 1
0 1 1 0 1 0 0 1
0 1 1 0 1 0 0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
2
2 to 4
2
2 to 4
3
3 to 5
4
4 to 6
Bytes
Flags
AC CY V
P
S
Z
AW
AL
reg8
AH = 0: CY
0, V
0
AH
0: CY
1, V
1
AW
AL
(mem8)
AH = 0: CY
0, V
0
AH
0: CY
1, V
1
DW, AW
AW
reg16
DW = 0: CY
0, V
0
DW = 1: CY
1, V
1
DW, AW
AW
(mem16)
DW = 0: CY
0, V
0
DW = 1: CY
1, V
1
AW
AL
reg8
Extension of AH = AL sign: CY
0, V
0
Extension of AH
AL sign: CY
1, V
1
AW
AL
(mem8)
Extension of AH = AL sign: CY
0, V
0
Extension of AH
AL sign: CY
1, V
1
DW, AW
AW
reg16
Extension of DW = AW sign: CY
0, V
0
Extension of DW
AW sign: CY
1, V
1
DW, AW
AW
(mem16)
Extension of DW = AW sign: CY
0, V
0
Extension of DW
AW sign: CY
1, V
1
reg16
reg16
imm8
Product
16 bits: CY
0, V
0
Product > 16 bits: CY
1, V
1
reg16
(mem16)
imm8
Product
16 bits: CY
0, V
0
Product > 16 bits: CY
1, V
1
reg16
reg16
imm16
Product
16 bits: CY
0, V
0
Product > 16 bits: CY
1, V
1
reg16
(mem16)
imm16
Product
16 bits: CY
0, V
0
Product > 16 bits: CY
1, V
1
Operation
Multipli-
cation
1 1 1 0 0 reg
mod 1 0 0 mem
1 1 1 0 0 reg
mod 1 0 0 mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 reg reg
mod reg mem
1 1 reg reg
mod reg mem
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Note The 2nd operand is omissible. If omitted, the 1st operand is assumed.
21
PD70320
DIVU
reg8
mem8
reg16
mem16
Operation Code
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
Bytes
Flags
AC CY V
P
S
Z
temp
AW
When temp
reg8
FFH
AH
temp%reg8, AL
temp
reg8
When temp
reg8 > FFH
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0, PS
(3, 2), PC
(1, 0)
temp
AW
When temp
(mem8)
FFH
AH
temp%(mem8), AL
temp
(mem8)
When temp
(mem8) > FFH
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0, PS
(3, 2), PC
(1, 0)
temp
DW, AW
When temp
reg16
FFFFH
DW
temp%reg16, AW
temp
reg16
When temp
reg16 > FFFFH
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0, PS
(3, 2), PC
(1, 0)
temp
DW, AW
When temp
(mem16)
FFFFH
DW
temp%(mem16), AW
temp
(mem16)
When temp
(mem16) > FFFFH
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0, PS
(3, 2), PC
(1, 0)
Operation
Unsign-
ed
division
1 1 1 1 0 reg
mod 1 1 0 mem
1 1 1 1 0 reg
mod 1 1 0 mem
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
22
PD70320
DIV
reg8
mem8
reg16
mem16
Operation Code
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 0 1 1 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
Bytes
Flags
AC CY V
P
S
Z
Operation
Signed
division
1 1 1 1 1 reg
mod 1 1 1 mem
1 1 1 1 1 reg
mod 1 1 1 mem
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
temp
AW
When temp
reg8 > 0 and temp
reg8
7FH or
temp
reg8 < 0 and temp
reg8 > 0 7FH 1
AH
temp%reg8, AL
temp
reg8
When temp
reg8 > 0 and temp
reg8 > 7FH or
temp
reg8 > 0 and temp
reg8 < 0 7FH 1
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0, PS
(3, 2), PC
(1, 0)
temp
AW
When temp
(mem8) > 0 and temp
(mem8)
7FH or
temp
(mem8) < 0 and temp
(mem8) > 0 7FH 1
AH
temp%(mem8), AL
temp
(mem8)
When temp
(mem8) > 0 and temp
(mem8) > 7FH or
temp
(mem8) > 0 and temp
(mem8) < 0 7FH 1
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0, PS
(3, 2), PC
(1, 0)
temp
DW, AW
When temp
reg16 > 0 and temp
reg16
7FFFH or
temp
reg16 < 0 and temp
reg16 > 0 7FFFH 1
DW
temp%reg16, AW
temp
reg16
When temp
reg16 > 0 and temp
reg16 > 7FFFH or
temp
reg16 > 0 and temp
reg16 < 0 7FFFH 1
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0, PS
(3, 2), PC
(1, 0)
temp
DW, AW
When temp
(mem16) > 0 and temp
(mem16)
7FFFH or
temp
(mem16) < 0 and temp
(mem16) > 0 7FFFH 1
DW
temp%(mem16), AW
temp
(mem16)
When temp
(mem16) > 0 and temp
(mem16) > 7FFFH or
temp
(mem16) > 0 and temp
(mem16) < 0 7FFFH 1
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0, PS
(3, 2), PC
(1, 0)
23
PD70320
ADJBA
ADJ4A
ADJBS
ADJ4S
CVTBD
CVTDB
CVTBW
CVTWL
CMP
NOT
NEG
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
reg
mem
reg
mem
Operation Code
0 0 1 1 0 1 1 1
0 0 1 0 0 1 1 1
0 0 1 1 1 1 1 1
0 0 1 0 1 1 1 1
1 1 0 1 0 1 0 0
1 1 0 1 0 1 0 1
1 0 0 1 1 0 0 0
1 0 0 1 1 0 0 1
0 0 1 1 1 0 1 W
0 0 1 1 1 0 0 W
0 0 1 1 1 0 1 W
1 0 0 0 0 0 s W
1 0 0 0 0 0 s W
0 0 1 1 1 1 0 W
1 1 1 1 0 1 1 W
1 1 1 1 0 1 1 W
1 1 1 1 0 1 1 W
1 1 1 1 0 1 1 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
1
1
1
1
2
2
1
1
2
2 to 4
2 to 4
3 to 4
3 to 6
2 to 3
2
2 to 4
2
2 to 4
Bytes
Flags
AC CY V
P
S
Z
When AL
0FH > 9 or AC = 1, AL
AL + 6
AH
AH + 1, AC
1, CY
AC, AL
AL
0FH
When AL
0FH > 9 or AC = 1,
AL
AL + 6, AC
1
When AL > 9FH or CY = 1,
AL
AL + 60H, CY
1
When AL
0FH > 9 or AC = 1,
AL
AL 6, AH
AH 1, AC
1
CY
AC, AL
AL
0FH
When AL
0FH > 9 or AC = 1,
AL
AL 6, AC
1
When AL > 9FH or CY = 1,
AL
AL 60H, CY
1
AH
AL
0AH, AL
AL%0AH
AL
AH
0AH + AL, AH
0
When AL < 80H, AH
0. In other cases, AH
FFH.
When AW < 8000H, DW
0. In other cases, DW
FFFFH.
reg reg
(mem) reg
reg (mem)
reg imm
(mem) imm
When W = 0, AL imm
When W = 1, AW imm
reg
reg
(mem)
(mem)
reg
reg + 1
(mem)
(mem) + 1
Operation
BCD
adjust-
ment
0 0 0 0 1 0 1 0
0 0 0 0 1 0 1 0
1 1 reg reg
mod reg mem
mod reg mem
1 1 1 1 1 reg
mod 1 1 1 mem
1 1 0 1 0 reg
mod 0 1 0 mem
1 1 0 1 1 reg
mod 0 1 1 mem
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Data
conver-
sion
Compare
Comple-
ment
opera-
tion
24
PD70320
TEST
AND
OR
XOR
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
reg,reg
mem,reg
reg,mem
reg,imm
mem,imm
acc,imm
Operation Code
1 0 0 0 0 1 0 W
1 0 0 0 0 1 0 W
1 1 1 1 0 1 1 W
1 1 1 1 0 1 1 W
1 0 1 0 1 0 0 W
0 0 1 0 0 0 1 W
0 0 1 0 0 0 0 W
0 0 1 0 0 0 1 W
1 0 0 0 0 0 0 W
1 0 0 0 0 0 0 W
0 0 1 0 0 1 0 W
0 0 0 0 1 0 1 W
0 0 0 0 1 0 0 W
0 0 0 0 1 0 1 W
1 0 0 0 0 0 0 W
1 0 0 0 0 0 0 W
0 0 0 0 1 1 0 W
0 0 1 1 0 0 1 W
0 0 1 1 0 0 0 W
0 0 1 1 0 0 1 W
1 0 0 0 0 0 0 W
1 0 0 0 0 0 0 W
0 0 1 1 0 1 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
3 to 4
3 to 6
2 to 3
2
2 to 4
2 to 4
3 to 4
3 to 6
2 to 3
2
2 to 4
2 to 4
3 to 4
3 to 6
2 to 3
2
2 to 4
2 to 4
3 to 4
3 to 6
2 to 3
Bytes
Flags
AC CY V
P
S
Z
reg
reg
(mem)
reg
reg
imm
(mem)
imm
When W = 0, AL
imm8
When W = 1, AW
imm16
reg
reg
reg
(mem)
(mem)
reg
reg
reg
(mem)
reg
reg
imm
(mem)
(mem)
imm
When W = 0, AL
AL
imm8
When W = 1, AW
AW
imm16
reg
reg
reg
(mem)
(mem)
reg
reg
reg
(mem)
reg
reg
imm
(mem)
(mem)
imm
When W = 0, AL
AL
imm8
When W = 1, AW
AW
imm16
reg
reg
reg
(mem)
(mem)
reg
reg
reg
(mem)
reg
reg
imm
(mem)
(mem)
imm
When W = 0, AL
AL
imm8
When W = 1, AW
AW
imm16
Operation
Logical
opera-
tion
1 1 reg reg
mod reg mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 reg reg
mod reg mem
mod reg mem
1 1 1 0 0 reg
mod 1 0 0 mem
1 1 reg reg
mod reg mem
mod reg mem
1 1 0 0 1 reg
mod 0 0 1 mem
1 1 reg reg
mod reg mem
mod reg mem
1 1 1 1 0 reg
mod 1 1 0 mem
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
25
PD70320
TEST1
NOT1
reg8,CL
mem8,CL
reg16,CL
mem16,CL
reg8,imm3
mem8,imm3
reg16,imm4
mem16,imm4
reg8,CL
mem8,CL
reg16,CL
mem16,CL
reg8,imm3
mem8,imm3
reg16,imm4
mem16,imm4
Operation Code
0 0 0 1 0 0 0 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
3
3 to 5
3
3 to 5
4
4 to 6
4
4 to 6
3
3 to 5
3
3 to 5
4
4 to 6
4
4 to 6
Bytes
Flags
AC CY V
P
S
Z
reg8 bit No. CL = 0: Z
1
reg8 bit No. CL = 1: Z
0
(mem8) bit No. CL = 0: Z
1
(mem8) bit No. CL = 1: Z
0
reg16 bit No. CL = 0: Z
1
reg16 bit No. CL = 1: Z
0
(mem16) bit No. CL = 0: Z
1
(mem16) bit No. CL = 1: Z
0
reg8 bit No. imm3 = 0: Z
1
reg8 bit No. imm3 = 1: Z
0
(mem8) bit No. imm3 = 0: Z
1
(mem8) bit No. imm3 = 1: Z
0
reg16 bit No. imm4 = 0: Z
1
reg16 bit No. imm4 = 1: Z
0
(mem16) bit No. imm4 = 0: Z
1
(mem16) bit No. imm4 = 1: Z
0
reg8 bit No. CL
reg8 bit No. CL
(mem8) bit No. CL
(mem8) bit No. CL
reg16 bit No. CL
reg16 bit No. CL
(mem16) bit No. CL
(mem16) bit No. CL
reg8 bit No. imm3
reg8 bit No. imm3
(mem8) bit No. imm3
(mem8) bit No. imm3
reg16 bit No. imm4
reg16 bit No. imm4
(mem16) bit No. imm4
(mem16) bit No. imm4
Operation
Bit
manipu-
lation
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
U
U
U
U
U
U
U
U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0 0 0 0
0 0 0 1
0 0 0 1
1 0 0 0
1 0 0 0
1 0 0 1
1 0 0 1
0 1 1 0
0 1 1 0
0 1 1 1
0 1 1 1
1 1 1 0
1 1 1 0
1 1 1 1
1 1 1 1
2nd byte
Note
3rd byte
Note
1st byte = 0FH
CY
CY
1
1 1 1 1 0 1 0 1
CY
NOT1
Note
26
PD70320
CLR1
SET1
reg8,CL
mem8,CL
reg16,CL
mem16,CL
reg8,imm3
mem8,imm3
reg16,imm4
mem16,imm4
reg8,CL
mem8,CL
reg16,CL
mem16,CL
reg8,imm3
mem8,imm3
reg16,imm4
mem16,imm4
Operation Code
0 0 0 1 0 0 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
3
3 to 5
3
3 to 5
4
4 to 6
4
4 to 6
3
3 to 5
3
3 to 5
4
4 to 6
4
4 to 6
Bytes
Flags
AC CY V
P
S
Z
reg8 bit No. CL
0
(mem8) bit No. CL
0
reg16 bit No. CL
0
(mem16) bit No. CL
0
reg8 bit No. imm3
0
(mem8) bit No. imm3
0
reg16 bit No. imm4
0
(mem16) bit No. imm4
0
reg8 bit No. CL
1
(mem8) bit No. CL
1
reg16 bit No. CL
1
(mem16) bit No. CL
1
reg8 bit No. imm3
1
(mem8) bit No. imm3
1
reg16 bit No. imm4
1
(mem16) bit No. imm4
1
Operation
Bit
manipu-
lation
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
0 0 1 0
0 0 1 1
0 0 1 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 0 1
2nd byte
Note
3rd byte
Note
Note 1st byte = 0FH
0
1
CY
0
DIR
0
CY
1
DIR
1
1
1
1
1
1 1 1 1 1 0 0 0
1 1 1 1 1 1 0 0
1 1 1 1 1 0 0 1
1 1 1 1 1 1 0 1
CY
DIR
CY
DIR
CLR1
SET1
27
PD70320
SHL
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
Operation Code
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
3
3 to 5
Bytes
Flags
AC CY V
P
S
Z
CY
reg MSB, reg
reg
2
When reg MSB
CY, V
1
When reg MSB = CY, V
0
CY
(mem) MSB, (mem)
(mem)
2
When (mem) MSB
CY, V
1
When (mem) MSB = CY, V
0
The following operations are repeated while temp
CL
and temp
0.
CY
reg MSB, reg
reg
2
temp
temp 1
The following operations are repeated while temp
CL
and temp
0.
CY
(mem) MSB, (mem)
(mem)
2
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
CY
reg MSB, reg
reg
2
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
CY
(mem) MSB, (mem)
(mem)
2
temp
temp 1
Operation
Shift
1 1 1 0 0 reg
mod 1 0 0 mem
1 1 1 0 0 reg
mod 1 0 0 mem
1 1 1 0 0 reg
mod 1 0 0 mem
U
U
U
U
U
U
U
U
U
U
28
PD70320
SHR
SHRA
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
Operation Code
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
3
3 to 5
2
2 to 4
2
2 to 4
3
3 to 5
Bytes
Flags
AC CY V
P
S
Z
CY
reg LSB, reg
reg
2
reg MSB
bit following reg MSB: V
1
reg MSB = bit following reg MSB: V
0
CY
(mem) LSB, (mem)
(mem)
2
(mem) MSB
bit following (mem) MSB: V
1
(mem) MSB = bit following (mem) MSB: V
0
The following operations are repeated while temp
CL
and temp
0.
CY
reg LSB, reg
reg
2
temp
temp 1
The following operations are repeated while temp
CL
and temp
0.
CY
(mem) LSB, (mem)
(mem)
2
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
CY
reg LSB, reg
reg
2
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
CY
(mem) LSB, (mem)
(mem)
2
temp
temp 1
CY
reg LSB, reg
reg
2, V
0
The operand MSB remains the same status.
CY
(mem) LSB, (mem)
(mem)
2, V
0
The operand MSB remains the same status.
The following operations are repeated while temp
CL
and temp
0. CY
reg LSB, reg
reg
2
temp
temp 1
The operand MSB remains the same status.
The following operations are repeated while temp
CL
and temp
0. CY
(mem) LSB, (mem)
(mem)
2
The operand MSB remains the same status.
The following operations are repeated while temp
imm8
and temp
0. CY
reg LSB, reg
reg
2
temp
temp 1
The operand MSB remains the same status.
The following operations are repeated while temp
imm8
and temp
0. CY
(mem) LSB, (mem)
(mem)
2
temp
temp 1
The operand MSB remains the same status.
Operation
Shift
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 1 0 1 reg
mod 1 0 1 mem
1 1 1 1 1 reg
mod 1 1 1 mem
1 1 1 1 1 reg
mod 1 1 1 mem
1 1 1 1 1 reg
mod 1 1 1 mem
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
0
0
U
U
U
U
temp
temp 1
29
PD70320
ROL
ROR
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
Operation Code
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
3
3 to 5
2
2 to 4
2
2 to 4
3
3 to 5
Bytes
Flags
AC CY V
P
S
Z
CY
reg MSB, reg
reg
2 + CY
reg MSB
CY: V
1
reg MSB = CY: V
0
CY
(mem) MSB, (mem)
(mem)
2 + CY
(mem) MSB
CY: V
1
(mem) MSB = CY: V
0
The following operations are repeated while temp
CL
and temp
0.
CY
reg MSB, reg
reg
2 + CY
temp
temp 1
The following operations are repeated while temp
CL
and temp
0.
CY
(mem) MSB, (mem)
(mem)
2 + CY
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
CY
reg MSB, reg
reg
2 + CY
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
CY
(mem) MSB, (mem)
(mem)
2 + CY
temp
temp 1
CY
reg LSB, reg
reg
2
reg MSB
CY
reg MSB
bit following reg MSB: V
1
reg MSB = bit following reg MSB: V
0
CY
(mem) LSB, (mem)
(mem)
2
(mem) MSB
CY
(mem) MSB
bit following (mem) MSB: V
1
(mem) MSB = bit following (mem) MSB: V
0
The following operations are repeated while temp
CL and temp
0.
CY
reg LSB, reg
reg
2
reg MSB
CY
temp
temp 1
The following operations are repeated while temp
CL and temp
0.
CY
(mem) LSB, (mem)
(mem)
2
(mem) MSB
CY
temp
temp 1
The following operations are repeated while temp
imm8 and temp
0.
CY
reg LSB, reg
reg
2
reg MSB
CY
temp
temp 1
The following operations are repeated while temp
imm8 and temp
0.
CY
(mem) LSB, (mem)
(mem)
2
(mem) MSB
CY
temp
temp 1
Operation
Rotate
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 0 reg
mod 0 0 0 mem
1 1 0 0 1 reg
mod 0 0 1 mem
1 1 0 0 1 reg
mod 0 0 1 mem
1 1 0 0 1 reg
mod 0 0 1 mem
U
U
U
U
U
U
U
U
30
PD70320
ROLC
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
Operation Code
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
3
3 to 5
Bytes
Flags
AC CY V
P
S
Z
tmpcy
CY, CY
reg MSB
reg
reg
2 + tmpcy
reg MSB
CY: V
1
reg MSB = CY: V
0
tmpcy
CY, CY
(mem) MSB
(mem)
(mem)
2 + tmpcy
(mem) MSB
CY: V
1
(mem) MSB = CY: V
0
The following operations are repeated while temp
CL and temp
0.
tmpcy
CY, CY
reg MSB
reg
reg
2 + tmpcy
temp
temp 1
The following operations are repeated while temp
CL and temp
0.
tmpcy
CY, CY
(mem) MSB
(mem)
(mem)
2 + tmpcy
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
tmpcy
CY, CY
reg MSB
reg
reg
2 + tmpcy
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
tmpcy
CY, CY
(mem) MSB
(mem)
(mem)
2 + tmpcy
temp
temp 1
Operation
Rotate
1 1 0 1 0 reg
mod 0 1 0 mem
1 1 0 1 0 reg
mod 0 1 0 mem
1 1 0 1 0 reg
mod 0 1 0 mem
U
U
U
U
31
PD70320
RORC
reg,1
mem,1
reg,CL
mem,CL
reg,imm8
mem,imm8
Operation Code
1 1 0 1 0 0 0 W
1 1 0 1 0 0 0 W
1 1 0 1 0 0 1 W
1 1 0 1 0 0 1 W
1 1 0 0 0 0 0 W
1 1 0 0 0 0 0 W
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2 to 4
2
2 to 4
3
3 to 5
Bytes
Flags
AC CY V
P
S
Z
tmpcy
CY, CY
reg LSB
reg
reg
2
reg MSB
tmpcy
reg MSB
bit following reg MSB: V
1
reg MSB = bit following reg MSB: V
0
tmpcy
CY, CY
(mem) LSB
(mem)
(mem)
2
(mem) MSB
tmpcy
(mem) MSB
bit following (mem) MSB: V
1
(mem) MSB = bit following (mem) MSB: V
0
The following operations are repeated while temp
CL and temp
0.
tmpcy
CY, CY
reg LSB
reg
reg
2
reg MSB
tmpcy
temp
temp 1
The following operations are repeated while temp
CL and temp
0.
tmpcy
CY, CY
(mem) LSB
(mem)
(mem)
2
(mem) MSB
tmpcy
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
tmpcy
CY, CY
reg LSB
reg
reg
2
reg MSB
tmpcy
temp
temp 1
The following operations are repeated while temp
imm8
and temp
0.
tmpcy
CY, CY
(mem) LSB
(mem)
(mem)
2
(mem) MSB
tmpcy
temp
temp 1
Operation
Rotate
1 1 0 1 1 reg
mod 0 1 1 mem
1 1 0 1 1 reg
mod 0 1 1 mem
1 1 0 1 1 reg
mod 0 1 1 mem
U
U
U
U
32
PD70320
CALL
RET
near-proc
regptr16
memptr16
far-proc
memptr32
pop-value
pop-value
Operation Code
1 1 1 0 1 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 0 0 1 1 0 1 0
1 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1
1 1 0 0 0 0 1 0
1 1 0 0 1 0 1 1
1 1 0 0 1 0 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
3
2
2 to 4
5
2 to 4
1
3
1
3
Bytes
Flags
AC CY V
P
S
Z
(SP 1, SP 2)
PC, SP
SP 2
PC
PC + disp
(SP 1, SP 2)
PC, PC
regptr16
SP
SP 2
(SP 1, SP 2)
PC, SP
SP 2
PC
(memptr16)
(SP 1, SP 2)
PS, (SP 3, SP 4)
PC
SP
SP 4
PS
seg, PC
offset
(SP 1, SP 2)
PS, (SP 3, SP 4)
PC
SP
SP 4
PS
(memptr32 + 2), PC
(memptr32)
PC
(SP + 1, SP)
SP
SP + 2
PC
(SP + 1, SP)
SP
SP + 2, SP
SP + pop-value
PC
(SP + 1, SP)
PS
(SP + 3, SP + 2)
SP
SP + 4
PC
(SP + 1, SP)
PS
(SP + 3, SP + 2)
SP
SP + 4, SP
SP + pop-value
Operation
Sub-
routine
control
1 1 0 1 0 reg
mod 0 1 0 mem
mod 0 1 1 mem
33
PD70320
PUSH
POP
PREPARE
DISPOSE
BR
mem16
reg16
sreg
PSW
R
imm8
imm16
mem16
reg16
sreg
PSW
R
imm16,imm8
near-label
short-label
regptr16
memptr16
far-label
memptr32
Operation Code
1 1 1 1 1 1 1 1
0 1 0 1 0 reg
0 0 0 sreg 1 1 0
1 0 0 1 1 1 0 0
0 1 1 0 0 0 0 0
0 1 1 0 1 0 1 0
0 1 1 0 1 0 0 0
1 0 0 0 1 1 1 1
0 1 0 1 1 reg
0 0 0 sreg 1 1 1
1 0 0 1 1 1 0 1
0 1 1 0 0 0 0 1
1 1 0 0 1 0 0 0
1 1 0 0 1 0 0 1
1 1 1 0 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 0 1 0 1 0
1 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2 to 4
1
1
1
1
2
3
2 to 4
1
1
1
1
4
1
3
2
2
2 to 4
5
2 to 4
Bytes
Flags
AC CY V
P
S
Z
(SP 1, SP 2)
(mem16)
SP
SP 2
(SP 1, SP 2)
reg16
SP
SP 2
(SP 1, SP 2)
sreg
SP
SP 2
(SP 1, SP 2)
PSW
SP
SP 2
Push registers on the stack
(SP 1, SP 2)
imm8 sign extension
SP
SP 2
(SP 1, SP 2)
imm16
SP
SP 2
SP
SP + 2
(mem16)
(SP 1, SP 2)
SP
SP + 2
reg16
(SP 1, SP 2)
SP
SP + 2
sreg: SS, DS0, DS1
sreg
(SP 1, SP 2)
SP
SP + 2
PSW
(SP 1, SP 2)
Pop registers from the stack
Prepare New Stack Frame
Dispose of Stack Frame
PC
PC + disp
PC
PC + ext-disp8
PC
regptr16
PC
(memptr16)
PS
seg
PC
offset
PS
(memptr32 + 2)
PC
(memptr32)
Operation
Stack
manipu-
lation
mod 1 1 0 mem
mod 0 0 0 mem
1 1 1 0 0 reg
mod 1 0 0 mem
mod 1 0 1 mem
Branch
R
R
R
R
R
R
34
PD70320
BV
BNV
BC
BL
BNC
BNL
BE
BZ
BNE
BNZ
BNH
BH
BN
BP
BPE
BPO
BLT
BGE
BLE
BGT
DBNZNE
DBNZE
DBNZ
BCWZ
BTCLR
Note
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
short-label
sfr,
imm3,
short-label
Operation Code
0 1 1 1 0 0 0 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
5
Bytes
Flags
AC CY V
P
S
Z
if V = 1
if V = 0
if CY = 1
if CY = 0
if Z = 1
if Z = 0
if CY
Z = 1
if CY
Z = 0
if S = 1
if S = 0
if P = 1
if P = 0
if S
V = 1
if S
V = 0
if (S
V)
Z = 1
if (S
V)
Z = 0
CW = CW 1
if Z = 0 and CW
0
CW = CW 1
if Z = 1 and CW
0
CW = CW 1
if CW
0
if CW = 0
When (sfr) bit No. imm3 = 1, PC
PC + ext-disp8 and (sfr)
bit No. imm3
0.
Operation
Condi-
tional
branch
1 0 0 1 1 1 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
1 1 1 0 0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0 1 1 1 1
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
PC
PC + ext-disp8
Note This instruction is newly added to the PD70108/70116.
35
PD70320
BRK
BRKV
RETI
RETRBI
Note
FINT
Note
CHKIND
BRKCS
Note
TSKSW
Note
3
imm8
(
3)
reg16,mem32
reg16
reg16
Operation Code
1 1 0 0 1 1 0 0
1 1 0 0 1 1 0 1
1 1 0 0 1 1 1 0
1 1 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1
0 1 1 0 0 0 1 0
0 0 0 0 1 1 1 1
1 1 0 0 0 reg
0 0 0 0 1 1 1 1
1 1 1 1 1 reg
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
1
2
1
1
2
2
2 to 4
3
3
Bytes
Flags
AC CY V
P
S
Z
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS,
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0
PS
(15, 14), PC
(13, 12)
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS,
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0
PS
(n
4 + 3, n
4 + 2), PC
(n
4 + 1, n
4) n = imm8
When V = 1,
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS,
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0
PS
(19, 18), PC
(17, 16)
PC
(SP + 1, SP), PS
(SP + 3, SP + 2),
PSW
(SP + 5, SP + 4), SP
SP + 6
PC
Save PC, PSW
Save PSW
Reports the CPU internal interrupt controller that interrupt service
routine operation has ended.
When (mem32) > reg16 or (mem32 + 2) < reg16,
(SP 1, SP 2)
PSW, (SP 3, SP 4)
PS,
(SP 5, SP 6)
PC, SP
SP 6
IE
0, BRK
0
PS
(23, 22), PC
(21, 20)
RB2 0
lower 3 bits of reg16, IE
0, BRK
0
Save PSW
PSW, Save PC
PC, PC
Vector PC
RB2
0
lower 3 bits of reg16,
Old register bank Save PSW and Save PC
PSW and PC,
PSW and PC
New register bank Save PSW and Save PC
Operation
Interrupt
1 0 0 1 0 0 0 1
1 0 0 1 0 0 1 0
mod reg mem
0 0 1 0 1 1 0 1
1 0 0 1 0 1 0 0
Note These instructions are newly added to the PD70108/70116.
Register
bank
switch
R
R
R
R
R
R
R
R
R
R
R
R
36
PD70320
HALT
STOP
Note 2
POLL
DI
EI
BUSLOCK
FPO1
Note 3
FPO2
Note 3
NOP
Note 1
fp-op
fp-op,mem
fp-op
fp-op,mem
Operation Code
1 1 1 1 0 1 0 0
0 0 0 0 1 1 1 1
1 0 0 1 1 0 1 1
1 1 1 1 1 0 1 0
1 1 1 1 1 0 1 1
1 1 1 1 0 0 0 0
1 1 0 1 1 X X X
1 1 0 1 1 X X X
0 1 1 0 0 1 1 X
0 1 1 0 0 1 1 X
1 0 0 1 0 0 0 0
0 0 1 sreg 1 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Group
Mnemonic
Operand
1
2
1
1
1
1
2
2 to 4
2
2 to 4
1
1
Bytes
Flags
AC CY V
P
S
Z
CPU Halt
CPU Stop
Poll and wait
IE
0
IE
1
Bus Lock Prefix
No Operation
data bus
(mem)
No Operation
data bus
(mem)
No Operation
Segment override prefix
Operation
CPU
control
1 0 0 1 1 1 1 0
1 1 Y Y Y Z Z Z
mod Y Y Y mem
1 1 Y Y Y Z Z Z
mod Y Y Y mem
Notes 1. DS0:, DS1:, PS: and SS:
2. This instruction is newly added to the PD70108/70116.
3. In the PD70320, an interrupt is generated without executing these instructions.
37
PD70320
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Data
MOV
reg, reg
2
2
2
2
transfer
mem, reg
EA + 4 + T
EA + 2
EA + 6 + 2T
EA + 2
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
mem, imm
EA + 5 + T
EA + 5 + T
EA + 5 + 2T
EA + 5 + T
reg, imm
5
5
6
6
acc, dmem
9 + T
9 + T
11 + 2T
11 + 2T
dmem, acc
7 + T
5
9 + 2T
5
sreg, reg16
--
--
4
4
sreg, mem16
--
--
EA + 10 + 2T
EA + 10 + 2T
reg16, sreg
--
--
3
3
mem16, sreg
--
--
EA + 7 + 2T
EA + 3
DS0, reg16,
--
--
EA + 19 + 4T
EA + 19 + 4T
mem32
DS1, reg16,
--
--
EA + 19 + 4T
EA + 19 + 4T
mem32
AH, PSW
2
2
--
--
PSW, AH
3
3
--
--
LDEA
reg16, mem16
--
--
EA + 2
EA + 2
TRANS
src-table
10 + T
10 + T
--
--
XCH
reg, reg
3
3
3
3
mem, reg/
EA + 10 + 2T
EA + 8 + 2T
EA + 14 + 2T
EA + 10 + 2T
reg, mem
AW, reg16/
--
--
4
4
reg16, AW
MOVSPA
--
--
16
16
MOVSPB
reg16
--
--
11
11
Repeat
REPC
2
2
2
2
prefix
REPNC
2
2
2
2
REP/REPE/
2
2
2
2
REPZ
REPNE/
2
2
2
2
REPNZ
Primitive
MOVKB
Note
dst-block,
20 + 2T
16 + T
24 + 4T
20 + 2T
block
src-block
16 + (16 + 2T)n
16 + (12 + T)n
16 + (20 + 4T)n
16 + (12 + 2T)n
transfer
CMPKB
Note
dst-block,
23 + 2T
19 + T
27 + 4T
21 + 4T
src-block
16 + (21 + 2T)n
16 + (21 + 2T)n
16 + (25 + 4T)n
16 + (25 + 2T)n
Note n
1
Table 2-8. Number of Clocks (1/10)
38
PD70320
Table 2-8. Number of Clocks (2/10)
Notes 1. n
1
2. When IBRK = 1
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Primitive
CMPM
Note 1
dst-block
17 + T
17 + T
19 + 2T
19 + 2T
block
src-block
16 + (15 + T)n
16 + (15 + T)n
16 + (17 + 2T)n
16 + (17 + 2T)n
transfer
LDM
Note 1
src-block
12 + T
12 + T
14 + 2T
14 + 2T
16 + (10 + T)n
16 + (10 + T)n
16 + (12 + 2T)n
16 + (12 + 2T)n
STM
Note 1
dst-block
12 + T
10
14 + 2T
10
16 + (8 + T)n
16 + (6+ T)n
16 + (10 + 2T)n
16 + (6 + 2T)n
Bit field
INS
reg8, reg8
63 to 155 (The processing differs among bit lengths.)
manipula-
reg8, imm4
64 to 156 (The processing differs among bit lengths.)
tion
EXT
reg8, reg8
41 to 121 (The processing differs among bit lengths.)
reg8, imm4
42 to 122 (The processing differs among bit lengths.)
I/O
IN
Note 2
acc, imm8
14 + T
14 + T
16 + 2T
16 + 2T
acc, DW
13 + T
13 + T
15 + 2T
15 + 2T
OUT
Note 2
imm8, acc
10 + T
10 + T
10 + 2T
10 + 2T
DW, acc
9 + T
9 + T
9 + 2T
9 + 2T
Primitive
INM
Note 2
dst-block, DW
19 + 2T
17 + 2T
21 + 4T
17 + 4T
I/O
18 + (13 + 2T)n
18 + (11 + 2T)n
18 + (15 + 4T)n
18 + (11 + 4T)n
OUTM
Note 2
DW, src-block
19 + 2T
17 + 2T
21 + 4T
17 + 4T
18 + (13 + 2T)n
18 + (11 + 2T)n
18 + (15 + 4T)n
18 + (11 + 4T)n
Addition/
ADD
reg, reg
2
2
2
2
subtraction
mem, reg
EA + 8 + 2T
EA + 6 + T
EA + 12 + 4T
EA + 8 + 2T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, imm
5
5
6
6
mem, imm
EA + 9 + 2T
EA + 7 + 2T
EA + 14 + 4T
EA + 10 + 4T
acc, imm
5
5
6
6
ADDC
reg, reg
2
2
2
2
mem, reg
EA + 8 + 2T
EA + 6 + T
EA + 12 + 4T
EA + 8 + 2T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, imm
5
5
6
6
mem, imm
EA + 9 + 2T
EA + 7 + 2T
EA + 14 + 4T
EA + 10 + 4T
acc, imm
5
5
6
6
39
PD70320
Table 2-8. Number of Clocks (3/10)
Note n: 1/2 of the number of BCD digits.
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Addition/
SUB
reg, reg
2
2
2
2
subtraction
mem, reg
EA + 8 + 2T
EA + 6 + T
EA + 12 + 4T
EA + 8 + 2T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, imm
5
5
6
6
mem, imm
EA + 9 + 2T
EA + 7 + 2T
EA + 14 + 4T
EA + 10 + 4T
acc, imm
5
5
6
6
SUBC
reg, reg
2
2
2
2
mem, reg
EA + 8 + 2T
EA + 6 + T
EA + 12 + 4T
EA + 8 + 2T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, imm
5
5
6
6
mem, imm
EA + 9 + 2T
EA + 7 + 2T
EA + 14 + 4T
EA + 10 + 4T
acc, imm
5
5
6
6
BCD
ADD4S
Note
22 + (27 + 3T)n
22 + (25 + 3T)n
--
--
operation
SUB4S
Note
22 + (27 + 3T)n
22 + (25 + 3T)n
--
--
CMP4S
Note
22 + (23 + 3T)n
22 + (23 + 3T)n
--
--
ROL4
reg8
17
17
--
--
mem8
EA + 18 + 2T
EA + 16 + 2T
--
--
ROR4
reg8
21
21
--
--
mem8
EA + 24 + 2T
EA + 22 + 2T
--
--
Increment / INC
reg8
5
5
--
--
decrement
mem8
EA + 11 + 2T
EA + 9 + 2T
EA + 15 + 4T
EA + 11 + 4T
reg16
--
--
2
2
DEC
reg8
5
5
--
--
mem8
EA + 11 + 2T
EA + 9 + 2T
EA + 15 + 4T
EA + 11 + 4T
reg16
--
--
2
2
Multiplica-
MULU
reg8
24
24
--
--
tion
mem8
EA + 26 + T
EA + 26 + T
--
--
reg16
--
--
32
32
mem16
--
--
EA + 34 + 2T
EA + 34 + 2T
40
PD70320
Table 2-8. Number of Clocks (4/10)
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Multiplica-
MUL
reg8
31 to 40
31 to 40
--
--
tion
mem8
EA + 33 + T to
EA + 33 + T to
--
--
EA + 42 + T
EA + 42 + T
reg16
--
--
39 to 48
39 to 48
mem16
--
--
EA + 43 + 2T to
EA + 43 + 2T to
EA + 52 + 2T
EA + 52 + 2T
reg16, (reg16,)
--
--
39 to 49
39 to 49
imm8
reg16, mem16,
--
--
EA + 43 + 2T to
EA + 43 + 2T to
imm8
EA + 53 + 2T
EA + 53 + 2T
reg16, (reg16,)
--
--
40 to 50
40 to 50
imm16
reg16, mem16,
--
--
EA + 44 + 2T to
EA + 44 + 2T to
imm16
EA + 54 + 2T
EA + 54 + 2T
Unsigned
DIVU
reg8
31
31
--
--
division
mem8
EA + 33 + T
EA + 33 + T
--
--
reg16
--
--
39
39
mem16
--
--
EA + 43 + 2T
EA + 43 + 2T
Signed
DIV
reg8
46 to 56
46 to 56
--
--
division
mem8
EA + 48 + T to
EA + 48 + T to
--
--
EA + 58 + T
EA + 58 + T
reg16
--
--
54 to 64
54 to 64
mem16
--
--
EA + 58 + 2T to
EA + 58 + 2T to
EA + 68 + 2T
EA + 68 + 2T
BCD
ADJBA
17
17
--
--
adjustment ADJ4A
9
9
--
--
ADJBS
17
17
--
--
ADJ4S
9
9
--
--
Data
CVTBD
19
19
--
--
conversion CVTDB
20
20
--
--
CVTBW
3
3
--
--
CVTWL
--
--
8
8
Compare
CMP
reg, reg
2
2
2
2
mem, reg
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, imm
5
5
6
6
mem, imm
EA + 7 + T
EA + 7 + T
EA + 10 + 2T
EA + 10 + 2T
acc, imm
5
5
6
6
41
PD70320
Table 2-8. Number of Clocks (5/10)
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Comple
NOT
reg
5
5
5
5
ment
mem
EA + 11 + 2T
EA + 9 + T
EA + 15 + 4T
EA + 11 + 2T
operation
NEG
reg
5
5
5
5
mem
EA + 11 + 2T
EA + 9 + T
EA + 15 + 4T
EA + 11 + 2T
Logical
TEST
reg, reg
4
4
4
4
operation
mem, reg/
EA + 8 + T
EA + 8 + T
EA + 10 + 2T
EA + 10 + 2T
reg, mem
reg, imm
7
7
8
8
mem, imm
EA + 11 + T
EA + 11 + T
EA + 11 + 2T
EA + 11 + 2T
acc, imm
5
5
6
6
AND
reg, reg
2
2
2
2
mem, reg
EA + 8 + 2T
EA + 6 + T
EA + 12 + 4T
EA + 8 + 2T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, imm
5
5
6
6
mem, imm
EA + 9 + T
EA + 7 + T
EA + 14 + 4T
EA + 10 + 4T
acc, imm
5
5
6
6
OR
reg, reg
2
2
2
2
mem, reg
EA + 8 + 2T
EA + 6 + T
EA + 12 + 4T
EA + 8 + 2T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, imm
5
5
6
6
mem, imm
EA + 9 + T
EA + 7 + T
EA + 14 + 4T
EA + 10 + 4T
acc, imm
5
5
6
6
XOR
reg, reg
2
2
2
2
mem, reg
EA + 8 + 2T
EA + 6 + T
EA + 12 + 4T
EA + 8 + 2T
reg, mem
EA + 6 + T
EA + 6 + T
EA + 8 + 2T
EA + 8 + 2T
reg, imm
5
5
6
6
mem, imm
EA + 9 + T
EA + 7 + T
EA + 14 + 4T
EA + 10 + 4T
acc, imm
5
5
6
6
Bit
TEST1
reg8, CL
7
7
--
--
manipula-
mem8, CL
EA + 11 + T
EA + 11 + T
--
--
tion
reg16, CL
--
--
7
7
mem16, CL
--
--
EA + 13 + 2T
EA + 13 + 2T
reg8, imm3
6
6
--
--
mem8, imm3
EA + 8 + T
EA + 8 + T
--
--
reg16, imm4
--
--
6
6
mem16, imm4
--
--
EA + 10 + 2T
EA + 10 + 2T
NOT1
reg8, CL
7
7
--
--
mem8, CL
EA + 13 + 2T
EA + 11 + T
--
--
reg16, CL
--
--
7
7
42
PD70320
Table 2-8. Number of Clocks (6/10)
Note n: Shift count
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Bit
NOT1
mem16, CL
--
--
EA + 17 + 4T
EA + 13 + 2T
manipula-
reg8, imm3
6
6
--
--
tion
mem8, imm3
EA + 10 + 2T
EA + 8 + T
--
--
reg16, imm4
--
--
6
6
mem16, imm4
--
--
EA + 14 + 4T
EA + 10 + 2T
NOT1
CY
2
2
2
2
Bit
CLR1
reg8, CL
8
8
--
--
manipula-
mem8, CL
EA + 14 + 2T
EA + 12 + T
--
--
tion
reg16, CL
--
--
8
8
mem16, CL
--
--
EA + 18 + 4T
EA + 14 + 2T
reg8, imm3
7
7
--
--
mem8, imm3
EA + 11 + 2T
EA + 9 + T
--
--
reg16, imm4
--
--
7
7
mem16, imm4
--
--
EA + 15 + 4T
EA + 10 + 2T
SET1
reg8, CL
7
7
--
--
mem8, CL
EA + 13 + 2T
EA + 11 + T
--
--
reg16, CL
--
--
7
7
mem16, CL
--
--
EA + 17 + 4T
EA + 13 + 2T
reg8, imm3
6
6
--
--
mem8, imm3
EA + 10 + 2T
EA + 8 + T
--
--
reg16, imm4
--
--
6
6
mem16, imm4
--
--
EA + 14 + 4T
EA + 10 + 2T
CLR1
CY
2
2
2
2
DIR
2
2
2
2
SET1
CY
2
2
2
2
DIR
2
2
2
2
Shift
SHL
reg,1
8
8
8
8
Note
mem, 1
EA + 14 + 2T
EA + 12 + T
EA + 18 + 4T
EA + 14 + 2T
reg, CL
11 + 2n
11 + 2n
11 + 2n
11 + 2n
mem, CL
EA + 17 + 2T + 2n EA + 15 + T + 2n EA + 21 + 4T + 2n EA + 17 + 2T + 2n
reg, imm8
9 + 2n
9 + 2n
9 + 2n
9 + 2n
mem, imm8
EA + 13 + 2T + 2n EA + 11 + T + 2n EA + 17 + 4T + 2n EA + 13 + 2T + 2n
SHR
reg, 1
8
8
8
8
mem, 1
EA + 14 + 2T
EA + 12 + T
EA + 18 + 4T
EA + 14 + 2T
43
PD70320
Table 2-8. Number of Clocks (7/10)
Note n: Shift count
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Shift
SHR
reg, CL
11 + 2n
11 + 2n
11 + 2n
11 + 2n
Note
mem, CL
EA + 17 + 2T + 2n EA + 15 + T + 2n EA + 21 + 4T + 2n EA + 17 + 2T + 2n
reg, imm8
9 + 2n
9 + 2n
9 + 2n
9 + 2n
mem, imm8
EA + 13 + 2T + 2n EA + 11 + T + 2n EA + 17 + 4T + 2n EA + 13 + 2T + 2n
SHRA
reg,1
8
8
8
8
Note
mem, 1
EA + 14 + 2T
EA + 12 + T
EA + 18 + 4T
EA + 14 + 2T
reg, CL
11 + 2n
11 + 2n
11 + 2n
11 + 2n
mem, CL
EA + 17 + 2T + 2n EA + 15 + T + 2n EA + 21 + 4T + 2n EA + 17 + 2T + 2n
reg, imm8
9 + 2n
9 + 2n
9 + 2n
9 + 2n
mem, imm8
EA + 13 + 2T + 2n EA + 11 + T + 2n EA + 17 + 4T + 2n EA + 13 + 2T + 2n
Rotate
ROL
reg,1
8
8
8
8
Note
mem, 1
EA + 14 + 2T
EA + 12 + T
EA + 18 + 4T
EA + 14 + 2T
reg, CL
11 + 2n
11 + 2n
11 + 2n
11 + 2n
mem, CL
EA + 17 + 2T + 2n EA + 15 + T + 2n EA + 21 + 4T + 2n EA + 17 + 2T + 2n
reg, imm8
9 + 2n
9 + 2n
9 + 2n
9 + 2n
mem, imm8
EA + 13 + 2T + 2n EA + 11 + T + 2n EA + 17 + 4T + 2n EA + 13 + 2T + 2n
ROR
reg,1
8
8
8
8
Note
mem, 1
EA + 14 + 2T
EA + 12 + T
EA + 18 + 4T
EA + 14 + 2T
reg, CL
11 + 2n
11 + 2n
11 + 2n
11 + 2n
mem, CL
EA + 17 + 2T + 2n EA + 15 + T + 2n EA + 21 + 4T + 2n EA + 17 + 2T + 2n
reg, imm8
9 + 2n
9 + 2n
9 + 2n
9 + 2n
mem, imm8
EA + 13 + 2T + 2n EA + 11 + T + 2n EA + 17 + 4T + 2n EA + 13 + 2T + 2n
ROLC
reg,1
8
8
8
8
Note
mem, 1
EA + 14 + 2T
EA + 12 + T
EA + 18 + 4T
EA + 14 + 2T
reg, CL
11 + 2n
11 + 2n
11 + 2n
11 + 2n
mem, CL
EA + 17 + 2T + 2n EA + 15 + T + 2n EA + 21 + 4T + 2n EA + 17 + 2T + 2n
reg, imm8
9 + 2n
9 + 2n
9 + 2n
9 + 2n
mem, imm8
EA + 13 + 2T + 2n EA + 11 + T + 2n EA + 17 + 4T + 2n EA + 13 + 2T + 2n
RORC
reg,1
8
8
8
8
mem, 1
EA + 14 + 2T
EA + 12 + T
EA + 18 + 4T
EA + 14 + 2T
44
PD70320
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Rotate
RORC
reg, CL
11 + 2n
11 + 2n
11 + 2n
11 + 2n
Note
mem, CL
EA + 17 + 2T + 2n EA + 15 + T + 2n EA + 21 + 4T + 2n EA + 17 + 2T + 2n
reg, imm8
9 + 2n
9 + 2n
9 + 2n
9 + 2n
mem, imm8
EA + 13 + 2T + 2n EA + 11 + T + 2n EA + 17 + 4T + 2n EA + 13 + 2T + 2n
Subroutine CALL
near-proc
--
--
22 + 2T
18 + 2T
control
regptr16
--
--
22 + 2T
18 + 2T
memptr16
--
--
EA + 26 + 4T
EA + 24 + 4T
far-proc
--
--
38 + 4T
34 + 4T
memptr32
--
--
EA + 36 + 8T
EA + 24 + 8T
RET
--
--
20 + 2T
20 + 2T
pop-value
--
--
20 + 2T
20 + 2T
--
--
29 + 4T
29 + 4T
pop-value
--
--
30 + 4T
30 + 4T
Stack
PUSH
mem16
--
--
EA + 18 + 4T
EA + 14 + 4T
manipula-
reg16
--
--
10 + 2T
6
tion
sreg
--
--
11 + 2T
7
PSW
--
--
10 + 2T
6
R
--
--
82 + 16T
50
imm8
--
--
13 + 2T
9
imm16
--
--
14 + 2T
10
POP
mem16
--
--
EA + 16 + 4T
EA + 12 + 2T
reg16
--
--
12 + 2T
12 + 2T
sreg
--
--
13 + 2T
13 + 2T
PSW
--
--
14 + 2T
14 + 2T
R
--
--
82 + 16T
58
PREPARE
imm16, imm8
When imm8 = 0, 27 + 2T
When imm8 = 1, 39 + 4T
When imm8 = n, n > 1, 46 + 19(n 1) + 4T
DISPOSE
--
--
12 + 2T
12 + 2T
Table 2-8. Number of Clocks (8/10)
Note n: Shift count
45
PD70320
Table 2-8. Number of Clocks (9/10)
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Branch
BR
near-label
--
--
12
12
short-label
--
--
12
12
regptr16
--
--
13
13
memptr16
--
--
EA + 17 + 2T
EA + 17 + 2T
far-label
--
--
15
15
memptr32
--
--
EA + 25 + 4T
EA + 25 + 4T
Conditional BV
short-label
--
--
15/8
15/8
branch
BNV
short-label
--
--
15/8
15/8
BC/BL
short-label
--
--
15/8
15/8
BNC/BNL
short-label
--
--
15/8
15/8
BE/BZ
short-label
--
--
15/8
15/8
BNE/BNZ
short-label
--
--
15/8
15/8
BNH
short-label
--
--
15/8
15/8
BH
short-label
--
--
15/8
15/8
BN
short-label
--
--
15/8
15/8
BP
short-label
--
--
15/8
15/8
BPE
short-label
--
--
15/8
15/8
BPO
short-label
--
--
15/8
15/8
BLT
short-label
--
--
15/8
15/8
BGE
short-label
--
--
15/8
15/8
BLE
short-label
--
--
15/8
15/8
BGT
short-label
--
--
15/8
15/8
DBNZNE
short-label
--
--
17/8
17/8
DBNZE
short-label
--
--
17/8
17/8
DBNZ
short-label
--
--
17/8
17/8
BCWZ
short-label
--
--
15/8
15/8
BTCLR
sfr, imm3,
29/21
29/21
--
--
short-label
Interrupt
BRK
3
--
--
55 + 10T
43 + 10T
imm8 (
3)
--
--
56 + 10T
44 + 10T
BRKV
--
--
55 + 10T
43 + 10T
RETI
--
--
45 + 6T
37 + 2T
RETRBI
--
--
12
12
FINT
2
2
2
2
CHKIND
reg16, mem32
--
--
EA + 26 + 4T
EA + 26 + 4T
46
PD70320
Table 2-8. Number of Clocks (10/10)
Byte Processing
Word Processing
Group
Mnemonic
Operands
On-chip RAM
On-chip RAM
On-chip RAM
On-chip RAM
Access Enable
Access Disable
Access Enable
Access Disable
Register
BRKCS
reg16
--
--
15
15
bank switch TSKSW
reg16
--
--
20
20
CPU
HALT
--
--
--
--
control
STOP
--
--
--
--
POLL
--
--
--
--
DI
4
4
4
4
EI
12
12
12
12
BUSLOCK
2
2
2
2
FPO1
fp-op
--
--
60 + 10T
48 + 10T
fp-op, mem
--
--
60 + 10T
48 + 10T
FPO2
fp-op
--
--
60 + 10T
48 + 10T
fp-op, mem
--
--
60 + 10T
48 + 10T
NOP
4
4
4
4
Segment override prefix
2
2
2
2
(DS0:, DS1:, PS: and SS:)
47
PD70320
3. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T
A
= 25
C)
Parameter
Symbol
Test Conditions
Rating
Unit
Supply Voltage
V
DD
0.5 to +7.0
V
Input Voltage
V
TH
0.5 to V
DD
+ 0.5
V
V
I
0.5 to V
DD
+ 0.5
V
Output Voltage
V
O
0.5 to V
DD
+ 0.5
V
Output Current Low
I
OL
Each output pin
4.0
mA
Total
50
mA
Output Current High
I
OH
Each output pin
2.0
mA
Total
20
mA
Operating Ambient Temperature
T
A
40 to +85
C
Storage Temperature
T
stg
65 to +150
C
Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with each
other, and also avoid direct connections to V
DD
, V
CC
or GND. However, the open drain pins or
the open collector pins can be directly connected with each other. For the external circuit
designed with the timing specifications so that any collision of the outputs from the pins subject
to high-impedance state may be prevented, direct connection can be also made.
2. Product quality may suffer if the absolute maximum ratings are exceeded for even a single
parameter, or even momentarily. In other words, the absolute maximum ratings are rated values
at which the product is on the verge of suffering physical damage, and therefore the product
must be used under conditions which ensure that the absolute maximum ratings are not
exceeded. The normal operation and reliability of the product can be only assured with the
specifications and the conditions indicated as the DC and AC characteristics.
48
PD70320
OSCILLATOR CHARACTERISTICS
(T
A
= 40 to +85
C, V
DD
= +5.0 V
10%, V
SS
= 0 V, 0 V
V
TH
V
DD
+ 0.1 V)
Resonator
Recommended Circuit
Parameter
PD70320
PD70320-8
Unit
MIN.
MAX.
MIN.
MAX.
Ceramic or Crystal
Oscillation
4
10
4
16
MHz
Resonator
frequency (f
XX
)
External Clock
X1 input
4
10
4
16
MHz
frequency (f
X
)
X1 rise/fall time
0
20
0
20
ns
(t
XR
, t
XF
)
X1 input high-/
35
250
20
250
ns
low-level width
(t
WXH
, t
WXL
)
Cautions 1. Mount the oscillation circuit as close to pins X1 and X2 as possible.
2. Do not route other signal lines through the area within the dotted line.
X1
X2
C1
C2
HCMOS
Inverter
X1
X2
1
2
X1
X2
HCMOS
Inverter
Open
or
49
PD70320
Manufacturer
Part Number
Recommended Constants
C1 [pF]
C2 [pF]
Kyocera Corp.
KBR-10.0M
Note 1
33
33
Murata Mfg. Co., Ltd.
CSA7.37MT040
Note 2
100
100
CSA10.0MT
Note 1
47
47
CSA11.0MT
Note 2
CSA16.0MX040
Note 1
30
30
TDK
FCR10.0M2S
Note 2
30
30
FCR16.0M2S
Note 2
15
6
FCR16.0M2G
Note 2
22
10
RECOMMENDED OSCILLATOR CONSTANT
Ceramic resonator
Notes 1. The operating ambient temperature (T
A
) is 10
C to +70
C when this resonator is used.
2. The operating ambient temperature (T
A
) is 20
C to +80
C when this resonator is used.
Crystal resonator
Remark
For more details on the characteristics of the resonators, please contact the manufacturer.
Manufacturer
Part Number
Recommended Constants
C1 [pF]
C2 [pF]
Kinseki Co., Ltd.
HC-49/U(KR-100)
22
22
HC-49/U(KR-160)
22
22
50
PD70320
CAPACITANCE (T
A
= 25
C, V
DD
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input Capacitance
C
I
f
C
= 1 MHz
10
pF
Output Capacitance
C
O
Unmeasured pins returned to 0 V.
20
pF
Input/output Capacitance
C
IO
20
pF
DC CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= +5.0 V
10%)
AC CHARACTERISTICS (T
A
= 40 to +85
C, V
DD
= +5.0 V
10%)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input Voltage Low
V
IL
0
0.8
V
Input Voltage High
V
IH1
Except RESET, P10/NMI, X1, X2
2.2
V
DD
V
V
IH2
RESET, P10/NMI, X1, X2
0.8V
DD
V
DD
V
Output Voltage Low
V
OL
I
OL
= 1.6 mA
0.45
V
Output Voltage High
V
OH
I
OH
= 0.4 mA
V
DD
1.0
V
Input Current
I
I
EA, P10/NMI; 0
V
I
V
DD
20
A
Input Leakage Current
I
LI
Except EA, P10/NMI; 0
V
I
V
DD
10
A
Output Leakage Current
I
LO
0
V
O
V
DD
10
A
V
TH
Current
I
TH
0 V
V
TH
V
DD
0.5
1.0
mA
V
DD
Supply Current
I
DD1
Operating mode
PD70320
50
100
mA
PD70320-8
65
120
mA
I
DD2
HALT mode
PD70320
20
40
mA
PD70320-8
25
50
mA
I
DD3
STOP mode
10
30
A
Parameter
Symbol
Test Conditions
PD70320
PD70320-8
Unit
MIN.
MAX.
MIN.
MAX.
X1 Input Cycle Time
t
CYX
98
250
62
250
ns
X1 Input High-/Low-Level Width
t
WXH
, t
WXL
35
20
ns
X1 Input Rise/Fall Time
t
XR
, t
XF
20
20
ns
CLKOUT Output Cycle Time
t
CYK
f
X
/2, T = t
CYK
200
2000
125
2000
ns
CLKOUT Output High-/Low-Level Width
t
WKH
, t
WKL
0.5T 15
0.5T 15
ns
CLKOUT Output Rise/Fall Time
t
KR
, t
KF
15
15
ns
Input Rise/Fall Time
t
IR
, t
IF
Except RESET, NMI,
20
20
ns
X1 and X2
t
IRS
, t
IFS
RESET, NMI
30
30
ns
Output Rise/Fall Time
t
OR
, t
OF
Except CLKOUT
20
20
ns
51
PD70320
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Address Delay Time from CLKOUT
t
DKA
90
ns
Data Input Delay Time from Address
t
DADR
(n + 1.5)T 90
ns
Data Delay Time from MREQ
t
DMRD
(n + 1)T 75
ns
Data Delay Time from MSTB
t
DMSD
(n+ 0.5)T 75
ns
MSTB
Delay Time from MREQ
t
DMRMS
0.5T 35
0.5T + 35
ns
MREQ Low-Level Width
t
WMRL
(n + 1)T 30
(n + 1)T + 30
ns
Address Hold Time (from MREQ
)
t
HMA
0.5T 30
ns
Data Input Hold Time (from MREQ
)
t
HMDR
0
ns
Control Signal Recovery Time
t
RVC
T 25
ns
Data Output Delay Time from Address
t
DADW
0.5T + 50
ns
Address Setup Time (to MREQ
)
t
DAMR
0.5T 30
ns
Address Setup Time (to MSTB
)
t
DAMS
T 30
ns
MSTB Low-Level Width
t
WMSL
(n + 0.5)T 30
(n + 0.5)T + 30
ns
Data Output Setup Time (to MSTB
)
t
SDM
(n + 1)T 50
ns
Data Output Hold Time (from MSTB
)
t
HMDW
0.5T 30
ns
Address Setup Time (to IOSTB
)
t
DAIS
0.5T 30
ns
Data Delay Time from IOSTB
t
DISD
(n + 1)T 90
ns
IOSTB Low-Level Width
t
WISL
(n + 1)T 30
ns
Address Hold Time (from IOSTB
)
t
HISA
0.5T 30
ns
Data Input Hold Time (from IOREQ
)
t
HISDR
0
ns
Data Output Setup Time (to IOSTB
)
t
SDIS
(n + 1)T 50
ns
Data Output Hold Time (from IOSTB
)
t
HISDW
0.5T 30
ns
DMARQ Setup Time (to MREQ
)
t
SDADQ
Demand release mode
1T
ns
DMARQ Hold Time (from DMAAK
)
t
HDADQ
Demand release mode
0
ns
DMAAK Output Low-Level Width
t
WDMRL
Read mode
(n + 1.5)T 30
ns
TC
Delay Time from DMAAK
t
DDATC
0.5T + 50
ns
TC Low-Level Width
t
WTCL
2T 30
ns
DMAAK Output Low-Level Width
t
WDMWL
Write mode
(n + 1)T 30
ns
Address Setup Time (to REFRQ
)
t
DARF
0.5T 30
ns
REFRQ Low-Level Width
t
WRFL
(n + 1)T 30
ns
Address Hold Time (from REFRQ
)
t
HRFA
0.5T 30
ns
RESET Low-Level Width
t
WRSL1
STOP mode release/
30
ms
power-ON reset
t
WRSL2
System reset
5
s
READY Setup Time
t
SCRY0
n
2
T 100
ns
(to MREQ
, IOSTB
)
t
SCRY
n
3
(n 1)T 100
ns
52
PD70320
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
READY Hold Time
t
HCRY0
n = 2
1T
ns
(from MREQ
, IOSTB
)
t
HCRY
n
3
(n 1)T
ns
t
HCRY1
n
3
(n 2)T
ns
HLDRQ Setup Time (to CLKOUT
)
t
SHQK
30
ns
HLDAK
Delay Time from CLKOUT
t
DKHA
80
ns
HLDAK
Delay Time from Bus Float
t
CFHA
1T 50
ns
Bus Output Delay Time from HLDAK
t
DHAC
1T 50
ns
HLDAK
Delay Time from HLDRQ
t
DHQHA
3T + 160
ns
Bus Output Delay Time from HLDRQ
t
DHQC
3T + 30
ns
HLDRQ Low-Level Width
t
WHQL
1.5T
ns
HLDAK Low-Level Width
t
WHAL
1T
ns
INT, DMARQ Setup Time (to CLKOUT
) t
SIQK
30
ns
INT, DMARQ High-/Low-Level Width
t
WIQH
, t
WIQL
8T
ns
POLL Setup Time (to CLKOUT
)
t
SPLK
30
ns
NMI High-/Low-Level Width
t
WNIH
, t
WNIL
5
s
CTS Low-Level Width
t
WCTL
2T
ns
INT Setup Time (to CLKOUT
)
t
SIRK
30
ns
INTAK
Delay Time from CLKOUT
t
DKIA
80
ns
INT Hold Time (from INTAK
)
t
HIAIQ
0
ns
INTAK Low-Level Width
t
WIAL
2T 30
ns
INTAK High-Level Width
t
WIAH
1T 30
ns
Data Delay Time from INTAK
t
DIAD
2T 130
ns
Data Hold Time (from INTAK
)
t
HIAD
0
0.5T
ns
SCK0 Cycle Time
t
CYTK
1000
ns
SCK0 High-/Low-Level Width
t
WSTH
, t
WSTL
450
ns
TxD Delay Time from SCK0
t
DTKD
210
ns
TxD Hold Time (from SCK0
)
t
HTKD
20
ns
CTS0 Cycle Time
t
CYRK
1000
ns
CTS0 High-/Low-Level Width
t
WSRH
, t
WSRL
420
ns
RxD Setup/Hold Time (to/from CTS0
)
t
SRDK
, t
HKRD
80
ns
Remark
n indicates the number of wait states. No wait is "n = 0".
53
PD70320
COMPARATOR CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= +5.0 V
10%)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Comparator Accuracy
V
ACOMP
100
mV
Threshold Voltage
V
TH
0
V
DD
+ 0.1
V
Compare Time
t
COMP
64
65
t
CYK
PT Input Voltage
V
IPT
0
V
DD
V
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA HOLDING CHARACTERISTICS
(T
A
= 40 to +85
C)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Data Hold Supply Voltage
V
DDDR
2.5
5.5
V
V
DD
Rise/Fall Time
t
RVD
, t
FVD
200
s
DATA HOLDING TIMING
90%
10%
V
DDDR
t
FVD
t
RVD
AC TEST INPUT WAVEFORM (Except RESET, NMI, X1 and X2)
2.2 V
0.8 V
t
IF
Test Points
2.2 V
0.8 V
t
IR
AC TEST INPUT WAVEFORM (RESET, NMI, X1 and X2)
0.8 V
DD
0.8 V
t
IFS
Test Points
0.8 V
DD
0.8 V
t
IRS
AC TEST OUTPUT TEST POINTS
Output load condition: 100 pF
2.2 V
0.8 V
Test Points
2.2 V
0.8 V
54
PD70320
CLOCK TIMING
t
CYX
t
WXH
t
WXL
t
XF
t
XR
0.8 V
DD
0.8 V
X1
t
CYK
t
WKH
t
WKL
t
KF
t
KR
2.2 V
0.8 V
CLKOUT
POLL INPUT TIMING
t
SPLK
t
SPLK
CLKOUT
POLL
CTS0 AND CTS1 INPUT TIMING
t
WCTL
CTS0 and CTS1
55
PD70320
INTERRUPT INPUT/DMA INPUT TIMING
CLKOUT
NMI
Note
t
SIQK
t
WNIH
t
WIQH
t
WNIL
t
WIQL
t
SIQK
Note INTP0 to INTP2, DMARQ0 to DMARQ1
RESET INPUT TIMING
When STOP mode is released/at power-on reset:
t
WRSL1
CLKOUT
Note
RESET
Note CLKOUT signal is output after CLKOUT output is set.
When system is reset:
t
WRSL2
CLKOUT
Note
RESET
Note CLKOUT output is set to input port by RESET input.
56
PD70320
READY TIMING
When 2 wait states are inserted:
When (n 2) extra wait states are inserted [n
3]:
Notes 1. In case of memory cycle
2. In case of I/O cycle
t
HCRY0
t
SCRY0
T1
TAW
TAW
T2
MREQ
Note 1
,
IOSTB
Note 2
READY
T1
TAW
TAW
T2
t
HCRY1
t
SCRY
t
HCRY
TW
(n 2)
READY
t
SCRY0
MREQ
Note 1
,
IOSTB
Note 2
57
PD70320
SERIAL OPERATION
When transmitting data in I/O interface mode
t
CYTK
t
WSTL
t
WSTH
t
DTKD
t
HTKD
SCK0
TxD
When receiving data in I/O interface mode
t
CYRK
t
WSRL
t
WSRH
t
SRDK
CTS0
RxD
t
HKRD
58
PD70320
READ
OPERATION
t
CYK
t
DKA
t
DADR
t
HMA
t
HMDR
t
DAMR
t
DMRD
t
WMRL
t
RVC
t
DMRMS
t
DMSD
t
DAMS
t
WMSL
CLKOUT
A19 to A0
D7 to D0
R/ W
MREQ
MSTB
IOSTB
REFRQ
DMAAK1 to
DMAAK0
59
PD70320
WRITE OPERATION
t
CYK
t
DKA
t
DADW
t
HMA
t
HMDW
t
DAMR
t
WMRL
t
RVC
t
DMRMS
t
DAMS
t
WMSL
CLKOUT
A19 to A0
D7 to D0
R/ W
MREQ
MSTB
IOSTB
REFRQ
DMAAK1 to
DMAAK0
t
SDM
60
PD70320
I/O READ TIMING
t
CYK
t
DKA
t
DADR
t
HISA
t
HISDR
t
DISD
CLKOUT
A19 to A0
D7 to D0
R/ W
MREQ
MSTB
IOSTB
REFRQ
DMAAK1 to
DMAAK0
t
DAIS
t
WISL
t
RVC
61
PD70320
I/O WRITE TIMING
t
CYK
t
DKA
t
DADW
t
HISA
t
HISDW
CLKOUT
A19 to A0
D7 to D0
R/ W
MREQ
MSTB
IOSTB
REFRQ
DMAAK1 to
DMAAK0
t
SDIS
t
DAIS
t
WISL
t
RVC
62
PD70320
DMA (I/O
MEMORY) TIMING
t
CYK
t
DKA
t
HMA
t
DAMR
t
WMRL
t
RVC
t
DMRMS
t
DAMS
t
WMSL
CLKOUT
A19 to A0
D7 to D0
R/ W
MREQ
MSTB
IOSTB
DMAAK1 to
DMAAK0
t
SDADQ
t
HDADQ
t
WDMRL
t
DDATC
t
WTCL
DMARQ1 to
DMARQ0
TC1 to TC0
63
PD70320
DMA (MEMORY
I/O) TIMING
t
CYK
t
DKA
t
HMA
t
DAMR
t
WMRL
t
RVC
t
DAMS
t
WMSL
CLKOUT
A19 to A0
D7 to D0
R/ W
MREQ
MSTB
IOSTB
DMAAK1 to
DMAAK0
t
SDADQ
t
HDADQ
t
WDMWL
t
DDATC
t
WTCL
DMARQ1 to
DMARQ0
TC1 to TC0
64
PD70320
REFRESH TIMING
t
CYK
t
DKA
CLKOUT
A19 to A0
D7 to D0
R/ W
MREQ
MSTB
IOSTB
REFRQ
DMAAK1 to
DMAAK0
t
RVC
t
HRFA
t
DARF
t
WRFL
65
PD70320
HOLD REQUEST/ACKNOWLEDGE TIMING
Normal mode
t
SHQK
t
SHQK
t
DKHA
t
WHQL
t
CFHA
t
WHAL
t
DHQHA
t
DHAC
CLKOUT
HLDRQ
Note
HLDAK
Releasing HOLD mode at refreshing time
Note A19 to A0, D7 to D0, MREQ, MSTB, IOSTB, R/W
EXTERNAL INTERRUPT REQUEST/ACKNOWLEDGE TIMING
t
SHQK
t
DKHA
t
WHQL
t
DHQC
CLKOUT
HLDRQ
Note
HLDAK
CLKOUT
INT
D0 to D7
t
SIRK
t
HIAIQ
t
DKIA
t
WIAL
t
RVC
t
WIAH
t
DIAD
t
HIAD
t
RVC
MREQ
IOSTB
INTAK
66
PD70320
4. CHARACTERISTIC CURVES
0
2
4
6
8
10
12
0
20
40
60
80
100
120
140
Supply Current I
DD1
(mA)
Supply Current I
DD2
(mA)
System Clock Frequency f
CLK
(MHz)
System Clock Frequency f
CLK
(MHz)
I
DD1
vs f
CLK
I
DD2
vs f
CLK
(T
A
= 25
C, V
DD
= 5 V)
(T
A
= 25
C, V
DD
= 5 V)
0
2
4
6
8
10
12
0
10
20
30
40
50
60
70
67
PD70320
0
4
5
6
0
20
40
60
80
100
120
0
4
5
6
0
10
20
30
40
50
Supply Current I
DD1
(mA)
Supply Current I
DD2
(mA)
Supply Voltage V
DD
(V)
Supply Voltage V
DD
(V)
f
CLK
= 8 MHz
f
CLK
= 8 MHz
f
CLK
= 5 MHz
f
CLK
= 5 MHz
f
CLK
= 2 MHz
f
CLK
= 2 MHz
f
CLK
= 1 MHz
f
CLK
= 1 MHz
f
CLK
= 0.5 MHz
f
CLK
= 0.5 MHz
I
DD1
vs V
DD
(T
A
= 25
C)
I
DD2
vs V
DD
(T
A
= 25
C)
68
PD70320
0
0.2
0.4
0.6
0
1
2
3
0
0.2
0.4
0.6
0
2
4
6
Output Current I
OH
(mA)
Output Current I
OL
(mA)
Output Voltage V
DD
V
OH
(V)
Output Voltage V
OL
(V)
I
OH
vs V
OH
(T
A
= 25
C, V
DD
= 5 V)
I
OL
vs V
OL
(T
A
= 25
C, V
DD
= 5 V)
69
PD70320
5. PACKAGE DRAWINGS
84 PIN PLASTIC QFJ ( 1150 mil)
P84L-50A3-2
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
30.2
0.2
29.28
0.6
4.4
0.2
2.8
0.2
29.28
1.189
0.008
0.076
0.024
0.110
0.035 MIN.
1.153
NOTE
M
N
0.12
0.40
0.10
3.4
0.9 MIN.
0.005
0.016
+0.004
0.005
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
0.134
0.173
1.153
1.27 (T.P.)
0.050 (T.P.)
P
28.20
0.20
1.110
1.189
0.008
30.2
0.2
1.94
0.15
Q
0.15
0.006
T
R 0.8
R 0.031
+0.009
0.008
E
U
0.20
0.008
+0.10
0.05
+0.004
0.002
+0.009
0.008
+0.007
0.006
+0.009
0.008
C
A
84
B
1
T
N
Q
M
K
I
M
U
H
E
G
J
F
D
70
PD70320
94 PIN PLASTIC QFP ( 20)
ITEM
MILLIMETERS
INCHES
F
1
F
2
I
1.6
0.8
0.15
Q
0.063
0.031
0.006
S94GJ-80-5BG-3
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
C
20.0
0.2
0.787
M
0.15
0.006
0.1
0.1
0.004
0.004
+0.004
0.003
+0.009
0.008
A
23.2
0.4
0.913
H
0.35
0.10
0.014+0.004
0.005
L
0.8
0.2
0.031+0.009
0.008
N
0.10
0.004
P
3.7
0.146
S
4.0 MAX.
0.158 MAX.
+0.10
0.05
B
20.0
0.2
0.787+0.009
0.008
+0.017
0.016
J
0.8 (T.P.)
0.031 (T.P.)
R
5
5
5
5
D
23.2
0.4
0.913+0.017
0.016
G
1
G
2
1.6
0.8
0.063
0.031
K
1.6
0.2
0.063
0.008
A
B
G
1
H
I
J
C
D
P
N
K
L
M
detail of lead end
F
2
F
1
M
71
72
47
94
24
23
48
1
G
2
S
Q
R
71
PD70320
6. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met when soldering this product.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(C10535E)
.
Please consult with our sales office when using other soldering process or under different soldering conditions.
Table 6-1. Surface Mount Type Soldering Conditions
(1)
PD70320L
: 84-pin plastic QFJ (1150
1150 mils)
PD70320L-8 : 84-pin plastic QFJ (1150
1150 mils)
Soldering Process
Soldering Conditions
Symbol
VPS
Package peak temperature: 215
C, Reflow time: 40 seconds or less,
VP15-162-1
Number of reflow processes: 1
Exposure limit: 2 days
Note
(16 hours pre-baking is required at 125
C afterwards)
Partial heating
Pin temperature: 300
C or below,
--
method
Flow time: 3 seconds or less (per side of device)
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25
C and relative
humidity at 65% or less.
(2)
PD70320GJ-5BG
: 94-pin plastic QFP (20
20 mm)
PD70320GJ-8-5BG : 94-pin plastic QFP (20
20 mm)
Soldering Process
Soldering Conditions
Symbol
Infrared ray reflow
Package peak temperature: 235
C, Reflow time: 30 seconds or less,
IR35-367-3
Number of reflow processes: 3 or less
Exposure limit: 7 days
Note
(36 hours pre-baking is required at 125
C afterwards)
VPS
Package peak temperature: 215
C, Reflow time: 40 seconds or less,
VP15-367-3
Number of reflow processes: 3 or less
Exposure limit: 7 days
Note
(36 hours pre-baking is required at 125
C afterwards)
Wave soldering
Package peak temperature: 260
C, Reflow time: 10 seconds or less,
WS60-367-1
Number of reflow processes: 1
Pre-heating temperature: 120
C max. (package surface temperature)
Exposure limit: 7 days
Note
(36 hours pre-baking is required at 125
C afterwards)
Partial heating
Pin temperature: 300
C or below,
--
method
Flow time: 3 seconds or less (per side of device)
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25
C and relative
humidity at 65% or less.
Caution
Use of more than one soldering process should be avoided (except for partial heating method).
72
PD70320
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
73
PD70320
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J97. 8
2
PD70320
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
Related documents
V25, V35 User's Manual -- Hardware
IEM-1220
V25, V35 Family User's Manual -- Instructions
U12120J (Japanese version)
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V20, V25, V30, and V35 are trademarks of NEC Corporation.
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