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MOS INTEGRATED CIRCUIT

PD720114

ECOUSB

Series

USB 2.0 HUB CONTROLLER

Document No. S17462EJ2V0DS00 (2nd edition)
Date Published May 2005 NS CP (K)
Printed in Japan

DATA SHEET

2005

The

PD720114 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision

2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports.
The

PD720114 works backward compatible either when any one of the downstream ports is connected to a USB 1.1

compliant device, or when the upstream port is connected to a USB 1.1 compliant host.

Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing.

PD720114 User's Manual: S17463E

FEATURES

· Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
· High-speed or full-speed packet protocol sequencer for Endpoint 0/1
· 4 (Max.) downstream facing ports
· All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5

Mbps) transaction.

· Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when

Hub controller is working in high-speed mode.

· One Transaction Translator per Hub and supports four non-periodic buffers
· Supports self-powered and bus-powered mode
· Supports individual or global over-current detection and individual or ganged power control
· Supports downstream port status with LED
· Supports non-removable devices by I/O pin configuration
· Support Energy Star for PC peripheral system
· On chip Rpu, Rpd resistors and regulator (for core logic)
· Low power consumption
· Use 30 MHz X'tal
· 3.3 V power supply

Data Sheet S17462EJ2V0DS

PD720114

APLL

: Generates all clocks of Hub.

ALL_TT

: Translates the high-speed transactions (split transactions) for full/low-speed device

to full/low-speed transactions. ALL_TT buffers the data transfer from either
upstream or downstream direction. For OUT transaction, ALL_TT buffers data from
upstream port and sends it out to the downstream facing ports after speed
conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers
data from downstream ports and sends it out to the upstream facing ports after
speed conversion from full/low-speed to high-speed.

CDR

: Data & clock recovery circuit

DPC

: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and

Resume

DP(n)_PHY

: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and

low-speed (1.5 Mbps) transaction

EP0

: Endpoint 0 controller

EP1

: Endpoint 1 controller

F_TIM (Frame Timer)

: Manages hub's synchronization by using micro-SOF which is received at upstream

port, and generates SOF packet when full/low-speed device is attached to
downstream facing port.

FS_REP

: Full/low-speed repeater is enabled when the

PD720114 are worked at full-speed

mode

OSB :

Oscillator

Block

2.5V REG

: On chip 2.5V regulator

SERDES :

Serializer

and

Deserializer

SIE_2H

: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer.

UP_PHY

: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)

transaction

UPC

: Upstream Port Controller handles Suspend and Resume

Data Sheet S17462EJ2V0DS

PD720114

1. PIN INFORMATION

Pin Name

I/O

Buffer Type

Active

Level

Function

2.5 V input

30MHz Crystal oscillator in

2.5 V output

30MHz Crystal oscillator out

SYSRSTB

3.3 V Schmitt input

Low

Asynchronous chip hardware reset

DP(4:1) I/O

USB

+ signal I/O

USB's downstream facing port D

+ signal

DM(4:1) I/O

USB

- signal I/O

USB's downstream facing port D

- signal

DPU I/O

USB

+ signal I/O

USB's upstream facing port D

+ signal

DMU I/O

USB

- signal I/O

USB's upstream facing port D

- signal

BUS_B

3.3 V Schmitt input

Power mode select

RREF A

(O)

Analog

Reference resistor connection

CSB1

5 V tolerant Schmitt input

Low

Port's over-current status input.

CSB(4:2)

3.3 V Schmitt input

Low

Port's over-current status input

PPB(4:1)

I/O

3.3 V output / input

Low

Port's power supply control output or hub
configuration input

VBUSM

5 V tolerant Schmitt input

Upstream V

BUS

monitor

AMBER

I/O

3.3V output / input

Amber colored LED control output or port
indicator select

GREEN

3.3V output

Green colored LED control output or port
indicator select

LED(4:1)

I/O

3.3V output / input

Low

LED indicator output show downstream port
status or Removable/Non-removable select

TEST

3.3 V Schmitt input

Test signal

DD25OUT

On chip 2.5 V regulator output, it must have a
4.7

F (or greater) capacitor to V

SSREG

DD33

3.3 V V

DD33REG

3.3 V V

for on chip 2.5V regulator input, it must

have a 4.7

F ( or greater) capacitor to V

SSREG

DD25

2.5 V V

for analog circuit

SSREG

On chip 2.5 V regulator V

for analog circuit

(R)

for reference resistor, Connect to AV

Remark "5 V tolerant" means that the buffer is 3 V buffer with 5 V tolerant circuit.

Data Sheet S17462EJ2V0DS

PD720114

2.2 Terminology

Terms Used in Absolute Maximum Ratings

Parameter Symbol

Meaning

Power supply voltage

DD33

Indicates voltage range within which damage or reduced reliability will not
result when power is applied to a V

pin.

Input voltage

Indicates voltage range within which damage or reduced reliability will not
result when power is applied to an input pin.

Output voltage

Indicates voltage range within which damage or reduced reliability will not
result when power is applied to an output pin.

Output current

Indicates absolute tolerance values for DC current to prevent damage or
reduced reliability when current flows out of or into an output pin.

Operating temperature

Indicates the ambient temperature range for normal logic operations.

Storage temperature

stg

Indicates the element temperature range within which damage or reduced
reliability will not result while no voltage or current are applied to the device.

Terms Used in Recommended Operating Range

Parameter Symbol

Meaning

Power supply voltage

DD33

Indicates the voltage range for normal logic operations to occur when V

= 0

High-level input voltage

Indicates the voltage, applied to the input pins of the device, which indicates
the high level state for normal operation of the input buffer.

* If a voltage that is equal to or greater than the "MIN." value is applied, the

input voltage is guaranteed as high level voltage.

Low-level input voltage

Indicates the voltage, applied to the input pins of the device, which indicates
the low level state for normal operation of the input buffer.

* If a voltage that is equal to or less than the "MAX." value is applied, the

input voltage is guaranteed as low level voltage.

Hysteresis voltage

Indicates the differential between the positive trigger voltage and the negative
trigger voltage.

Input rise time

Indicates allowable input rise time to input signal transition time from
0.1

× V

to 0.9

× V

Input fall time

Indicates allowable input fall time to input signal transition time from
0.9

× V

to 0.1

× V

Data Sheet S17462EJ2V0DS

PD720114

Terms Used in DC Characteristics

Parameter Symbol

Meaning

Off-state output leakage current

Indicates the current that flows into a 3-state output pin when it is in a high-
impedance state and a voltage is applied to the pin.

Output short circuit current

Indicates the current that flows from an output pin when it is shorted to GND
pins.

Input leakage current

Indicates the current that flows into an input pin when a voltage is applied to
the pin.

Low-level output current

Indicates the current that flows to the output pins when the rated low-level
output voltage is being applied.

High-level output current

Indicates the current that can flow out of an output pin in the high-level state
without reducing the output voltage below the specified V

. (A negative

current indicates current flowing out of the pin.)

2.3 Electrical

Specifications

Absolute Maximum Ratings

Parameter Symbol

Condition

Rating Unit

Power supply voltage

DD33

-0.5 to +4.6 V

Input/output voltage

3.3 V input/output voltage

3.0 V

DD33

3.6 V

< V

DD33

+ 1.0 V

-0.5 to +4.6 V

5 V input/out voltage

3.0 V

DD33

3.6 V

< V

DD33

+ 3.0 V

-0.5 to +6.6 V

Output current

= 3 mA

= 6 mA

= 12 mA

10
20
40

mA
mA
mA

Operating temperature

+70

°C

Storage temperature

stg

-65 to +150

°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameters. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent the
quality assurance range during normal operation.

Data Sheet S17462EJ2V0DS

PD720114

DC Characteristics

Parameter Symbol

Condition

MIN.

MAX.

Unit

Off-state output leakage current

= V

DD33,

DD25

or V

±10

Output short circuit current

Note

-250 mA

Low-level output current

3.3 V low-level output current

= 0.4 V

3.3 V low-level output current

= 0.4 V

5.0 V low-level output current

= 0.4 V

High-level output current

3.3 V high-level output current

= 2.4 V

-3 mA

3.3 V high-level output current

= 2.4 V

-6 mA

5.0 V high-level output current

= 2.4 V

-2 mA

Input leakage current

3.3 V buffer

= V

or V

±10

5.0 V buffer

= V

or V

±10

Note The output short circuit time is measured at one second or less and is tested with only one pin on the LSI.

Data Sheet S17462EJ2V0DS

PD720114

USB Interface Block

Parameter Symbol

Conditions

MIN

MAX

Unit

Output pin impedance

HSDRV

Includes

resistor

40.5

49.5

Termination voltage for upstream facing
port pullup (full-speed)

TERM

3.0

3.6

Input Levels for Low-/full-speed:

High-level input voltage (drive)

2.0

High-level input voltage (floating)

IHZ

2.7 3.6 V

Low-level input voltage

0.8 V

Differential input sensitivity

(D+) - (D-) 0.2

Differential common mode range

Includes

range

0.8

2.5

Output Levels for Low-/full-speed:

High-level output voltage

of 14.25 k

to GND

2.8

3.6

Low-level output voltage

of 1.425 k

to 3.6 V

0.0

0.3

SE1 V

OSE1

0.8

Output signal crossover point voltage

CRS

1.3

2.0 V

Input Levels for High-speed:

High-speed squelch detection threshold
(differential signal)

HSSQ

100

150 mV

High-speed disconnect detection
threshold (differential signal)

HSDSC

525

625 mV

High-speed data signaling common
mode voltage range

HSCM

-50

+500 mV

High-speed differential input signaling
levels

See Figure 2-4.

Output Levels for High-speed:

High-speed idle state

HSOI

-10.0

+10 mV

High-speed data signaling high

HSOH

360

440 mV

High-speed data signaling low

HSOL

-10.0

+10 mV

Chirp J level (different signal)

CHIRPJ

700

1100 mV

Chirp K level (different signal)

CHIRPK

-900

-500 mV

Data Sheet S17462EJ2V0DS

PD720114

Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed

4.6

-1.0

Input Voltage Range (Volts)

Differential Input Voltage Range

Differential Output

Crossover

Voltage Range

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

Figure 2-2. Full-speed Buffer V

Characteristics for High-speed Capable Transceiver

Max.

Min.

0.3

OUT

(V)

OUT

(mA)

2.3

3.3

0.8

1.3

1.8

2.8

Figure 2-3. Full-speed Buffer V

Characteristics for High-speed Capable Transceiver

Max.

Min.

0.5

1.5

2.5

OUT

(V)

OUT

(mA)

Data Sheet S17462EJ2V0DS

PD720114

Power Consumption

Parameter Symbol

Condition

TYP. Unit

Power Consumption

W-0

The power consumption under the state without suspend.
All the ports do not connect to any function.

Hub controller is operating at full-speed mode.
Hub controller is operating at high-speed mode.

31
86

mA
mA

W-2

The power consumption under the state without suspend.
The number of active ports is 2.

Hub controller is operating at full-speed mode.
Hub controller is operating at high-speed mode.

120

mA
mA

W-3

The power consumption under the state without suspend.
The number of active ports is 3.

Hub controller is operating at full-speed mode.
Hub controller is operating at high-speed mode.

134

mA
mA

W-4

The power consumption under the state without suspend.
The number of active ports is 4.

Hub controller is operating at full-speed mode.
Hub controller is operating at high-speed mode.

149

mA
mA

W_S

The power consumption under suspend state.

220

Remark The power consumption depends on the number of ports available and actively operating. Ports

available but inactive or unplugged do not add to the power consumption. If the

PD720114 is locally

powered and the upstream facing port is unplugged,

PD720114 goes into suspend state and

downstream facing port Vbus goes down.

Data Sheet S17462EJ2V0DS

PD720114

Over-current Response Timing

Parameter Symbol

Condition

MIN.

TYP.

MAX.

Unit

Over-current response time from CSB
low to PPB high (Figure 2-7)

Figure 2-7. Over-current Response Timing

CSB(4:1)

PPB(4:1)

Figure 2-8. CSB/PPB Timing

Bus Reset

Port power

supply ON

DEVICE

connection

inrush current

Output

cut-off

Overcurrent

generation

Hub power supply

Up port D+ line

PPB pin output

CSB pin input

CSB pin opration region

Bus power: Up port connection
Self power: Power supply ON

CSB active

period

CSB detection

delay time

4ms

Remark The active period of the CSB pin is in effect only when the PPB pin is ON.

There is a delay time of approximately 4 ms duration at the CSB pin.

Data Sheet S17462EJ2V0DS

PD720114

USB Interface Block

(1/4)

Parameter Symbol

Conditions

MIN.

MAX.

Unit

Low-speed Electrical Characteristics

Rise time (10% to 90%)

= 200 pF to 600 pF

300

Fall time (90% to 10%)

= 200 pF to 600 pF

300

Differential rise and fall time matching

LRFM

)

Note

125

Low-speed data rate

LDRATHS

Average bit rate

1.49925

1.50075

Mbps

Downstream facing port source jitter total
(including frequency tolerance) (Figure
2-13):

To next transition

For paired transitions

DDJ1

DDJ2

-25
-14

+25
+14

ns
ns

Downstream facing port differential
receiver jitter total (including frequency
tolerance) (Figure 2-15):

To next transition

For paired transitions

UJR1

UJR2

-152
-200

+152
+200

ns
ns

Source SE0 interval of EOP (Figure 2-14)

LEOPT

1.25

1.5

Receiver SE0 interval of EOP (Figure 2-14)

LEOPR

670

Width of SE0 interval during differential
transition

LST

210

Hub differential data delay (Figure 2-11)

LHDD

300 ns

Hub differential driver jitter (including cable)
(Figure 2-11):

Downstream facing port
To next transition
For paired transitions

Upstream facing port
To next transition
For paired transitions

LDHJ1

LDHJ2

LUHJ1

LUHJ2

-45
-15

-45
-45

+45
+15

+45
+45

ns
ns

Data bit width distortion after SOP (Figure
2-11)

LSOP

-60

+60 ns

Hub EOP delay relative to t

HDD

(Figure

2-12)

LEOPD

200 ns

Hub EOP output width skew (Figure 2-12)

LHESK

-300

+300 ns

Full-speed Electrical Characteristics

Rise time (10% to 90%)

= 50 pF,

= 36

4 20

Fall time (90% to 10%)

= 50 pF,

= 36

4 20

Differential rise and fall time matching

FRFM

) 90

111.11

Full-speed data rate

FDRATHS

Average bit rate

11.9940

12.0060

Mbps

Frame interval

FRAME

0.9995 1.0005 ms

Note Excluding the first transition from the Idle state.

Data Sheet S17462EJ2V0DS

PD720114

(2/4)

Parameter Symbol

Conditions

MIN.

MAX.

Unit

Full-speed Electrical Characteristics (Continued)

Consecutive frame interval jitter

RFI

No clock adjustment

Source jitter total (including frequency
tolerance) (Figure 2-13):
To next transition
For paired transitions

DJ1

DJ2

Note

-3.5
-4.0

+3.5
+4.0

ns
ns

Source jitter for differential transition to
SE0 transition (Figure 2-14)

FDEOP

-2

+5 ns

Receiver jitter (Figure 2-15):
To Next Transition
For

Paired

Transitions

JR1

JR2

-18.5

-9

+18.5

ns
ns

Source SE0 interval of EOP (Figure 2-14)

FEOPT

160

175 ns

Receiver SE0 interval of EOP (Figure 2-14)

FEOPR

Width of SE0 interval during differential
transition

FST

14 ns

Hub differential data delay (Figure 2-11)

(with cable)
(without cable)

HDD1

HDD2

70
44

ns
ns

Hub differential driver jitter (including cable)
(Figure 2-11):
To next transition
For paired transitions

HDJ1

HDJ2

-3
-1

+3
+1

ns
ns

Data bit width distortion after SOP (Figure
2-11)

FSOP

-5

+5 ns

Hub EOP delay relative to t

HDD

(Figure

2-12)

FEOPD

Hub EOP output width skew (Figure 2-12)

FHESK

-15

+15 ns

High-speed Electrical Characteristics

Rise time (10% to 90%)

HSR

500

Fall time (90% to 10%)

HSF

500

Driver waveform

See Figure 2-9.

High-speed data rate

HSDRAT

479.760 480.240 Mbps

Microframe interval

HSFRAM

124.9375 125.0625

Consecutive microframe interval difference

HSRFI

high-

speed

Bit

times

Data source jitter

See Figure 2-9.

Receiver jitter tolerance

See Figure 2-4.

Hub data delay (without cable)

HSHDD

high-

speed

+4 ns

Bit

times

Hub data jitter

See Figure 2-4, Figure 2-9.

Hub delay variation range

HSHDV

high-

speed

Bit

times

Note Excluding the first transition from the Idle state.

Data Sheet S17462EJ2V0DS

PD720114

(3/4)

Parameter Symbol

Conditions

MIN.

MAX.

Unit

Hub Event Timings

Time to detect a downstream facing port
connect event (Figure 2-17):
Awake

hub

Suspended

hub

DCNN

2.5
2.5

2000

12000

Time to detect a disconnect event at a
hub's downstream facing port (Figure 2-16)

DDIS

2.0

2.5

Duration of driving resume to a
downstream port (only from a controlling
hub)

DRSMDN

Time from detecting downstream resume
to rebroadcast

URSM

1.0 ms

Duration of driving reset to a downstream
facing port (Figure 2-18)

DRST

Only for a SetPortFeature
(PORT_RESET) request

10 20

Time to detect a long K from upstream

URLK

2.5

100

Time to detect a long SE0 from upstream

URLSE0

2.5

10000

Duration of repeating SE0 upstream (for
low-/full-speed repeater)

URPSE0

23 FS

Bit

times

Inter-packet delay (for high-speed) of
packets traveling in same direction

HSIPDSD

Bit

times

Inter-packet delay (for high-speed) of
packets traveling in opposite direction

HSIPDOD

Bit

times

Inter-packet delay for device/root hub
response with detachable cable for high-
speed

HSRSPIPD1

192

Bit

times

Time of which a Chirp J or Chirp K must be
continuously detected (filtered) by hub or
device during Reset handshake

FILT

2.5

Time after end of device Chirp K by which
hub must start driving first Chirp K in the
hub's chirp sequence

WTDCH

100

Time for which each individual Chirp J or
Chirp K in the chirp sequence is driven
downstream by hub during reset

DCHBIT

Time before end of reset by which a hub
must end its downstream chirp sequence

DCHSE0

100

500

Time from internal power good to device
pulling D

+ beyond V

IHZ

(Figure 2-18)

SIGATT

100 ms

Debounce interval provided by USB
system software after attach (Figure 2-18)

ATTDB

100 ms

Maximum duration of suspend averaging
interval

SUSAVGI

Period of idle bus before device can initiate
resume

WTRSM

Duration of driving resume upstream

DRSMUP

Data Sheet S17462EJ2V0DS

PD720114

(4/4)

Parameter Symbol

Conditions

MIN.

MAX.

Unit

Hub Event Timings (Continued)

Resume recovery time

RSMRCY

Remote-wakeup

enabled

Time to detect a reset from upstream for
non high-speed capable devices

DETRST

2.5

10000

Reset recovery time (Figure 2-18)

RSTRCY

Inter-packet delay for full-speed

IPD

Bit

times

Inter-packet delay for device response with
detachable cable for full-speed

RSPIPD1

6.5

Bit

times

SetAddress() completion time

DSETADDR

Time to complete standard request with no
data

DRQCMPLTND

Time to deliver first and subsequent
(except last) data for standard request

DRETDATA1

500

Time to deliver last data for standard
request

DRETDATAN

Time for which a suspended hub will see a
continuous SE0 on upstream before
beginning the high-speed detection
handshake

FILTSE0

2.5

Time a hub operating in non-suspended
full-speed will wait after start of SE0 on
upstream before beginning the high-speed
detection handshake

WTRSTFS

2.5

3000

Time a hub operating in high-speed will
wait after start of SE0 on upstream before
reverting to full-speed

WTREV

3.0

3.125 ms

Time a hub will wait after reverting to full-
speed before sampling the bus state on
upstream and beginning the high-speed
will wait after start of SE0 on upstream
before reverting to full-speed

WTRSTHS

100

875

Minimum duration of a Chirp K on
upstream from a hub within the reset
protocol

UCH

1.0

Time after start of SE0 on upstream by
which a hub will complete its Chirp K within
the reset protocol

UCHEND

7.0

Time between detection of downstream
chip and entering high-speed state

WTHS

500

Time after end of upstream Chirp at which
hub reverts to full-speed default state if no
downstream Chirp is detected

WTFS

1.0

2.5 ms

Data Sheet S17462EJ2V0DS

PD720114

Timing Diagram

Figure 2-11. Hub Differential Delay, Differential Jitter, and SOP Distortion

C. Upstream Hub Delay with or without Cable

D. Measurement Points

50% Point of

Initial Swing

50% Point of

Initial Swing

Upstream

End of

Cable

Upstream

Port of Hub

Downstream

Port of Hub

Downstream

Port of Hub

Downstream

Port of Hub

Upstream Port

End of Cable

A. Downstream Hub Delay with Cable

B. Downstream Hub Delay without Cable

Hub Delay

Downstream

HDD1

Hub Delay

Upstream

HDD1

HDD2

Crossover

Point

Crossover

Point

Crossover

Point

Hub Differential Jitter:
t

HDJ1

= t

HDDx

(J)

HDDx

(K) or t

HDDx

(K)

HDDx

(J) Consecutive Transitions

HDJ2

= t

HDDx

(J)

HDDx

(J) or t

HDDx

(K)

HDDx

(K) Paired Transitions

Bit after SOP Width Distortion (same as data jitter for SOP and next J transition):
t

FSOP

= t

HDDx

(next J)

HDDx

(SOP)

Low-speed timings are determined in the same way for:
t

LHDD

, t

LDHJ1

, t

LDJH2

, t

LUHJ1

, t

LUJH2

, and t

LSOP

Host or

Hub

Function

Upstream end of cable

Upstream port

Downstream port

Downstream signaling

Upstream signaling

Plug

Receptacle

Hub Delay

Downstream

HDD2

Data Sheet S17462EJ2V0DS

PD720114

Figure 2-12. Hub EOP Delay and EOP Skew

EOP-

EOP+

EOP-

EOP+

EOP-

EOP+

C. Upstream EOP Delay with or without Cable

Upstream

End of

Cable

Upstream

Port of Hub

Downstream

Port of Hub

Downstream

Port of Hub

Downstream

Port of Hub

Upstream Port

End of Cable

A. Downstream EOP Delay with Cable

B. Downstream EOP Delay without Cable

50% Point of

Initial Swing

Crossover

Point

Extended

Crossover

Point

Extended

Crossover

Point

Extended

EOP Delay:
t

FEOPD

= t

EOPy

HDDx

EOPy

means that this equation applies to t

EOP-

and t

EOP+

)

EOP Skew:
t

FHESK

= t

EOP+

EOP-

Low-speed timings are determined in the same way for:
t

LEOPD

and t

LHESK

Data Sheet S17462EJ2V0DS

PD720114

Figure 2-13. USB Differential Data Jitter for Low-/full-speed

PERIOD

Differential
Data Lines

Crossover

Points

Consecutive

Transitions

PERIOD

xDJ1

Paired

Transitions

PERIOD

xDJ2

Figure 2-14. USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed

PERIOD

Differential
Data Lines

Crossover

Point

Crossover

Point Extended

Source EOP Width: t

FEOPT

Receiver EOP Width: t

FEOPR

LEOPT

LEOPR

Diff. Data-to-

SE0 Skew

PERIOD

xDEOP

Figure 2-15. USB Receiver Jitter Tolerance for Low-/full-speed

Differential
Data Lines

PERIOD

xJR

xJR1

xJR2

Consecutive

Transitions

PERIOD

xJR1

Paired

Transitions

PERIOD

xJR2

Data Sheet S17462EJ2V0DS

PD720114

4. RECOMMENDED SOLDERING CONDITIONS

The

PD720114 should be soldered and mounted under the following recommended conditions.

For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales

representative.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

PD720114GA-9EU-A:

48-pin plastic TQFP (Fine pitch) (7

× 7)

Soldering Method

Soldering Conditions

Symbol

Infrared reflow

Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),

Count: Three times or less

Exposure limit: 3 days

Note

(after that, prebake at 125°C for 10 hours)

Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended.

IR60-103-3

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Data Sheet S17462EJ2V0DS

PD720114

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

(MAX) and V

(MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MAX) and

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

PD720114

ECOUSB is a trademark of NEC Electronics Corporation.

The information in this document is current as of May 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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(Note)

M8E 02. 11-1

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).

Computers, office equipment, communications equipment, test and measurement equipment, audio
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Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
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"Standard":

"Special":

"Specific":

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