DESCRIPTION
PD75108A is a 4-bit single-chip CMOS microcomputer having a data processing capability comparable to
that of an 8-bit microcomputer. Operating at high speeds, the microcomputer allows data to be manipulated
in units of 1, 4, or 8 bits. In addition, various bit manipulation instructions are provided to reinforce I/O
manipulation capability. Equipped with I/Os for interfacing with peripheral circuits operating on a different
supply voltage, outputs that can directly drive LEDs, and analog inputs,
PD75108A is suitable for controlling
such small equipments as cameras and VCRs.
Detailed functions are described in the following user's manual. Be sure to read it for designing.
PD751XX Series User's Manual: IEM-922
FEATURES
Internal memory
Program memory (ROM)
: 8064
8 bits (
PD75108A)
: 4096
8 bits (
PD75104A)
Data memory (RAM)
: 512
4 bits (
PD75108A)
: 320
4 bits (
PD75104A)
Architecture "75X" rivaling 8-bit microcomputers
43 systematically organized instructions
A wealth of bit manipulation instructions
8-bit data transfer, compare, operation, increment, and decrement instructions
1-byte relative branch instructions
GETI instruction executing 2-/3-byte instruction with one byte
High speed. Minimum instruction execution time: 0.95
s (at 4.19 MHz, 5V)
Instruction execution time change function: 0.95
s/1.91
s/15.3
s (at 4.19 MHz)
I/O port pins as many as 58
Three channels of 8-bit timers
8-bit serial interface
Multiplexed vector interrupt function
NEC Corporation 1989
Document No.
IC-2568A
(O. D. No.
IC-7080B)
Date Published
January 1994 P
Printed in Japan
DATA SHEET
MOS INTEGRATED CIRCUIT
PD75104A, 75108A
4-BIT SINGLE-CHIP MICROCOMPUTER
The mark 5 shows major revised points.
The information in this document is subject to change without notice.
Unless there are differences among
PD75104A and 75108A functions,
PD75108A is treated as the
representative model throughout this manual.
PD75104A, 75108A
2
ORDERING INFORMATION
Part Number
Package
Quality Grade
PD75104AGC-xxx-AB8
64-pin plastic QFP ( 14 mm)
Standard
PD75108AGC-xxx-AB8
64-pin plastic QFP ( 14 mm)
Standard
Remarks: xxx is ROM code number.
Please refer to "Quality Grade on NEC Semiconductor Devices" (Document Number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
PD75104A, 75108A
3
Item
Specifications
Number of Basic Instructions
43
Minimum Instruction
Changeable in three steps: 0.95
s, 1.91
s, and 15.3
s at 4.19 MHz
Execution Time
ROM
8064
8 bits (
PD75108A), 4096
8 bits (
PD75104A)
RAM
512
4 bits (
PD75108A), 320
4 bits (
PD75104A)
General-Purpose Register
(4 bits
8
)
4 banks or (8 bis x 4 ) x 4 banks
Three accumulators selectable according to the bit length of manipulated data:
1-bit accumulator (CY), 4-bit accumulator (A), and 8-bit accumulator (XA)
58 port pins
CMOS input pins (Pull-up resistor can be conneced to 4 out of 10 pins
in bit units.): 10
I/O Port
CMOS I/O pins (can directly drive LEDs. Pull-up resistors can be connected to
24 out of 32 pins in bit units.): 32
Medium voltage N-ch open-drain I/O pins: 12
(can directly drive LEDs. Pull-up resistors can be connected in bit units.)
Comparator input pins (4-bit accuracy): 4
8-bit timer/event counter
2
Timer/Counter
8-bit basic interval timer (can be used as watchdog timer)
8 bits
Serial Interface
LSB first/MSB first mode selectable
Two transfer modes (transfer/reception and reception only modes)
Vector Interrupt
External: 3, Internal: 4
Test Input
External: 2
Standby
STOP and HALT modes
Various bit manipulation instructions (set, reset, test, Boolean operation)
Instruction Set
8-bit data transfer, compare, operation, increment, and decrement
1-byte relative branch instructions
GETI instruction constituting 2 or 3-byte instruction with 1 byte
Power-ON reset circuit (mask option)
Others
Bit manipulation memory (bit sequential buffer: 16 bits)
Package
64-pin plastic QFP ( 14 mm)
FUNCTIONAL OUTLINE
Internal Memory
Accumulator
PD75104A, 75108A
4
CONTENTS
1.
PIN CONFIGURATION (TOP VIEW) ...............................................................................................
6
2.
BLOCK DIAGRAM ...........................................................................................................................
7
3.
PIN FUNCTIONS ..............................................................................................................................
8
3.1
PORT PINS .............................................................................................................................................
8
3.2
PINS OTHER THAN PORTS .................................................................................................................
9
3.3
PIN INPUT/OUTPUT CIRCUITS ...........................................................................................................
10
3.4
RECOMMENDED PROCESSING OF UNUSED PINS ..........................................................................
12
3.5
NOTES ON USING THE P00/INT4, AND RESET PINS ......................................................................
13
4.
MEMORY CONFIGURATION ..........................................................................................................
14
5.
PERIPHERAL HARDWARE FUNCTIONS ........................................................................................
19
5.1
PORTS ....................................................................................................................................................
19
5.2
CLOCK GENERATOR CIRCUIT ............................................................................................................
20
5.3
CLOCK OUTPUT CIRCUIT ....................................................................................................................
21
5.4
BASIC INTERVAL TIMER .....................................................................................................................
22
5.5
TIMER/EVENT COUNTER .....................................................................................................................
22
5.6
SERIAL INTERFACE ..............................................................................................................................
24
5.7
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) ....................................................
26
5.8
BIT SEQUENTIAL BUFFER .... 16 BITS ...............................................................................................
27
5.9
POWER-ON FLAG (MASK OPTION) ....................................................................................................
27
6.
INTERRUPT FUNCTIONS ................................................................................................................
27
7.
STANDBY FUNCTIONS ..................................................................................................................
29
8.
RESET FUNCTION ...........................................................................................................................
30
9.
INSTRUCTION SET .........................................................................................................................
33
10. APPLICATION EXAMPLES ..............................................................................................................
42
10.1
VCR CAMERA ........................................................................................................................................
42
11. MASK OPTION SELECTION ...........................................................................................................
43
PD75104A, 75108A
5
12. ELECTRICAL SPECIFICATIONS ......................................................................................................
44
13. CHARACTERISTIC DATA (REFERENCE VALUE) ..........................................................................
54
14. PACKAGE DRAWINGS ...................................................................................................................
59
15. RECOMMENDED SOLDERING CONDITIONS ...............................................................................
60
APPENDIX A.
FUNCTIONAL DIFFERENCES AMONG THIS SERIES PRODUCTS ........................
61
APPENDIX B.
DEVELOPMENT TOOLS ..............................................................................................
62
APPENDIX C.
RELATED DOCUMENTS ..............................................................................................
63
PD75104A, 75108A
6
1.
PIN CONFIGURATION (TOP VIEW)
64-Pin Plastic QFP ( 14 mm)
P00-P03
: Port 0
SCK
: Serial Clock Input/Output
P10-P13
: Port 1
SO
: Serial Output
P20-P23
: Port 2
SI
: Serial Input
P30-P33
: Port 3
PTO0, PTO1
: Timer Output
P40-P43
: Port 4
PCL
: Clock Output
P50-P53
: Port 5
PTH00-PTH03
: Comparator Input
P60-P63
: Port 6
INT0, INT1, INT4
: External Vector Interrupt Input
P70-P73
: Port 7
INT2, INT3
: External Test Input
P80-P83
: Port 8
TI0, TI1
: Timer Input
P90-P93
: Port 9
X1, X2
: Oscillation Pin
P120-P123 : Port 12
RESET
: Reset Input
P130-P133 : Port 13
NC
: No Connection
P140-P143 : Port 14
V
DD
: Positive Power Supply
V
SS
: GND
V
SS
PD75104AGC-xxx-AB8
PD75108AGC-xxx-AB8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
V
DD
P21/PTO1
P20/PTO0
P01/SCK
P00/INT4
P123
P122
P121
P120
P133
P22/PCL
P23
TI1
TI0
PTH00
P02/SO
P03/SI
P61
P62
X2
RESET
P50
P51
P52
P53
P40
P60
P73
P72
P71
P70
X1
P63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P83
P82
P81
P80
P93
P92
P91
P90
P13/INT3
P12/INT2
P11/INT1
P10/INT0
PTH03
PTH02
PTH01
P41
P42
P43
P30
P31
P32
P33
NC
P140
P141
P142
P143
P130
P131
P132
PD75104A, 75108A
7
2.
BLOCK DIAGRAM
TI0
PTO0/P20
BASIC
INTERVAL
TIMER
INTBT
PROGRAM
COUNTER*
ALU
CY
SP (8)
BANK
GENERAL REG.
DECODE
AND
CONTROL
ROM
PROGRAM
MEMORY
8064 8BITS
: PD75108A
4096 4BITS
: PD75104A
RAM
DATA MEMORY
512 4BITS
: PD75108A
320 4BITS
: PD75104A
f /2
X
N
CPU CLOCK
PCL/P22
X1
X2
V
DD
V
SS
RESET
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
CLOCK
GENERATOR
STAND BY
CONTROL
TIMER/EVENT
COUNTER
#0
TIMER/EVENT
COUNTER
#1
SERIAL
INTERFACE
INTERRUPT
CONTROL
PROGRAM-
MABLE
THRESHOLD
PORT #0
TI1
PTO1/P21
SI/P03
SO/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT3/P13
INT4/P00
PTH00-PTH03
4
4
4
4
4
4
4
4
4
4
4
4
4
4
BIT SEQ.
BUFFER (16)
PORT 0
P00 - P03
P10 - P13
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT 8
PORT 9
PORT 12
PORT 13
PORT 14
P20 - P23
P30 - P33
P40 - P43
P50 - P53
P60 - P63
P70 - P73
P80 - P83
P90 - P93
P120 - P123
P130 - P133
P140 - P143
*: 13 bits: PD75108A
12 bits: PD75104A
INTT0
INTT1
INTSIO
PD75104A, 75108A
8
3.
PIN FUNCTIONS
3.1
PORT PINS
I/O
Pin Name
I/O
Shared with:
Function
At Reset
Circuit
Type*
1
P00
Input
INT4
B
P01
I/O
SCK
F
4-bit input port (PORT 0)
Input
P02
I/O
SO
E
P03
Input
SI
B
x
P10
INT0
P11
INT1
Input
4-bit input port (PORT 1)
Input*
2
B -A
P12
INT2
P13
INT3
P20*
3
PTO0
P21*
3
PTO1
I/O
4-bit I/O port (PORT 2)
Input
E
P22*
3
PCL
x
P23*
3
--
4-bit programmable I/O port (PORT 3)
P30-P33*
3
I/O
--
Input
E
Can be specified for input or output bitwise.
P40-P43*
3
I/O
--
4-bit I/O port (PORT 4)
Input*
2
E-A
o
P50-P53*
3
I/O
--
4-bit I/O port (PORT 5)
Input*
2
E-A
4-bit programmable I/O port (PORT 6)
P60-P63*
3
I/O
--
Input*
2
E-A
Can be specified for input or output bitwise.
o
P70-P73*
3
I/O
4-bit I/O port (PORT 7)
Input*
2
E-A
P80-P83*
3
I/O
--
4-bit I/O port (PORT 8)
Input*
2
E-A
o
P90-P93*
3
I/O
--
4-bit I/O port (PORT 9)
Input*
2
E-A
4-bit N-ch open-drain I/O port (PORT 12)
Built-in pull-up resistors can be specified in bit
P120-P123*
3
I/O
--
units (by mask option).
Open-drain withstanding voltage: 12 V
o
4-bit N-ch open-drain I/O port (PORT 13)
Built-in pull-up resistors can be specified in bit
P130-P133*
3
I/O
--
units (by mask option).
Open-drain withstanding voltage: 12 V
4-bit N-ch open-drain I/O port (PORT 14)
Built-in pull-up resistors can be specified in bit
P140-P143*
3
I/O
--
Input*
2
M
units (by mask option).
Open-drain withstanding voltage: 12 V
*1: Circles indicate Schmitt trigger input pins.
2: With pull-up resistor connected: high level
Without pull-up resistor connected: high impedance
3: Can directly drive LEDs.
8-Bit
I/O
Input*
2
M
Input*
2
M
PD75104A, 75108A
9
3.2
PINS OTHER THAN PORTS
I/O
Pin Name
I/O
Shared with:
Function
At Reset
Circuit
Type*
1
PTH00-PTH03
Input
--
4-bit variable threshold voltage analog input port
--
N
TI0
External event pulse inputs for timer/event counter.
Input
--
Also serves as edge-detected vector interrupt input.
--
B
TI1
1-bit input also possible.
PTO0
P20
I/O
Outputs for timer/event counter
Input
E
PTO1
P21
SCK
I/O
P01
Serial clock I/O
Input
F
SO
I/O
P02
Serial data output
Input
E
SI
Input
P03
Serial data input
Input
B
Edge-detected vectored interrupt input (both rising and
INT4
Input
P00
Input
B
falling edges detected)
INT0
P10
Edge-detected vectored interrupt inputs (valid
Input
Input*
2
B -A
INT1
P11
edge selectable)
INT2
P12
Input
Edge-detected testable inputs (rising edge detected)
Input*
2
B -A
INT3
P13
PCL
I/O
P22
Clock output
Input
E
Crystal/ceramic system clock oscillator connections.
X1, X2
--
--
Input external clock to X1, and signal in reverse phase
--
--
with X1 to X2.
RESET
Input
--
System reset input (low level active type)
--
B
NC
--
--
No Connection
--
--
V
DD
--
--
Positive power supply
--
--
V
SS
--
--
GND
--
--
*1: Circles indicate Schmitt trigger input pins.
2: With pull-up resistor connected: high level
Without pull-up resistor connected: high impedance
PD75104A, 75108A
10
3.3
PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the
PD75108A.
TYPE A
TYPE D
TYPE B
TYPE E
IN
V
DD
Input buffer of CMOS standard
Pch
Nch
IN
Schmitt trigger input with hysteresis characteristics
data
output
disable
Type D
Type A
IN/OUT
TYPE D
TYPE E-A
data
output
disable
Type D
Type A
IN/OUT
data
output
disable
OUT
Push pull output that can be set in a output
high impedance state (both P ch and N ch are off)
V
DD
P-ch
N-ch
I/O circuit consisting of Type D push-pull output circuit
and Type A input buffer
I/O circuit consisting of Type D push-pull output and Type
A input buffer
IN
Schmitt trigger input with hysteresis characteristics
V
DD
Pull-up resistor
(mask option)
V
DD
Pull-up resistor
(mask option)
PD75104A, 75108A
11
TYPE F
IN
+
Comparator
V (threshold voltage)
REF
TYPE N
TYPE M
V
DD
IN/OUT
data
output
disable
N-ch
(+12 V
withstand)
Medium-voltage input buffer
(+12 V withstand)
Pull-up resistor
(mask option)
data
output
disable
Type D
Type B
IN/OUT
I/O circuit consisting of Type D push-pull output circuit
and Type B Schmitt trigger input
PD75104A, 75108A
12
3.4
RECOMMENDED PROCESSING OF UNUSED PINS
Pin
Recommended connections
PTH00-PTH03
TI0
Connect to V
SS
or V
DD
TI1
P00
Connect to V
SS
P01-P03
Connect to V
SS
or V
DD
P10-P13
Connect to V
DD
when a pull-up resistor is provided.
Connect to VSS when a pull-up resistor is not provided.
P20-P23
Input: Connect to V
SS
P30-P33
Output: Open
P40-P43
P50-P53
When a pull-up resistor is provided:
P60-P63
Input: Connect to V
DD
P70-P73
Output: Open
P80-P83
When a pull-up resistor is not provided:
P90-P93
Input: Connect to V
SS
or V
DD
P120-P123
Output: Open
P130-P133
P140-P143
RESET
Connect to V
DD
*
NC
Open or connect to V
DD
*: Connect this pin to the V
DD
pin only when a power-ON reset circuit
is provided as a mask option.
PD75104A, 75108A
13
3.5
NOTES ON USING THE P00/INT4, AND RESET PINS
In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode,
in which the internal fuctions of the
PD75108A are tested (solely used for IC tests), is provided to the P00/
INT4 and RESET pins.
If a voltage exceeding V
DD
is applied to either of these pins, the
PD75108A is put into test mode. Therefore,
even when the
PD75108A is in normal operation, if noise exceeding the V
DD
is input into any of these pins,
the
PD75108A will enter the test mode, and this will cause problems for normal operation.
As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up
to these pins and the above montioned problem may occur.
Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot
be avoided, suppress the noise using a capacitor or diode as shown in the figure below.
Connect a capacitor across P00/INT4 and
RESET , and V
DD
.
Connect a diode across P00/INT4 and
RESET , and V
DD
.
V
DD
V
DD
P00/INT4, RESET
V
DD
V
DD
P00/INT4, RESET
PD75104A, 75108A
14
4.
MEMORY CONFIGURATION
Program memory (ROM) ... 8064
8 bits (0000H-1F7FH) :
PD75108A
... 4096
8 bits (0000H-0FFFH) :
PD75104A
0000H, 0001H :
Vector table to which address from which program is started is written after reset
0002H-000BH: Vector table to which address from which program is started is written after interrupt
0020H-007FH : Table area referenced for GETI instruction
Data memory (RAM)
Data area ....512
4 bits (000H1FFH) :
PD75108A
320
4 bits (000H-13FH) :
PD75104A
Peripheral hardware area .... 128
4 bits (F80HFFFH)
PD75104A, 75108A
15
(a)
PD75108A
7
6
5
MBE RBE
0
MBE RBE
0
MBE RBE
0
MBE RBE
0
MBE RBE
0
MBE RBE
0
Internal reset start address (upper 5 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (upper 5 bits)
INTBT/INT4 start address (lower 8 bits)
INT0/INT1 start address (upper 5 bits)
INT0/INT1 start address (lower 8 bits)
INTSIO start address (upper 5 bits)
INTSIO start address (lower 8 bits)
INTT0 start address (upper 5 bits)
INTT0 start address (lower 8 bits)
INTT1 start address (upper 5 bits)
INTT1 start address (lower 8 bits)
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1F7FH
GETI instruction reference table
0
BRCB
! caddr
instruction
branch
address
CALLF
! faddr
instruction
entry
address
BR ! addr
instruction
branch address
CALL ! addr
instruction
subroutine
entry address
BR $addr
instruction
relational
branch address
-15 to -1,
+2 to +16
Branch destination
address and
subroutine entry
address for
GETI instruction
Address
BRCB ! caddr
instruction
branch address
Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC
with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.
Fig. 4-1 Program Memory Map (1/2)
PD75104A, 75108A
16
(b)
PD75104A
Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC
with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.
Fig. 4-1 Program Memory Map (2/2)
7
6
5
MBE RBE
0
MBE RBE
0
MBE RBE
0
MBE RBE
0
MBE RBE
0
MBE RBE
0
Internal reset start address (upper 4 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (upper 4 bits)
INTBT/INT4 start address (lower 8 bits)
INT0/INT1 start address (upper 4 bits)
INT0/INT1 start address (lower 8 bits)
INTSIO start address (upper 4 bits)
INTSIO start address (lower 8 bits)
INTT0 start address (upper 4 bits)
INTT0 start address (lower 8 bits)
INTT1 start address (upper 4 bits)
INTT1 start address (lower 8 bits)
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
GETI instruction reference table
0
CALLF
! faddr
instruction
entry
address
CALL ! addr
instruction
subroutine
entry address
Address
4
0
0
0
0
0
0
BR $addr
instruction
relational
branch address
-15 to -1,
+2 to +16
BRCB ! caddr
instruction
branch address
Branch destination
address and
subroutine entry
address for
GETI instruction
PD75104A, 75108A
17
(a)
PD75108A
000H
01FH
0FFH
100H
1FFH
F80H
FFFH
Data memory
Memory bank
(32
4)
256
4
Not provided
128
4
Bank 0
General-purpose
register area
Stack area
Data memory
Static RAM
(512
4)
Peripheral hardware area
256
4
Bank 1
Bank 15
Fig. 4-2 Data Memory Map(1/2)
PD75104A, 75108A
18
(b)
PD75104A
000H
01FH
0FFH
100H
13FH
F80H
FFFH
Data memory
Memory bank
(32
4)
256
4
Not provided
128
4
Bank 0
General-purpose
register area
Stack area
Data
area
Static RAM
(320
4)
Peripheral hardware area
64
4
Bank 1
Bank 15
Fig. 4-2 Data Memory Map(2/2)
PD75104A, 75108A
19
Shared witn SI, SO, SCK, and
Can always be read or tested regardless of operation
INT4 pins
4-bit input
mode of shared pin
Shared with INT0 to 3 pins each
bit can be connected to pull-up
resistor by mask otion.
Each bit of Port 6 pins can be
Can be set in input or output mode bitwise
connected to pull-up resistor by
mask option
Shared with PTO0, PTO1, and
PCL pins.
4-bit I/O*
4-bit I/O*
Can be set in input or output mode in 4-bit units.
Each bit can be connected to
(N-ch open-drain.
Ports 12 and 13 can be used in pairs to input or
pull-up resistor by mask option
12V)
output 8-bit data
5.
PERIPHERAL HARDWARE FUNCTIONS
5.1
PORTS
I/O ports are classified into the following 3 kinds:
CMOS input (PORT0, 1)
:
8
CMOS input/output (PORT2, 3, 4, 5, 6, 7, 8, 9) : 32
N-ch open-drain input/output (PORT12, 13, 14)
: 12
Total
: 52
Table 5-1 Port Function
PORT0
PORT1
PORT3
PORT6
PORT2
PORT4
PORT5
PORT7
PORT8
PORT9
PORT12
PORT13
PORT14
Port
(Symbol)
Function
Operation and Features
Remarks
Can be set in input or output mode in 4-bit units.
Ports 4 and 5, 6 and 7, 8 and 9 can be used in pairs
to input or output 8-bit data
Each bit can be connected to pull-
up resistor by mask option
*: Can directly drive LED.
PD75104A, 75108A
20
5.2
CLOCK GENERATOR CIRCUIT
The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and
peripheral hardware. In addition, this circuit can change the instruction execution time.
0.95
s/1.91
s/15.3
s (operating at 4.19 MHz)
Basic interval timer (BT)
Clock output circuit
Timer/event counter
Serial interface
f or
XX
f
X
1/2 1/16
1/8 to 1/4096
Frequency divider
X1
X2
System clock
generator
circuit
Oscillation
stops
Selector
1/4
Frequency
divider
CPU
Clock output
circuit
HALT F/F
S
R
Q
PCC
PCC0
PCC1
PCC2
PCC3
4
Internal bus
HALT*
STOP*
Clears
PCC2,
PCC3
STOP F/F
Q
S
R
Wait release signal from BT
RES (internal reset) signal
Standby release signal from
interrupt control circuit
X2
X1
Remarks 1: f
XX
= Crystal/ceramic oscillator
2: f
X
= External clock frequency
3: * indicates the instruction execution
4: PCC: Processor clock control register
5: One clock cycle (t
CY
) of
is one machine cycle of an instruction. For t
CY
, refer to AC
characteristics in 12. ELECTRICAL SPECIFICATIONS.
Fig. 5-1 Clock Generator Block Diagram
5
PD75104A, 75108A
21
5.3
CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output
clock pulses to the remote control output, peripheral LSIs, etc.
Clock output (PCL) :
, 524 kHz, 262 kHz (operating at 4.19 MHz)
Selector
Output
buffer
PCL/P22
Bit 2 of PMGB
PORT2.2
Port 2 input/
output mode
specification
bit
P22 output
latch
Internal bus
CLOM3 CLOM2 CLOM1 CLOM0 CLOM
4
f
X
/2
3
f
X
/2
4
From the
clock
generator
X
X
Fig. 5-2 Clock Output Circuit Configuration
PD75104A, 75108A
22
5.4
BASIC INTERVAL TIMER
The basic interval timer has these functions:
Interval timer operation which generates a reference time interrupt
Watchdog timer application which detects a program runaway
Selects the wait time for releasing the standby mode and counts the wait time
Reads out the count value
Remarks : *: Instruction execution
Fig. 5-3 Basic Interval Timer Configuration
From the
clock generator
f
X
/2
5
f
X
/2
7
f
X
/2
9
f
X
/2
12
MPX
Clear
Basic interval timer
(8-bit frequency divider circuit)
3
4
8
BT
Clear
Set
signal
BT
interrupt
request flag
IRQBT
Wait release signal
for standby release
Vector
interrupt
request
signal
Internal bus
BTM3
BTM2
BTM1
BTM0
BTM
*SET1
X
X
X
X
5.5
TIMER/EVENT COUNTER
PD75108A contains two channels of timer/event counters.
These two channels are almost identical in terms of configuration and function except the count pulse (CP) that
can be selected and the function to supply clocks to the serial interface.
The functions of the timer/event counter include:
Programmable interval timer operation
Output of square wave at an arbitrary frequency to PTOn pin
Event counter operation
Input of TIn pin signal as external interrupt input signal
Dividing TIn pin input by N to output to PTOn pin (frequency divider operation)
Supply of serial shift clock to serial interface circuit (channel 0 only)
Reading counting status
PD75104A, 75108A
23
Internal bus
8
8
8
Modulo register (8)
TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0
TIn
Input buffer
TIn
MPX
CP
From
clock
generator
circuit
Timer operation start
SET1*
TMn
TMODn
Tn
Clear
RES
Comparator (8)
Count register (8)
TOUT
F/F
Coincidence
TOFn
To
selector
TMn1
TMn0
Edge
detector
circuit
To
enable
flag
P2n
output
latch
Port 2
I/O
mode
TOEn
TOn
PORT2.n
Bit 2 of PGMB
To serial
interface
(channel 0 only)
P2n/PTOn
Output
buffer
IRQTn set
signal
Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1)
*: SET1: Execution of the instruction
8
8
IRQTn clear
signal
INTTn
PD75104A, 75108A
24
5.6
SERIAL INTERFACE
The
PD75108A is equipped with clock 8-bit serial interface that operates in the following two modes:
Operation stop mode
Three-line serial I/O mode
PD75104A, 75108A
25
Internal bus
8
8
8
P03/SI
P02/SO
P01/SCK
SIO0
Shift register (8)
SIO7
SIO
Q
S
R
Clear
Serial clock
counter (3)
Overflow
MPX
*: Execution of the instruction
f /2
XX
4
f /2
XX
10
TOF0 (from timer channel 0)
Serial start
SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0
SET1*
SIOM
IRQSIO
clear signal
Fig. 5-5 Serial Interface Block Diagram
IRQSIO
set signal
INTSIO
PD75104A, 75108A
26
5.7
PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)
PD75108A is equipped with a 4-bit analog input port (consisting of PTH00 to PTH03 pins) whose threshold
voltage is programmable. This programmable threshold port is configured as shown in Figure 5-6.
The threshold voltage (V
REF
) can be changed in 16 steps (V
DD
0.5/16 V
DD
15.5/16), and analog signals can be
directly input.
When V
REF
is set to V
DD
7.5/16, the programmable threshold port can also be used as a digital signal input port.
Input buffer
PTH00
PTH01
PTH02
PTH03
+
+
+
+
V
DD
Internal bus
Programmable threshold port
input latch (4)
Operates
/stops
PTH0
8
4
MPX
PTHM7
PTHM6
PTHM5
PTHM4
PTHM3
PTHM2
PTHM1
PTHM0
PTHM
1
2
R
1
2
R
R
R
V
REF
Fig. 5-6 Programmable Threshold Port Configuration
PD75104A, 75108A
27
5.8
BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this
buffer is very useful for processing long data in bit units.
Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 5-7 Bit Sequential Buffer Format
5.9
POWER-ON FLAG (MASK OPTION)
The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal
has been generated (see Fig. 8-1).
The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation
instruction. However, it cannot be set by the SET1 instruction.
6. INTERRUPT FUNCTIONS
The
PD75108A has 7 different interrupt sources and can perform multiplexed interrupt processing with
priority assigned. In addition to that, the
PD75108A is also provided with two types of edge detection testable
inputs.
The interrupt control circuit of the
PD75108A has these functions:
Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by
using the interrupt enable flag (IExxx) and interrupt master enable flag (IME).
The interrupt start address can be arbitrarily set.
Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS).
Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of
software).
Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
Address bit
Symbol
L register
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
L = F
L = C L = B
L = 8 L = 7
L = 4 L = 3
L = 0
BSB3
BSB2
BSB1
BSB0
DECS L
INCS L
FC3H
FC2H
FC1H
FC0H
PD75104A, 75108A
28
Internal bus
2
2
IM1
IM0
IRQBT
INT4
/P00
INT0
/P10
INT1
/P11
INT2
/P12
INT
BT
INTSIO
INTT0
Edge
detection
circuit
Edge
detection
circuit
Edge
detection
circuit
Edge
detection
circuit
Edge
detection
circuit
IRQ4
IRQ0
IRQ1
IRQSIO
IRQT0
IRQT1
IRQ2
Interrupt enable flag (IE )
IME
Decoder
IST
Priority control
circuit
Vector table
address
generator
Standby
release signal
Fig. 6-1 Interrupt Control Block Diagram
9
IRQ3
IPS
2
4
INTT1
INT3
/P13
Interrupt
request flag
PD75104A, 75108A
29
7. STANDBY FUNCTIONS
The
PD75108A has two different standby modes (STOP mode and HALT mode) to reduce the power
consumption of the microcomputer chip while waiting for program execution.
Table 7-1 Each Status in Standby Mode
Setting Instruction
STOP instruction
HALT instruction
Clock Oscillator
circuit
Basic Interval
Timer
Operates (sets IRQBT at reference
time intervals)
Outputs when clock other than CPU
clock
is used
Operates only when input of external
SCK or output of TO0 is selected as
serial clock (where external TI0 is input
to timer/event counter 0)
Operates when serial clock other
than
is specified
Operates
CPU
Stops
Stops
Stops
Release Signal
Interrupt request signal enabled by interrupt enable flag, or RESET input
Serial Interface
Clock output circuit
Stops
STOP Mode
HALT Mode
Clock oscillation stops
Only CPU clock
is stopped
Operation
Status
Timer/Event
Counter
Operates only when TIn pin input
signal is specified as count clock
PD75104A, 75108A
30
8.
RESET FUNCTION
The reset ( RES ) signal generator circuit is configured as shown in Figure 8-1.
RESET
SWB
SWA
Power-ON
reset
generator
circuit
Internal reset signal
(RES)
Power-ON
flag (PONF)
Execution of bit
manipulation
instruction*
Internal bus
Mask
option
*: PONF cannot be set to 1 by SET1 instruction.
Fig. 8-1 Reset Signal Generator Circuit
The Power-ON reset generator circuit generates an internal reset signal when the supply voltage rises. This pulse
can be used in three ways by specifying a mask option through SWA and SWB shown in Fig. 8-1. (Refer to 11. MASK
OPTION SELECTION.)
The reset operations performed by the Power-On reset circuit and the RESET input signal are illustrated in Figs.
8-2 and 8-3, respectively.
Supply voltage
0 V
Internal reset signal
(RES)
Wait*
(approx. 31.3 ms: 4.19 MHz)
HALT mode
Operation mode
Internal reset operation
*: The wait time does not include the time required after the RES signal has been generated until the
oscillation starts.
Fig. 8-2 Reset by Power-ON Reset Circuit
PD75104A, 75108A
31
RESET input during
Power-ON Reset or RESET
standby mode
Input during Operation
Lower 5 bits of program
Lower 5 bits of program
memory address 0000H are
memory address 0000H
Program Counter (PC)
set to PC
12-8
,*
1
and
are set to PC
12-8
,*
1
and
contents of address 0001H
contents of address 0001H
are set to PC
7-0
.
are set to PC
7-0
.
Carry Flag (CY)
Retained
Undefined
Skip Flags (SK0-SK2)
0
0
PSW
Interrupt Status Flags (IST0, IST1)
0
0
Bit 6 of program memory
Bit 6 of program memory
Bank Enable Flags (MBE, RBE)
address 0000H is set in
address 0000H is set in
RBE, and bit 7 is set in
RBE, and bit 7 is set in
MBE.
MBE.
Stack Pointer (SP)
Undefined
Undefined
Data Memory (RAM)
Retained*
2
Undefined
General-Purpose Registers (X,A,H,L,D,E,B,C)
Retained
Undefined
Bank Selector Registers (MBS, RBS)
0, 0
0, 0
Counter (BT)
Undefined
Undefined
Mode Register (BTM)
0
0
Counter (Tn)
0
0
Modulo Register (TMODn)
FFH
FFH
Mode Register (TMn)
0
0
TOEn, TOFn
0, 0
0, 0
Serial Interface
Shift Register (SIO)
Retained
Undefined
Mode Register (SIOM)
0
0
*1: PC
11-8
for
PD75104A
2: Data at data memory addresses 0F8H to 0FDH become undefined when the RESET signal has been input.
Wait*
(31.3 ms: 4.19 MHz)
HALT mode
Operation mode
Operation mode
or standby mode
RESET input
Internal reset operation
Table 8-1 Hardware Device Status After Reset (1/2)
Hardware
Basic interval timer
Timer/Event Counter
(n = 0, 1)
*: The wait time does not include the time required after the RES signal has been generated until the
oscillation starts.
Fig. 8-3 Reset by RESET Signal
The status of each internal hardware device after the reset operation has been performed is shown in Table 8-
1.
PD75104A, 75108A
32
RESET input during
Power-ON Reset or RESET
standby mode
Input during Operation
Processor Clock Control Register
0
0
(PCC)
Clock Output Mode Register
0
0
(CLOM)
Interrupt Request Flags
Reset (0)
Reset (0)
(IRQxxx)
Interrupt Enable Flags (IExxx)
0
0
Interrupt
Priority Selector Register (IPS)
0
0
INT0, 1 Mode Registers
0, 0
0, 0
(IM0, IM1)
Output Buffer
Off
Off
Digital Port
Output Latch
Cleared (0)
Cleared (0)
I/O Mode Registers
0
0
(PMGA, PMGB, PMGC)
PTH00-PTH03 Input Latches
Undefined
Undefined
Analog Port
Mode Register (PTHM)
0
0
Power-ON Flag (PONF)
Retained
1 or undefined*
Bit Sequential Buffer (BSB0-BSB3)
0
0
*: Power-ON reset: 1
RESET input during operation: undefined
Table 8-1 Hardware Device Status After Reset (2/2)
Hardware
Clock Generator Circuit,
Clock Output Circuit
PD75104A, 75108A
33
9.
INSTRUCTION SET
(1)
Operand representation and description
Describe one or more operands in the operand field of each instruction according to the operand
representation and description methods of the instruction (for details, refer to RA75X Assembler Package
User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from
several operands. The uppercase characters, +, and are keywords and must be described as is.
Describe an appropriate numeric value or label as immediate data.
The symbols in the register and flag symbols can be described as labels in the places of mem, fmem,
pmem, and bit (for details, refer to
PD751XX Series User`s Manual (IEM-922)). However, fmem and pmem
restricts the label that can be described.
Representation
Description
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp'
XA, BC, DE, HL, XA', BC', DE', HL'
rp'1
BC, DE, HL, XA', BC', DE', HL'
rpa
HL, HL+, HL, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or label*
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
addr
PD75104A
0000H to 0FFFH immediate data or label
PD75108A
0000H to 1F7FH immediate data or label
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (where bit0 = 0) or label
PORTn
PORT0 - PORT9, PORT12 - PORT14
IExxx
IEBT, IESIO, IET0, IET1, IE0 - IE4
RBn
RB0 - RB3
MBn
MB0, MB1, MB15
*: Only even address can be described as mem for 8-bit data processing.
PD75104A, 75108A
34
(2)
Legend of operation field
A
: A register; 4-bit accumulator
B
: B register; 4-bit accumulator
C
: C register; 4-bit accumulator
D
: D register; 4-bit accumulator
E
: E register; 4-bit accumulator
H
: H register; 4-bit accumulator
L
: L register; 4-bit accumulator
X
: X register; 4-bit accumulator
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC); 8-bit accumulator
DE
: Register pair (DE); 8-bit accumulator
HL
: Register pair (HL); 8-bit accumulator
XA'
: Expansion register pair (XA')
BC'
: Expansion register pair (BC')
DE'
: Expansion register pair (DE')
HL'
: Expansion register pair (HL')
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; or bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 - 9, 12 - 14)
IME
: Interrupt mask enable flag
IPS
: Interrupt priority selection register
IExxx
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Delimiter of address and bit
(xx)
: Contents addressed by xx
xxH
: Hexadecimal data
PD75104A, 75108A
35
(3)
Symbols in addressing area field
*1
MB = MBE . MBS
(MBS = 0, 1, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (00H-7FH)
Data memory
MB = 15 (80H-FFH)
addressing
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4
MB = 15, fmem = FB0H-FBFH,
FF0H-FFFH
*5
MB = 15, pmem = FC0H-FFFH
*6
PD75104A
addr = 0000H-0FFFH
PD75108A
addr = 0000H-1F7FH
*7
addr = (Current PC) 15 to (Current PC) 1
(Current PC) + 2 to (Current PC) + 16
Program memory
*8
PD75104A
caddr = 0000H-0FFFH (PC
11
= 0)
addressing
PD75108A
caddr = 0000H-0FFFH (PC
12
= 0) or 1000H-1F7FH (PC
12
= 1)
*9
faddr = 0000H-07FFH
*10
taddr = 0020H-007FH
Remarks MB indicates memory bank that can be accessed.
In *2, MB = 0 regardless of MBE and MBS.
In *4 and *5, MB = 15 regardless of MBE and MBS.
*6 to *10 indicate areas that can be addressed.
(4)
Machine cycle field
In this field, S indicates the number of machine cycles required when an instruction having a skip
function skips. The value of S varies as follows:
When no instruction is skipped ........................................................................
S = 0
When 1-byte or 2-byte instruction is skipped .................................................
S = 1
When 3-byte instruction (BR ! adder or CALL ! adder) is skipped ..............
S = 2
Note : The GETI instruction is skipped in one machine cycle.
One machine cycle equals to one cycle of the CPU clock
, (= t
CY
), and can be changed in three steps
depending on the setting of the processor clock control register (PCC).
PD75104A, 75108A
36
Ma-
Instruc-
Mne-
Operand
Bytes
chine
Operation
Addressing
Skip
tions
monics
Cyc-
Area
Conditions
les
Transfer MOV
A, #n4
1
1
A
n4
String effect A
reg1, #n4
2
2
reg1
n4
XA, #n8
2
2
XA
n8
String effect A
HL, #n8
2
2
HL
n8
String effect B
rp2, #n8
2
2
rp2
n8
A, @HL
1
1
A
(HL)
*1
A, @HL+
1
2+S
A
(HL), then L
L+1
*1
L = 0
A, @HL
1
2+S
A
(HL), then L
L1
*1
L = FH
A, @rpa1
1
1
A
(rpa1)
*2
XA, @HL
2
2
XA
(HL)
*1
@HL, A
1
1
(HL)
A
*1
@HL, XA
2
2
(HL)
XA
*1
A, mem
2
2
A
(mem)
*3
XA, mem
2
2
XA
(mem)
*3
mem, A
2
2
(mem)
A
*3
mem, XA
2
2
(mem)
XA
*3
A, reg
2
2
A
reg
XA, rp'
2
2
XA
rp'
reg1, A
2
2
reg1
A
rp'1, XA
2
2
rp'1
XA
XCH
A, @HL
1
1
A
(HL)
*1
A, @HL+
1
2+S
A
(HL), then L
L+1
*1
L = 0
A, @HL
1
2+S
A
(HL), then L
L1
*1
L = FH
A, @rpa1
1
1
A
(rpa1)
*2
XA, @HL
2
2
XA
(HL)
*1
A, mem
2
2
A
(mem)
*3
XA, mem
2
2
XA
(mem)
*3
A, reg1
1
1
A
reg1
XA, rp'
2
2
XA
rp'
MOVT
XA, @PCDE
1
3
PD75104A
XA
(PC
11-8
+DE)
ROM
PD75108A
XA
(PC
12-8
+DE)
ROM
XA, @PCXA
1
3
PD75104A
XA
(PC
11-8
+XA)
ROM
PD75108A
XA
(PC
12-8
+XA)
ROM
Table
Refer-
ence
PD75104A, 75108A
37
Ma-
Instruc-
Mne-
Operand
Bytes
chine
Operation
Addressing
Skip
tions
monics
Cyc-
Area
Conditions
les
Bit
MOV1
CY, fmem.bit
2
2
CY
(fmem.bit)
*4
transfer
CY, pmem.@L
2
2
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.
2
2
CY
(H+mem
3-0.
bit)
*1
bit
fmem.bit, CY
2
2
(fmem.bit)
CY
*4
pmem.@L, CY
2
2
(pmem
7-2
+L
3-2.
bit(L
1-0
))
CY
*5
@H+mem.bit,
2
2
(H+mem
3-0
.bit)
CY
*1
CY
Arith-
ADDS
A, #n4
1
1+S
A
A+n4
carry
metic
XA, #n8
2
2+S
XA
XA+n8
carry
opera-
A, @HL
1
1+S
A
A+(HL)
*1
carry
tion
XA, rp'
2
2+S
XA
XA+rp'
carry
rp'1, XA
2
2+S
rp'1
rp'1+XA
carry
ADDC
A, @HL
1
1
A, CY
A+(HL)+CY
*1
XA, rp'
2
2
XA, CY
XA+rp'+CY
rp'1, XA
2
2
rp'1, CY
rp'1+XA+CY
SUBS
A, @HL
1
1+S
A
A-(HL)
*1
borrow
XA, rp'
2
2+S
XA
XA-rp'
borrow
rp'1, XA
2
2+S
rp'1
rp'1-XA
borrow
SUBC
A, @HL
1
1
A, CY
A-(HL)-CY
*1
XA, rp'
2
2
XA, CY
XA-rp'-CY
rp'1, XA
2
2
rp'1,CY
rp'1-XA-CY
AND
A, #n4
2
2
A
A
n4
A, @HL
1
1
A
A
(HL)
*1
XA, rp'
2
2
XA
XA
rp'
rp'1, XA
2
2
rp'1
rp'1
XA
OR
A, #n4
2
2
A
A
n4
A, @HL
1
1
A
A
(HL)
*1
XA, rp'
2
2
XA
XA
rp'
rp'1, XA
2
2
rp'1
rp'1
XA
XOR
A, #n4
2
2
A
A
n4
A, @HL
1
1
A
A
(HL)
*1
XA, rp'
2
2
XA
XA
rp'
rp'1, XA
2
2
rp'1
rp'1
XA
RORC
A
1
1
CY
A
0
, A
3
CY, A
n-1
A
n
NOT
A
2
2
A
A
Incre-
INCS
reg
1
1+S
reg
reg+1
reg = 0
ment/
rp1
1
1+S
rp1
rp1+1
rp1 = 00H
decre-
@HL
2
2+S
(HL)
(HL)+1
*1
(HL) = 0
ment
mem
2
2+S
(mem)
(mem)+1
*3
(mem) = 0
DECS
reg
1
1+S
reg
reg-1
reg = FH
rp'
2
2+S
rp'
rp'-1
rp' = FFH
Accumulator
Manipulation
PD75104A, 75108A
38
Ma-
Instruc-
Mne-
Operand
Bytes
chine
Operation
Addressing
Skip
tions
monics
Cyc-
Area
Conditions
les
Com-
SKE
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
pare
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A = reg
XA, rp'
2
2+S
Skip if XA = rp'
XA = rp'
Carry
SET1
CY
1
1
CY
1
flag
CLR1
CY
1
1
CY
0
Manipu- SKT
CY
1
1+S
Skip if CY = 1
CY = 1
lation
NOT1
CY
1
1
CY
CY
Memory/ SET1
mem.bit
2
2
(mem.bit)
1
*3
Bit
fmem.bit
2
2
(fmem.bit)
1
*4
Manipu-
pmem.@L
2
2
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
1
*5
lation
@H+mem.bit
2
2
(H + mem
3-0
.bit)
1
*1
CLR1
mem.bit
2
2
(mem.bit)
0
*3
fmem.bit
2
2
(fmem.bit)
0
*4
pmem.@L
2
2
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
0
*5
@H+mem.bit
2
2
(H+mem
3-0
.bit)
0
*1
SKT
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem
7-2
+L
3-2
.bit (L
1-0
)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H + mem
3-0
.bit) = 1
*1
(@H+mem.bit) = 1
SKF
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem
7-2
+L
3-2
.bit (L
1-0
)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2+S
Skip if (H + mem
3-0
.bit) = 0
*1
(@H+mem.bit) = 0
SKTCLR fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem
7-2
+L
3-2
.bit
*5
(pmem.@L) = 1
(L
1-0
)) = 1 and clear
@H+mem.bit
2
2+S
Skip if (H+mem
3-0
.bit) = 1 and clear
*1
(@H+mem.bit) = 1
AND1
CY, fmem.bit
2
2
CY
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
CY
(H+mem
3-0
.bit)
*1
OR1
CY, fmem.bit
2
2
CY
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
(pmem
7-2
+L
3-2
.bit (L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
CY
(H+mem
3-0
.bit)
*1
XOR1
CY, fmem.bit
2
2
CY
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
(pmem
7-2
+L
3-2
.bit (L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
CY
(H+mem
3-0
.bit)
*1
PD75104A, 75108A
39
Ma-
Instruc-
Mne-
Operand
Bytes
chine
Operation
Addressing
Skip
tions
monics
Cyc-
Area
Conditions
les
Branch
BR
addr
--
--
PD75104A
*6
PC
11-0
addr
The most suitable instruction
is selectable from among
BRCB ! caddr, and BR $ addr
depending on the assembler.
PD75108A
PC
12-0
addr
The most suitable instruction
is selectable from among BR
! addr, BRCB ! caddr, and BR
$ addr depending on the
assembler.
! addr
3
3
PD75108A
*6
PC
12-0
addr
$ addr
1
2
PD75104A
*7
PC
11-0
addr
PD75108A
PC
12-0
addr
BRCB
! caddr
2
2
PD75104A
*8
PC
11-0
caddr
11-0
PD75108A
PC
12-0
PC
12
+ caddr
11-0
BR
PCDE
2
3
PD75104A
PC
11-0
PC
11-8
+ DE
PD75108A
PC
12-0
PC
12-8
+ DE
PCXA
2
3
PD75104A
PC
11-0
PC
11-8
+ XA
PD75108A
PC
12-0
PC
12-8
+ XA
Subrou-
CALL
! addr
3
3
PD75104A
*6
tine/
(SP-4)(SP-1)(SP-2)
PC
11-0
Stack
(SP-3)
MBE, RBE, 0, 0
Control
PC
11-0
addr, SP
SP-4
PD75108A
(SP-4)(SP-1)(SP-2)
PC
11-0
(SP-3)
MBE, RBE, 0, PC
12
PC
12-0
addr, SP
SP-4
PD75104A, 75108A
40
Ma-
Instruc-
Mne-
Operand
Bytes
chine
Operation
Addressing
Skip
tions
monics
Cyc-
Area
Conditions
les
CALLF
! faddr
2
2
PD75104A
*9
(SP-4)(SP-1)(SP-2)
PC
11-0
(SP-3)
MBE, RBE, 0, 0
PC
11-0
0,
faddr, SP
SP-4
PD75108A
(SP-4)(SP-1)(SP-2)
PC
11-0
(SP-3)
MBE, RBE, 0, PC
12
PC
12-0
00, faddr, SP
SP-4
RET
1
3
PD75104A
MBE, RBE, x, x
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
SP
SP+4
PD75108A
MBE, RBE, x, PC
12
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
SP
SP+4
RETS
1
3+S
PD75104A
Unconditioned
MBE, RBE, x, x
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
SP
SP+4,
then skip unconditionally
PD75108A
MBE, RBE, x, PC
12
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
SP
SP+4,
then skip unconditionally
RETI
1
3
PD75104A
MBE, RBE, x, x
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
PSW
(SP+4)(SP+5), SP
SP+6
PD75108A
MBE, RBE, x, PC
12
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
PSW
(SP+4)(SP+5), SP
SP+6
PUSH
rp
1
1
(SP-1)(SP-2)
rp, SP
SP-2
BS
2
2
(SP-1)
MBS, (SP-2)
RBS,
SP
SP-2
POP
rp
1
1
rp
(SP+1)(SP), SP
SP+2
BS
2
2
MBS
(SP+1), RBS
(SP),
SP
SP+2
Subrou-
tine/
Stack
Control
(Cont`d)
PD75104A, 75108A
41
Ma-
Instruc-
Mne-
Operand
Bytes
chine
Operation
Addressing
Skip
tions
monics
Cyc-
Area
Conditions
les
Inter-
EI
2
2
IME (IPS.3)
1
rupt
IExxx
2
2
IExxx
1
Control
DI
2
2
IME (IPS.3)
0
IExxx
2
2
IExxx
0
I/O
IN*
A, PORTn
2
2
A
PORT
n
(n = 0-9, 12-14)
XA, PORTn
2
2
XA
PORT
n+1
,PORT
n (n = 4, 6, 8, 12)
OUT*
PORTn, A
2
2
PORT
n
A
(n = 2-9, 12-14)
PORTn, XA
2
2
PORT
n+1
,
PORT
n
XA
(n = 4, 6, 8, 12)
CPU
HALT
2
2
Set HALT Mode (PCC.2
1)
Control
STOP
2
2
Set STOP Mode (PCC.3
1)
NOP
1
1
No Operation
Special
SEL
RBn
2
2
RBS
n (n = 0-3)
MBn
2
2
MBS
n (n = 0, 1, 15)
GETI
taddr
1
3
PD75104A
*10
Where TBR instruction,
PC
11-0
(taddr)
3-0
+(taddr+1)
Where TCALL instruction,
(SP-4)(SP-1)(SP-2)
PC
11-0
(SP-3)
MBE, RBE, 0, 0
PC
11-0
(taddr)
3-0
+(taddr+1)
SP
SP-4
Except for TBR and TCALL
Depends on
instructions,
referenced
Instruction execution of
instruction
(taddr)(taddr+1)
PD75108A
Where TBR instruction,
PC
12-0
(taddr)
4-0
+(taddr+1)
Where TCALL instruction,
(SP-4)(SP-1)(SP-2)
PC
11-0
(SP-3)
MBE, RBE, 0, PC
12
PC
12-0
(taddr)
4-0
+(taddr+1)
SP
SP-4
Except for TBR and TCALL
Depends on
instructions,
referenced
Instruction execution of
instruction
(taddr)(taddr+1)
*: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.
Remarks: TBR and TCALL instructions are assembler instructions for GETI instruction table definition.
.........................................................
.........................................................
.........................................................
.............................
.........................................................
.............................
5
PD75104A, 75108A
42
10. APPLICATION EXAMPLES
10.1
VCR CAMERA
PD75108A
Operation
mode LED
indicator
Servo
system
control
circuit
INT
Motor
plunger
driver
circuit,
etc.
System control/
editing
function
INT
Key matrix
(including
message
input)
Reel pulse
Battery sensor
Sensor circuit
Exposure sensor
Tape start/end
sensor
Power-
down
detector
On-screen
display
controller
12 V
Audio video system
control circuit
Comparator
input
High-
current
output
PD75104A, 75108A
43
PD75108A has the following mask options. Options to be built in can be selected.
(1)
Pin
Pin
Mask Option
P10 - P13
P40 - P43
P50 - P53
P60 - P63
P70 - P73
Pull-down resistor can be built in bitwise.
P80 - P83
P90 - P93
P120 - P123
P130 - P133
P140 - P143
11. MASK OPTION SELECTION
(2)
Power-ON reset generation circuit, power-ON flag (PONF)
One from the following three ways can be selected.
SWA
SWB
Provided
Provided
ON
ON
Generates automatically
Not provided
Provided
ON
OFF
Not generate autoamtically
Not provided
Not provided
OFF
OFF
--
Switching Selection
(Refer to Fig. 8-1.)
Mask Option Specification
Power-On Reset
Generator Circuit
Power-On Flag
(PONF)
Internal Reset Signal
(RES)
PD75104A, 75108A
44
12. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T
a
= 25
C)
Parameter
Symbol
Conditions
Ratings
Unit
Supply Voltage
V
DD
-0.3 to +7.0
V
V
I1
Other than ports 12 to 14
-0.3 to V
DD
+0.3
V
Input Voltage
V
I2
*
1
Ports 12 to 14
w/pull-up
-0.3 to V
DD
+0.3
V
resistor
Open drain
-0.3 to +13
V
Output Voltage
V
O
-0.3 to V
DD
+0.3
V
High-Level Output
I
OH
1 pin
-15
mA
Current
All pins
-30
mA
Low-Level Output
I
OL
*
2
1 pin
Peak
30
mA
Current
rms
15
mA
Total of ports 0, 2 to 4, 12 to 14
Peak
100
mA
rms
60
mA
Total of ports 5 to 9
Peak
100
mA
rms
60
mA
Operating Temperature
T
opt
-40 to +85
C
Storage Temperature
T
stg
-65 to +150
C
*1: The power supply impedance (pull-up resistor) must be 50 k
or higher when a voltage higher than
10 V is applied to ports 12 to 14.
2: rms = Peak value x
Duty
Note: Even if one of the parametrs exceed its absolute maximum rating even momentarily, the quality
of the product may be degraded. The absolute maximum rating therefore specifies the upper or
lower limit of the value at which the product can be used without physical damages. Be sure not
to exceed or fall below this value when using the product.
5
PD75104A, 75108A
45
OSCILLATOR CIRCUIT CHARACTERISTICS
(T
a
= -40 to +85
C, V
DD
= 2.7 to 6.0 V)
Oscillator
Recommended
Item
Conditions
MIN.
TYP.
MAX.
Unit
Constants
Ceramic
Oscillation
V
DD
= Oscillation
2.0
5.0
MHz
frequency(f
XX
)*
1
voltage range
Oscillation stabiliza- After V
DD
come to
tion time*
2
MIN. of oscillation
voltage range
4
ms
Crystal
Oscillation
2.0
4.19
5.0
MHz
frequency (f
XX
)*
1
Oscillation stabiliza- V
DD
= 4.5 to 6.0 V
10
ms
tion time*
2
30
ms
External Clock
X1 input frequency
2.0
5.0
MHz
(f
X
)*
1
X1 input high-,
low-level widths
(t
XH
, t
XL
)
100
250
ns
*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics
of the oscillator circuit. For instruction execution time, refer to AC Characteristics.
2: Time required for oscillation to stabilize after V
DD
has come to MIN. of oscillation voltage range
or the STOP mode has been released.
3: When the oscillation frequency is 4.19 MHz
<
f
xx
5.0 MHz, do not select PCC = 0011 as the
instruction execution time: otherwise, one machine cycle is set to less than 0.95
s, falling short
of the rated minimum value of 0.95
s.
Note:
When using the oscillation circuit of the system clock, wire the portion enclosed in dotted line
in the figures as follows to avoid adverse influences on the wiring capacity:
Keep the wiring length as short as possible.
Do not cross the wiring over the other signal lines. Also, do not route the wiring in the vicinity
of lines through which a high alternating current flows.
Always keep the ground point of the capacitor of the osccillator circuit at the same potential
as V
SS
. Do not connect the ground pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
X1
X2
C1
C2
X1
X2
C1
C2
X1
X2
PD74HCU04
*
3
*
3
*
3
5
5
PD75104A, 75108A
46
RECOMMENDED OSCILLATOR CIRCUITS CONSTANTS
RECOMMENDED CERAMIC OSCILLATORS
External
Oscillation
Manufacturer
Product Name
Capacitance (pF)
Voltage Range (V)
C1
C2
MIN.
MAX.
CSA 2.00MG
30
30
2.7
6.0
Murata Mfg.
CSA 4.19MG
30
30
3.0
6.0
Co., Ltd.
CSA 4.19MGU
30
30
2.7
6.0
CST 4.19T
Provided
Provided
3.0
6.0
KBR-2.0MS
100
100
3.0
6.0
Kyoto Ceramic
KBR-4.0MS
33
33
3.0
6.0
Co., Ltd.
KBR-4.19MS
33
33
3.0
6.0
KBR-4.9152M
33
33
3.0
6.0
RECOMMENDED CRYSTAL OSCILLATOR
External
Oscillation
Manufacturer
Product Name
Capacitance (pF)
Voltage Range (V)
C1
C2
MIN.
MAX.
Kinseki
HC-49/U
22
22
2.7
6.0
Note: Use a crystal oscillator with an equivalent series resistance of 80
or less.
PD75104A, 75108A
47
DC CHARACTERISTICS (T
a
= -40 to +85
C, V
DD
= 2.7 to 6.0 V)
Item
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
IH1
Other than below
0.7V
DD
V
DD
V
High-Level
V
IH2
Ports 0, 1, TI0, 1, RESET
0.8 V
DD
V
DD
V
Input Voltage
Pull-up resistor
0.7 V
DD
V
DD
V
Open drain
0.7 V
DD
12
V
V
IH4
X1, X2
V
DD
-0.5
V
DD
V
V
IL1
Other than below
0
0.3 V
DD
V
Low-Level Input Voltage
V
IL2
Ports 0, 1, TI0, 1, RESET
0
0.2 V
DD
V
V
IL3
X1, X2
0
0.4
V
V
DD
= 4.5 to 6.0 V,I
OH
= -1 mA
V
DD
-1.0
V
I
OH
= -100
A
V
DD
-0.5
V
V
DD
=
Ports 0, 2 to 9, I
OL
= 15 mA
0.35
2.0
V
4.5 to 6.0 V
Ports 12 to 14, I
OL
= 10 mA
0.35
2.0
V
V
DD
= 4.5 to 6.0 V, I
OL
= 1.6 mA
0.4
V
I
OL
= 400
A
0.5
V
I
LIH1
Other than below
3
A
I
LIH2
X1,X2
20
A
I
LIH3
V
IN
= 12 V
Ports 12 to 14 (open drain)
20
A
Low-Level Input
I
LIL1
Other than X1, X2
3
A
Leakage Current
I
LIL2
X1, X2
20
A
High-Level Output
I
LOH1
V
OUT
= V
DD
Other than below
3
A
Leakage Current
I
LOH2
V
OUT
= 12 V
Ports 12 to 14 (open drain)
20
A
Low-Level Output
I
LOL
V
OUT
= 0 V
3
A
Leakage Current
V
DD
= 5 V
10%
15
40
70
k
10
80
k
4.19MHz
V
DD
= 5 V
10%*
2
3
9
mA
crystal
V
DD
= 3 V
10%*
3
0.55
1.5
mA
Supply Current*
1
oscillator
HALT
V
DD
= 5 V
10%
600
1800
A
C1 = C2 = 22pF
mode
V
DD
= 3 V
10%
200
600
A
I
DD3
STOP mode, V
DD
= 3 V
10%
0.1
10
A
*1: The current flowing into the internal pull-up resistor, power-ON reset circuit (mask option), and comparator
circuit is not included.
2: When the high-speed mode is set by setting the processor clock control register (PCC) to 0011.
3: When the low-speed mode is set by setting the PCC to 0000.
Low-Level Output Voltage
V
OL
High-Level Output Voltage
V
OH
V
IN
= V
DD
V
IN
= 0 V
High-Level Input Leakage
Current
Internal Pull-Up Resistor
R
L
I
DD1
I
DD2
V
IH3
Ports 12 to 14
Ports 1, 4 to 9,
and 12 to 14
PD75104A, 75108A
48
CAPACITANCE (T
a
= 25
C, V
DD
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input Capacitance
C
IN
f = 1 MHz
15
pF
Output Capacitance
C
OUT
Pins other than thosemeasured are at 0 V
15
pF
Input/Output
C
IO
15
pF
Capacitance
COMPARATOR CHARACTERISTICS (T
a
= -40 to +85
C, V
DD
= 4.5 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Comparison Accuracy
V
ACOMP
100
mV
Threshold Voltage
V
TH
0
V
DD
V
PTH Input voltage
V
IPTH
0
V
DD
V
Comparator circuit
PTHM7 is set to "1"
1
mA
current dissipation
POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (T
a
= -40 to +85
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Power-On Reset
High-Level
V
DDH
4.5
6.0
V
Operating Voltage
Power-On Reset
Low-Level
V
DDL
0
0.2
V
Operating Voltage
Supply Voltage
t
r
10
*
1
s
Rise Time
Supply Voltage
t
off
1
s
Off Time
Power-On Reset Circuit
I
DDPR
V
DD
= 5 V
10%
10
100
A
Current Dissipation*
2
V
DD
= 2.5 V
2
20
A
*1: 2
17
/f
XX
(31.3 ms at f
XX
= 4.19 MHz)
2: Current flowing when power-ON reset circuit or power-ON Flag is incorporeated.
Note: Apply power gradually and smoothly.
V
DD
V
DDH
V
DDL
t
off
t
r
PD75104A, 75108A
49
AC CHARACTERISTICS (T
a
= -40 to +85
C, V
DD
= 2.7 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
= 4.5 to 6.0 V
0.95
32
s
3.8
32
s
V
DD
= 4.5 to 6.0 V
0
1
MHz
0
275
kHz
t
TIH
,
V
DD
= 4.5 to 6.0 V
0.48
s
t
TIL
1.8
s
V
DD
= 4.5 to 6.0 V
Input
0.8
s
Output
0.95
s
Input
3.2
s
Output
3.8
s
V
DD
= 4.5 to 6.0 V
Input
0.4
s
Output
t
KCY
/2-50
ns
Input
1.6
s
Output
t
KCY
/2-150
ns
SI Setup Time
t
SIK
100
ns
(vs. SCK
)
SI Hold Time
t
KSI
400
ns
(vs. SCK
)
V
DD
= 4.5 to 6.0 V
300
ns
1000
ns
INT0 to INT4
t
INTH,
5
s
High-/Low-Level Width
t
INTL
RESET Low-Level Width
t
RSL
5
s
*: The cycle time of the CPU clock (
) is
determined by the input frequency of
the ceramic or crystal oscillator circuit
and the set value of the processor clock
control register.
The t
CY
vs. V
DD
characteristics are as
shown on the right.
0
1
2
3
4
5
6
0.5
1
2
3
4
5
6
V
DD
[V]
t
CY
[ s]
t
CY
vs. V
DD
32
40
Operation
guaranteed
range
7
CPU Clock Cycle Time*
(Minimum Instruction
Execution Time = 1
Machine Cycle)
t
CY
TI0, TI1 Input Frequency
f
TI
TI0, TI1 Input High-/
Low-Level Width
SCK Cycle Time
t
KCY
SCK High-/Low-Level
Width
t
KH,
t
KL
SCK
SO Output
delay Time
t
KSO
PD75104A, 75108A
50
AC TIMING MEASURING POINTS (excluding Ports 0, 1, TI0, TI1, X1, X2, and RESET)
CLOCK TIMING
TI INPUT TIMING
Measuring
points
0.7 V
DD
0.3 V
DD
0.7 V
DD
0.3 V
DD
X1 input
V
DD
0.5
0.4
t
XL
t
XH
1/f
X
0.8
TI0, TI1
t
TIL
t
TIH
1/f
TI
0.2
V
DD
V
DD
PD75104A, 75108A
51
SERIAL TRANSFER TIMING
SCK
t
KL
t
KH
t
KCY
Output data
t
SIK
t
KSI
t
KSO
Input data
SI
SO
0.8 V
0.2 V
DD
DD
0.8 V
DD
0.2 V
DD
INTERRUPT INPUT TIMING
RESET INPUT TIMING
INT0 to INT4
t
INTL
t
INTH
0.8 V
0.2 V
DD
DD
RESET
t
RSL
0.2 V
DD
PD75104A, 75108A
52
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(T
a
= 40 to +85
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data Retention Supply
V
DDDR
2.0
6.0
V
Voltage
Data Retention Supply
I
DDDR
V
DDDR
= 2.0 V
0.1
10
A
Current*
1
Release Signal Set Time
t
SREL
0
s
Oscillation Stabilization
t
WAIT
Released by RESET
2
17
/f
X
ms
Wait Time*
2
Released by interrupt request
*
3
ms
*1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and
comparator circuit is not included
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent
unstable operation when oscillation is started.
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3
BTM2
BTM1
BTM0
Wait time ( ): f
XX
= 4.19 MHz
0
0
0
2
20
/f
XX
(approx. 250 ms)
0
1
1
2
17
/f
XX
(approx. 31.3 ms)
1
0
1
2
15
/f
XX
(approx. 7.82 ms)
1
1
1
2
13
/f
XX
(approx. 1.95 ms)
DATA RETENTION TIMING (releasing STOP mode by RESET)
STOP mode
Data retention mode
STOP instruction
execution
V
DD
RESET
V
DDDR
t
SREL
t
WAIT
Operation
mode
Internal reset operation
HALT mode
PD75104A, 75108A
53
STOP mode
Data retention mode
STOP instruction execution
V
DD
V
DDDR
t
SREL
t
WAIT
Operation
mode
HALT mode
Standby release signal
(interrupt request)
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
PD75104A, 75108A
54
13. CHARACTERISTIC DATA (REFERENCE VALUE)
5000
1000
500
100
50
10
5
1
0.5
0
1
2
3
4
5
6
I vs. V Characteristics (crystal oscillation)
DD
DD
Supply voltage V [V]
DD
Supply current I [ A]
DD
High-speed mode [0011]
Medium-speed mode [0010]
Low-speed mode [0000]
HALT mode [0100]
STOP mode [1000]
When power-ON
reset circuit and
power-ON flag are
incorporated.
Figure in [ ] indicates
set values of PCC.
Crystal
oscillation
4.194304 MHz
22 pF
22 pF
X1
X2
I vs. f Characteristics (crystal oscillation)
DD
XX
Supply current I [mA]
DD
4
f [MHz]
XX
0
1
2
3
5
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure in [ ] indicates
set values of PCC.
X1
X2
C
1
C
2
High-speed mode [0011]
Medium-speed mode [0010]
Low-speed mode [0000]
HALT mode [0100]
(V = 5.0 V, T = 25C)
DD
a
a
(T = 25C)
PD75104A, 75108A
55
DD
5000
1000
500
100
50
10
5
1
0.5
0
1
2
3
4
5
6
I vs. V Characteristics (ceramic oscillation)
DD
DD
High-speed mode [0011]
Medium-speed mode [0010]
Low-speed mode [0000]
STOP mode [1000]
When power-ON
reset circuit and
power-ON flag are
incorporated.
Figure in [ ] indicates
set values of PCC.
Ceramic
oscillation
4.19 MHz
30 pF
30 pF
X1
X2
I vs. f Characteristics (ceramic oscillation)
XX
DD
4
f [MHz]
XX
0
1
2
3
5
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure in [ ] indicates
set values of PCC.
X1
X2
C
C
High-speed mode [0011]
Medium-speed mode [0010]
Low-speed mode [0000]
HALT mode [0100]
HALT mode [0100]
1
2
a
(T = 25C)
(V = 5.0 V, T = 25C)
a
Supply voltage V [V]
DD
Supply current I [ A]
DD
Supply current I [mA]
DD
PD75104A, 75108A
56
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1
2
3
4
5
X1
X2
PD74HCU04
Figures in [ ] indicates
set values of PCC.
I vs. f Characteristics (external clock)
DD
X
f vs. V Characteristics
DD
TI
f [MHz]
X
1000
TIn input frequency f [kHz]
TI
0
1
2
3
4
5
V [V]
DD
6
7
500
100
50
High-speed mode [0011]
Medium-speed mode [0010]
Low-speed mode [0000]
HALT mode [0100]
Operation guaranteed
range
(V = 5.0 V, T = 25C)
DD
a
Supply current I [ A]
DD
PD75104A, 75108A
57
V vs. I (Ports 0 and 2 to 9) Characteristics
OL
OL
30
20
10
0
0
1
2
3
4
V [V]
OL
Low-level output current of port 0 and 2 to 9 I [mA]
OL
V vs. I (Ports 12 to 14) Characteristics
OL
OL
V = 6 V
DD
V = 5 V
DD
0
1
2
3
4
V [V]
OL
30
20
10
0
Low-level output current of ports 12 to 14 I [mA]
OL
V = 4 V
DD
V = 3 V
DD
DD
V = 4 V
V = 3 V
DD
V = 6 V
DD
V = 5 V
DD
PD75104A, 75108A
58
V vs. I (Ports 0 and 2 to 9) Characteristics
OH
OH
15
10
5
0
0
1
2
3
4
V - V [V]
DD
OH
High-level output current of port 0 and 2 to 9 I [mA]
OH
V = 6 V
DD
V = 5 V
DD
V = 4 V
DD
V = 3 V
DD
PD75104A, 75108A
59
14. PACKAGE DRAWINGS
N
A
M
F
B
48
49
32
K
L
64 PIN PLASTIC QFP ( 14)
64
1
17
16
33
D
C
detail of lead end
S
Q
55
P
M
I
H
J
G
P64GC-80-AB8-3
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
17.60.4
14.00.2
1.0
0.350.10
0.15
14.00.2
0.6930.016
0.039
0.039
0.006
0.031 (T.P.)
0.551
NOTE
M
N
0.10
0.15
1.80.2
0.8 (T.P.)
0.004
0.006
+0.004
0.003
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
0.0710.008
0.014
0.551
0.80.2
0.031
P
2.55
0.100
0.6930.016
17.60.4
1.0
+0.009
0.008
Q
0.10.1
0.0040.004
S
2.85 MAX.
0.112 MAX.
+0.10
0.05
+0.009
0.008
+0.004
0.005
+0.009
0.008
PD75104A, 75108A
60
Symbol for Recommended
Condition
Symbol for Recommended
Condition
15. RECOMMENDED SOLDERING CONDITIONS
It is recommended that
PD75104A, 75106A, and 75108A be soldered under the following conditions.
For details on the recommended soldering conditions, refer to Information Document "Semiconductor
Devices Mounting Manual" (IEI-616).
For other soldering methods and conditions, please consult NEC.
Table 15-1 Soldering Conditions of Surface Mount Type
(1)
PD75108AGC - xxx - AB8: 64-pin plastic QFP ( 14 mm)
Soldering Method
Soldering Conditions
Infrared Reflow
Package peak temperature: 230
C, time: 30 seconds max.
IR30-00-1
(210
C min.), number of times: 1
VPS
Package peak temperature: 215
C, time: 40 seconds max.
VP15-00-1
(200
C min.), number of times: 1
Wave Soldering
Soldering bath temperature: 260
C max., time: 10 seconds
WS60-00-1
max., number of times: 1,
pre-heating temperature: 120
C max. (package surface
temperature)
Pin Partial Heating
Pin temperature: 300
C max.,
--
time: 3 seconds max. (per side)
(2)
PD75104AGC - xxx - AB8: 64-pin plastic QFP ( 14 mm)
Soldering Method
Soldering Conditions
Infrared Reflow
Package peak temperature: 230
C, time: 30 seconds max.
IR30-162-1
(210
C min.), number of times: 1, number of days: 2 days
*
,
(afterwards, 16 hours of prebaking at 125
C is required.)
VPS
Package peak temperature: 215
C, time: 40 seconds max.
VP15-162-1
(200
C min.), number of times: 1, number of days: 2 days
*
,
(afterwards, 16 hours of prebaking at 125
C is required.)
Wave Soldering
Soldering bath temperature: 260
C max., time: 10 seconds
WS60-162-1
max., number of times: 1, pre-heating temperature: 120
C
max. (package surface temperature), number of days:
2 days
*
, (afterwards, 16 hours of prebaking at 125
C is
required.)
Pin Partial Heating
Pin temperature: 300
C max.,
--
time: 3 seconds max. (per side)
*:
This means the number of days after unpacking the dry pack. Storage conditions are 25
C and 65% RH max.
Caution: Do not use two or more soldering methods in combination (except the pin partial heating method).
Notice
A model that can be soldered under the more stringent conditions (infrared reflow peak temperature:
235
C, number of times: 2, and an extended number of days) is also available.
For details, consult NEC.
PD75104A,
75108A
61
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG THIS SERIES PRODUCTS
Item
PD75104
PD75106
PD75108
PD75112
PD75116
PD75104A
PD75108A
PD75P108B
PD75P116
Program Memory
Mask ROM
0000H-0FFFH
4096 x 8 bits
Data Memory
Instruction Set
Total
58
Input
I/O
Lines
Power-ON
Reset Circuit
Power-ON Flag
Provided (mask option)
Provided with BR !addr instruction except for PD75104 and 75104A
Not provided
Pin Connections
Mask ROM
0000H-177FH
6016 x 8 bits
Mask ROM
0000H-1F7FH
8064 x 8 bits
Mask ROM
0000H-2F7FH
12160 x 8 bits
Mask ROM
0000H-3F7FH
16256 x 8 bits
Mask ROM
0000H-0FFFH
4096 x 8 bits
Mask ROM
0000H-1F7FH
8064 x 8 bits
One-time PROM
0000H-1F7FH
8064 x 8 bits
One-time PROM
0000H-3F7FH
16256 x 8 bits
320 x 4 bits
Bank 0: 256 x 4
Bank 1: 64 x 4
Operating
Voltage Range
2.7 to 6.0 V
5V 10%
Package
64-pin plastic QFP (
64-pin plastic shrink DIP (750 mil)
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14
20 mm)
64-pin plastic QFP (14
20 mm)
14 mm)
I/O
CMOS I/O: 32
+12 V withstand open-drain output: 12
(pull-up resistor as mask option)
LED direct drive: 44
CMOS I/O: 32
(pull-up resistor as mask option: 24)
+12 V withstand open-drain output
: 12
(pull-up resistor as mask option)
LED direct drive: 44
CMOS I/O: 32
+12 V open-drain output: 12
LED direct drive: 44
CMOS input: 10
Comparator input: 4
CMOS input: 10
Comparator input: 4
CMOS input: 10
Comparator input: 4
(pull-up resistor as mask option: 4)
320 x 4 bits
Bank 0: 256 x 4
Bank 1: 64 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
512 x 4 bits
Bank 0: 256 x 4
Bank 1: 256 x 4
Depends on package. Only PD75P116 has V pin.
PP
PD75104A, 75108A
62
Hardware
IE-75000-R*
1
In-circuit emulator for 75X series
IE-75001-R
IE-75000-R-EM*
2
Emulation board for IE-75000-R and IE-75001-R
EP-75108AGC-R
Emulation prove for
PD75104AGC and 75108AGC. It is provided with a 64-
pin conversion socket, EV-9200GC-64
Software
IE Control Program
RA75X Relocatable
Assembler
*1: Maintenance product
2: Not provided with IE-75001-R.
3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function.
Remarks:
For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
APPENDIX B. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using
PD75108A:
EV-9200GC-64
Host machine
PC-9800 series (MS-DOS
TM
Ver.3.30 to Ver.5.00A*
3
)
IBM PC/AT
TM
(PC DOS
TM
Ver.3.1)
PD75104A, 75108A
63
APPENDIX C. RELATED DOCUMENTS
5
PD75104A, 75108A
64
[MEMO]
PD75104A, 75108A
65
STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled.
The insulation of the gates of the MOS device may be destroyed by a strong static charge.
Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,
or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use
grounding when assembling the MOS device system. Do not leave the MOS device on a plastic
plate and do not touch the pins of the device.
Handle boards on which MOS devices are mounted similarly .
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices.
Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow
through the device, causing the device to malfunction. Therefore, fix the input level of the device
by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an
output pin (whose timing is not specified), each pin should be connected to V
DD
or GND through
a resistor.
Refer to "Processing of Unused Pins" in the documents of each devices.
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application.
Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The
output status of pins, I/O setting, and register contents upon power application are not guaranteed.
However, the items defined for reset operation and mode setting are subject to guarantee after
the respective operations have been executed.
When using a device with a reset function, be sure to reset the device after power application.
GENERAL NOTES ON CMOS DEVICES
PD75104A, 75108A
66
[MEMO]
No p
art of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which
may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties b y or arising from use of a device described herein or any
other liability arising from use of such device. No license, either express, implied or otherwise, is granted
under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,
nuclear reactor control systems and life support systems. If customers intend to use NEC devices for
above applications or they intend to use "Standard" quality grade NEC devices for the applications not
intended by NEC, please contact our sales people in advance.
Application examples recommended by NEC Corporation
Standard:
Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime system, etc.
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.
M4 92.6
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