Document Outline
- COVER
- FEATURES
- APPLICATIONS
- ORDERING INFORMATION
- FUNCTION LIST
- 1. PIN CONFIGURATION (Top View)
- 2. BLOCK DIAGRAM
- 3. PIN FUNCTION
- 3.1 Port Pins
- 3.2 Non-port Pins
- 3.3 Pin Input/Output Circuits
- 3.4 Recommended Connection of Unused Pins
- 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
- 4.1 Differences between Mk I Mode and Mk II Mode
- 4.2 Setting Method of Stack Bank Select Register (SBS)
- 5. MEMORY CONFIGURATION
- 6. PERIPHERAL HARDWARE FUNCTION
- 6.1 Digital I/O Port
- 6.2 Clock Generator
- 6.3 Basic Interval Timer/Watchdog Timer
- 6.4 Timer Counter
- 6.5 Bit Sequential Buffer
- 7. INTERRUPT FUNCTION AND TEST FUNCTION
- 8. STANDBY FUNCTION
- 9. RESET FUNCTION
- 9.1 Configuration and Operation Status of Reset Function
- 9.2 Watchdog Flag (WDF), Key Return Flag (KRF)
- 10. MASK OPTION
- 11. INSTRUCTION SETS
- 12. ELECTRICAL SPECIFICATIONS
- 13. CHARACTERISTIC CURVES (REFERENCE VALUES)
- 14. PACKAGE DRAWINGS
- 15. RECOMMENDED SOLDERING CONDITIONS
- APPENDIX A. uPD754202, 75F4264 FUNCTION LIST
- APPENDIX B. DEVELOPMENT TOOLS
- APPENDIX C. RELATED DOCUMENTS
The
PD754202 is a member of the 75XL Series of 4-bit single-chip microcontrollers that enable data processing
equivalent to that of an 8-bit microcontroller.
It features expanded CPU functions compared to the 75X Series and enables high-speed, low-voltage operation
at 1.8 V, making it suitable for battery-driven applications.
The
PD754202(A) is a higher-reliability product compared to the
PD754202.
Detailed function descriptions, etc., are provided in the following user's manual. Be sure to read it
when designing.
PD754202 User's Manual: U11132E
FEATURES
Key return reset function for keyless entry
Low-voltage operation: V
DD
= 1.8 to 6.0 V
On-chip memory
Program memory (ROM): 2048
8 bits
Data memory (RAM)
: 128
4 bits
Variable instruction execution time useful for high-speed operation and power save
0.95, 1.91, 3.81, 15.3
s (at 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7
s (at 6.0-MHz operation)
Compact package (20-pin plastic shrink SOP (300 mil, 0.65-mm pitch))
APPLICATIONS
Automotive electronics such as keyless entry units
The
PD754202 and
PD754202(A) have different quality grades. Unless otherwise specified, descriptions in
this data sheet apply to the
PD754202.
MOS INTEGRATED CIRCUIT
PD754202, 754202(A)
Document No. U12181EJ1V0DS00 (1st edition)
Date Published May 1997 N
Printed in Japan
4-BIT SINGLE-CHIP MICROCONTROLLERS
1997
DATA SHEET
The information in this document is subject to change without notice.
2
PD754202, 754202(A)
ORDERING INFORMATION
Part Number
Package
Quality Grade
PD754202GS-
-BA5
20-pin plastic SOP (300 mil, 1.27-mm pitch)
Standard
PD754202GS-
-GJG
20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
Standard
PD754202GS(A)-
-BA5
20-pin plastic SOP (300 mil, 1.27-mm pitch)
Special
PD754202GS(A)-
-GJG
20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
Special
Remark
indicates the ROM code suffix.
Differences between
PD754202 and
PD754202(A)
Part Number
PD754202
PD754202(A)
Item
Quality grade
Standard
Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
3
PD754202, 754202(A)
FUNCTION LIST
Parameter
Function
Instruction execution time
0.95, 1.91, 3.81, 15.3
s (system clock: at 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7
s (system clock: at 6.0-MHz operation)
On-chip memory
ROM
2048
8 bits
RAM
128
4 bits
General-purpose register
4-bit manipulation: 8
4 banks
8-bit manipulation: 4
4 banks
I/O port
CMOS input
4 Mask option-specifiable on-chip pull-up resistor
CMOS input/output
9 Software-specifiable on-chip pull-up resistor connection
Total
13
Timer
4 channels
8-bit timer counter: 3 channels
(Usable as 16-bit timer counter)
Basic interval timer/watchdog timer: 1 channel
Bit sequential buffer (BSB)
16 bits
Vectored interrupt
External: 1, Internal: 4
Test input
External: 1 (key return reset function provided)
System clock oscillation circuit
Ceramic/crystal oscillation circuit
Standby function
STOP/HALT mode
Operating ambient temperature
T
A
= 40 to +85 C
Supply voltage
V
DD
= 1.8 to 6.0 V
Package
20-pin plastic SOP (300 mil, 1.27-mm pitch)
20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
4
PD754202, 754202(A)
CONTENTS
1.
PIN CONFIGURATION (Top View) .................................................................................................... 6
2.
BLOCK DIAGRAM ............................................................................................................................... 7
3.
PIN FUNCTION .................................................................................................................................... 8
3.1
Port Pins ...................................................................................................................................... 8
3.2
Non-port Pins .............................................................................................................................. 9
3.3
Pin Input/Output Circuits ......................................................................................................... 10
3.4
Recommended Connection of Unused Pins .......................................................................... 11
4.
SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ....................................... 12
4.1
Differences between Mk I Mode and Mk II Mode .................................................................... 12
4.2
Setting Method of Stack Bank Select Register (SBS) ........................................................... 13
5.
MEMORY CONFIGURATION ............................................................................................................ 14
6.
PERIPHERAL HARDWARE FUNCTION ......................................................................................... 17
6.1
Digital I/O Port ........................................................................................................................... 17
6.2
Clock Generator ........................................................................................................................ 17
6.3
Basic Interval Timer/Watchdog Timer ..................................................................................... 19
6.4
Timer Counter ........................................................................................................................... 20
6.5
Bit Sequential Buffer ................................................................................................................ 24
7. INTERRUPT FUNCTION AND TEST FUNCTION ........................................................................... 25
8.
STANDBY FUNCTION ....................................................................................................................... 27
9.
RESET FUNCTION ............................................................................................................................ 28
9.1
Configuration and Operation Status of Reset Function ........................................................ 28
9.2
Watchdog Flag (WDF), Key Return Flag (KRF) ...................................................................... 32
10. MASK OPTION .................................................................................................................................. 34
11. INSTRUCTION SETS ......................................................................................................................... 35
12. ELECTRICAL SPECIFICATIONS ...................................................................................................... 44
13. CHARACTERISTIC CURVES (REFERENCE VALUES) ................................................................ 53
14. PACKAGE DRAWINGS ...................................................................................................................... 55
15. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 57
5
PD754202, 754202(A)
APPENDIX A.
PD754202, 75F4264 FUNCTION LIST ..................................................................... 58
APPENDIX B. DEVELOPMENT TOOLS .............................................................................................. 59
APPENDIX C. RELATED DOCUMENTS .............................................................................................. 62
6
PD754202, 754202(A)
1. PIN CONFIGURATION (Top View)
20-pin plastic SOP (300 mil, 1.27-mm pitch)
PD754202GS-
-BA5
PD754202GS(A)-
-BA5
20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
PD754202GS-
-GJG
PD754202GS(A)-
-GJG
IC: Internally Connected (Connect directly to V
DD
)
Pin Identification
IC
:
Internally Connected
INT0
:
External Vectored Interrupt
KR4 to KR7
:
Key Return 4 to 7
KRREN
:
Key Return Reset Enable
P30 to P33
:
Port 3
P60 to P63
:
Port 6
P70 to P73
:
Port 7
P80
:
Port 8
PTO0 to PTO2 :
Programmable Timer Output 0 to 2
RESET
:
Reset
V
DD
:
Positive Power Supply
V
SS
:
Ground
X1, X2
:
System Clock (Ceramic/Crystal)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
X1
X2
V
SS
IC
V
DD
P60
P61/INT0
P62
P63
KRREN
P80
P30/PTO0
P31/PTO1
P32/PTO2
P33
P70/KR4
P71/KR5
P72/KR6
P73/KR7
7
PD754202, 754202(A)
2. BLOCK DIAGRAM
BASIC INTERVAL
TIMER/WATCHDOG
TIMER
8-BIT TIMER
COUNTER#0
8-BIT
TIMER
COUNTER#1
8-BIT
TIMER
COUNTER#2
CASCADED
16-BIT
TIMER
COUNTER
INTERRUPT
CONTROL
INTBT
RESET
INTT0
TOUT
INTT1
INTT2
PTO0/P30
PTO1/P31
PTO2/P32
INT0/P61
KR4/P70-
KR7/P73
ALU
PROGRAM COUNTER
PROGRAM MEMORY
(ROM)
2048
8 BITS
DECODE
AND
CONTROL
CY
SP (8)
SBS
BANK
GENERAL REG.
DATA MEMORY
(RAM)
128
4 BITS
PORT3
4
PORT6
4
PORT7
4
PORT8
1
BIT SEQ. BUFFER (16)
P30-P33
P60-P63
P70-P73
P80
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
STAND BY
CONTROL
f
X
/2
N
X1
X2
CPU CLOCK
IC
V
DD
V
SS
RESET
4
KRREN
8
PD754202, 754202(A)
3. PIN FUNCTION
3.1 Port Pins
Pin Name
Input/Output
Alternate
Function
8-bit
After Reset
I/O Circuit
Function
I/O
Type
Note
P30
Input/Output
PTO0
Input
E-B
P31
PTO1
P32
PTO2
P33
P60
Input/Output
Input
F -A
P61
INT0
P62
P63
P70
Input
KR4
Input
B -A
P71
KR5
P72
KR6
P73
KR7
P80
Input/Output
Input
F -A
Note Circled characters indicate Schmitt trigger input.
Programmable 4-bit input/output port
(PORT3).
This port can be specified input/output bit-
wise.
On-chip pull-up resistor can be specified by
software in 4-bit units.
Programmable 4-bit input/output port (PORT6).
This port can be specified input/output bit-wise.
On-chip pull-up resistor can be specified by
software in 4-bit units.
Noise eliminator can be selected on P61/
INT0.
4-bit input port (PORT7).
On-chip pull-up resistor can be specified
bit-wise (mask option).
1-bit input/output port (PORT8).
On-chip pull-up resistor can be specified by
software.
9
PD754202, 754202(A)
3.2 Non-port Pins
Pin Name
Input/Output
Alternate
Function
After Reset
I/O Circuit
Function
Type
Note
PTO0
Output
P30
Timer counter output
Input
E-B
PTO1
P31
PTO2
P32
INT0
Input
P61
Edge detection vectored Noise eliminator/
Input
F -A
interrupt input (detected asynchronous
edge is selectable) selectable
Noise eliminator
selectable
KR4 to KR7
Input
P70 to P73
Falling edge detection testable input
Input
B -A
KRREN
Input
Key return reset enable.
Input
B
When KRREN = high level in STOP mode, reset
signal is generated at falling edge of KRn.
X1
Input
System clock oscillation crystal/ceramic
connection pin.
X2
If using an external clock, input to X1 and reverse
input to X2.
RESET
Input
System reset input (low-level active).
B -A
Pull-up resistor can be incorporated on-chip
(mask option).
IC
Internally connected. Connect directly to V
DD
.
V
DD
Positive power supply
V
SS
Ground potential
Note
Circled characters indicate Schmitt trigger input.
10
PD754202, 754202(A)
3.3 Pin Input/Output Circuits
The
PD754202 pin input/output circuits are shown schematically.
TYPE A
TYPE B
TYPE D
TYPE E-B
TYPE B-A
TYPE F-A
V
DD
IN
P-ch
N-ch
data
output
disable
N-ch
P-ch
IN
OUT
V
DD
P-ch
output
disable
data
P.U.R.
enable
Type D
Type A
IN/OUT
V
DD
P.U.R. (Mask Option)
IN
V
DD
P.U.R.
P.U.R.
enable
P-ch
IN/OUT
Type D
Type B
output
disable
data
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
Schmitt trigger input with hysteresis characteristics
CMOS standard input buffer
Push-pull output that can be placed in output
high-impedance (both P-ch and N-ch off).
P.U.R.
V
DD
11
PD754202, 754202(A)
3.4 Recommended Connection of Unused Pins
Table 3-1. List of Recommended Connection of Unused Pins
Pin
Recommended Connecting Method
P30/PTO0
Input state : Independently connect to V
SS
or V
DD
via a resistor.
P31/PTO1
Output state: Leave open.
P32/PTO2
P33
P60
P61/INT0
P62
P63
P70/KR4
Connect to V
DD
.
P71/KR5
P72/KR6
P73/KR7
P80
Input state : Independently connect to V
SS
or V
DD
via a resistor.
Output state: Leave open.
KRREN
When this pin is connected to V
DD
, internal reset signal is gener-
ated at the falling edge of the KRn pin in the STOP mode.
When this pin is connected to V
SS
, internal reset signal is not
generated even if the falling edge of KRn pin is detected in the
STOP mode.
IC
Connect directly to V
DD
.
12
PD754202, 754202(A)
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Differences between Mk I Mode and Mk II Mode
The
PD754202 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The
mode can be switched by bit 3 of the stack bank select register (SBS).
Mk I mode :
Instructions are compatible with the 75X Series. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
Mk II mode:
Incompatible with 75X Series. Can be used in all the 75XL CPU's including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode
Mk II mode
Number of stack bytes
2 bytes
3 bytes
for subroutine instructions
BRA !addr1 instruction
Not available
Available
CALLA !addr1 instruction
CALL !addr instruction
3 machine cycles
4 machine cycles
CALLF !faddr instruction
2 machine cycles
3 machine cycles
Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL
Series. Therefore, this mode is effective for enhancing software compatibility with
products that have a program area of more than 16 Kbytes.
The number of stack bytes (usable area) during execution of subroutine call instruc-
tions increases by 1 byte per stack compared to the Mk I mode when the Mk II mode
is selected.
However, when the CALL !addr and CALL !faddr instructions are used, the machine
cycle becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on
RAM use efficiency and processing performance than on software compatibility, the
Mk I mode should be used.
13
PD754202, 754202(A)
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction.
When using the Mk I mode, the SBS must be initialized to 1000B at the beginning of a program. When using
the Mk II mode, it must be initialized to 0000B.
Figure 4-1. Stack Bank Select Register Format
SBS3
SBS2
SBS1
SBS0
3
2
1
0
Symbol
SBS
Address
F84H
0
0
0
1
0
Memory bank 0
Other than above setting prohibited
0 must be set in the bit 2 position.
Stack area specification
Mk II mode
Mk I mode
Mode switching specification
Caution Because SBS.3 is set to "1" after a RESET signal is generated, the CPU operates in the
Mk I mode. When executing an instruction in the Mk II mode, set SBS.3 to "0" to select
the Mk II mode.
14
PD754202, 754202(A)
5. MEMORY CONFIGURATION
Program Memory (ROM): 2048
8 bits (0000H-07FFH)
Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET
signal is generated are written. Reset start is possible from any address.
Addresses 0002H to 000DH
Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts
are written. Interrupt service can start from any address.
Addresses 0020H to 007FH
Table area referenced by the GETI instruction
Note
.
Note
The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the number of program steps.
Data Memory (RAM)
Data area: 128 words
4 bits (000H-07FH)
Peripheral hardware area: 128 words
4 bits (F80H-FFFH)
15
PD754202, 754202(A)
Figure 5-1. Program Memory Map
Note Can be used in Mk II mode only.
Remark In addition to the above, a branch can be made to an address with only the low-order 8 bits of the PC
changed by means of a BR PCDE or BR PCXA instruction.
7
6
0
MBE RBE
Internal reset start address (high-order 3 bits)
Internal reset start address
(low-order 8 bits)
MBE RBE
INTBT start address
(high-order 3 bits)
INTBT start address
(low-order 8 bits)
MBE RBE
INT0 start address
(high-order 3 bits)
INT0 start address
(low-order 8 bits)
MBE RBE
INTT0 start address
(high-order 3 bits)
INTT0 start address
(low-order 8 bits)
MBE RBE
INTT1/INTT2 start address (high-order 3 bits)
INTT1/INTT2 start address
(low-order 8 bits)
GETI instruction reference table
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
0020H
007FH
0080H
07FFH
CALLF !faddr instruction
entry address
Branch address of
BR !addr
BRCB !caddr
BR BCDE
BR BCXA
BRA !addr1
Note
CALL !addr
CALLA !addr1
Note
instructions
GETI branch/call
address
BR $addr instruction
relative branch address
(15 to 1, +2 to +16)
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
4
3
16
PD754202, 754202(A)
Figure 5-2. Data Memory Map
000H
01FH
020H
07FH
080H
0FFH
F80H
FFFH
128
4
Not incorporated
128
4
(96
4)
(32
4)
0
15
General-purpose
register area
Stack area
Data area
static RAM (128
4)
Peripheral hardware area
Data memory
Memory bank
17
PD754202, 754202(A)
6. PERIPHERAL HARDWARE FUNCTION
6.1 Digital I/O Port
The following two types of I/O ports are provided.
CMOS Input (PORT7)
:
4
CMOS Input/Output (PORT3, 6, 8) :
9
Total
13
Table 6-1. Types and Features of Digital Ports
Port Name
Function
Operation and Features
Remarks
PORT3
4-bit I/O
Can be set to input or output mode bit-wise.
Also used for PTO0 to PTO2
pins.
PORT6
Also used for INT0 pin.
PORT7
4-bit input
4-bit input only port
Also used for KR4 to KR7 pins.
On-chip pull-up resistor can be specified by mask
option bit-wise.
PORT8
1-bit I/O
Can be set to input or output mode bit-wise.
6.2 Clock Generator
The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown
in Figure 6-1.
The operation of the clock generator is set with the processor clock control register (PCC). The instruction
execution time can be changed as follows.
0.95, 1.91, 3.81, 15.3
s (system clock operating at 4.19 MHz)
0.67, 1.33, 2.67, 10.7
s (system clock operating at 6.0 MHz)
18
PD754202, 754202(A)
Figure 6-1. Clock Generator Block Diagram
Note
Instruction execution
Remarks 1.
f
X
: System clock frequency
2.
= CPU clock
3.
PCC: Processor Clock Control Register
4.
One clock cycle (t
CY
) of the CPU clock is equal to one machine cycle of the instruction.
X1
X2
System
clock
oscillator
Oscillation stops
1/2 1/41/16
f
X
Divider
1/4
HALT F/F
S
R
Q
S
R
Q
STOP F/F
PCC0
PCC1
PCC2
PCC3
PCC2,
PCC3
clear
HALT
Note
STOP
Note
Wait release signal from BT
Reset signal
Standby release signal from
interrupt control circuit
PCC
4
Basic interval timer (BT)
Timer counter
INT0 noise eliminator
1/1 to 1/4096
CPU
INT0 noise
eliminator
Divider
Selector
Internal bus
19
PD754202, 754202(A)
6.3 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions.
(a) Interval timer operation to generate a reference time interrupt
(b) Watchdog timer operation to detect a runaway of program and reset the CPU
(c) Selects and counts the wait time when the standby mode is released
(d) Reads the contents of counting
Figure 6-2. Basic Interval Timer/Watchdog Timer Block Diagram
Note Instruction execution
From clock
generator
f
X
/2
5
f
X
/2
7
f
X
/2
9
f
X
/2
12
MPX
BTM3 BTM2 BTM1 BTM0 BTM
4
SET1
Note
Internal bus
8
1
Basic interval timer
(8-bit frequency divider)
Clear
BT
Wait release signal
when standby is
released.
Set
Clear
3
WDTM
SET1
Note
Internal reset
signal
Vectored
interrupt
request signal
BT
interrupt
request flag
IRQBT
20
PD754202, 754202(A)
6.4 Timer Counter
The
PD754202 incorporates three timer counters. Its configuration is shown in Figures 6-3, 6-4, and 6-5. The
timer counter functions are shown below.
(a) Programmable interval timer operation
(b) Square wave output of any frequency to PTO0-PTO2 pins
(c) Count value read function
The timer counter can operate in the following four modes as set by the mode register.
Table 6-2. Mode List
Mode
Channel
Channel 0 Channel 1 Channel 2
TM11
TM10
TM21
TM20
8-bit timer counter mode
0
0
0
0
PWM pulse generator mode
0
0
0
1
16-bit timer counter mode
1
0
1
0
Carrier generator mode
0
0
1
1
Remark : Available
: Not available
21
PD754202, 754202(A)
Figure 6-3. Timer Counter (Channel 0) Block Diagram
TM06 TM05 TM04 TM03 TM02
0
0
TM0
SET1
Note
8
8
8
MPX
From clock
generator
Timer operation start
CP
Clear
Count register (8)
T0
8
8
Comparator (8)
Modulo register (8)
TMOD0
TOUT
F/F
Reset
TOE0
PORT3.0
PMGA bit 0
T0
enable flag
P30
output latch
Port 3
input/output
mode
Output buffer
P30/PTO0
INTT0
IRQT0
set signal
RESET
IRQT0
clear signal
Internal bus
Match
f
x
/2
4
f
x
/2
6
f
x
/2
8
f
x
/2
10
Note
Instruction execution
Caution Always set bits 0 and 1 to 0 when setting data to TM0.
22
PD754202, 754202(A)
Figure 6-4. Timer Counter (Channel 1) Block Diagram
8
8
8
8
TM15TM14TM13TM12TM11TM10
TM16
TM1
Decoder
MPX
Timer counter
(channel 2) output
From clock
generator
CP
Clear
T1
Count register (8)
Comparator (8)
Modulo register (8)
TMOD1
Timer operation start
16-bit timer counter mode
Selector
Match
Reset
TOUT
F/F
TOE1
PORT3.1
PMGA bit 1
T1
enable flag
P31
output latch
Port 3
input/output
mode
Output buffer
P31/PTO1
INTT1
IRQT1
set signal
RESET
IRQT1
clear signal
Timer counter (channel 2) match signal
(When 16-bit timer counter mode)
Timer counter (channel 2) comparator
(When 16-bit timer counter mode)
Timer counter (channel 2) reload signal
Internal bus
f
x
/2
5
f
x
/2
6
f
x
/2
8
f
x
/2
10
f
x
/2
12
SET1
Note
Note Instruction execution
23
PD754202, 754202(A)
Figure 6-5. Timer Counter (Channel 2) Block Diagram
Internal bus
8
8
8
8
8
8
8
TM25 TM24 TM23 TM22 TM21 TM20
TM26
MPX
Decoder
From clock
generator
CP
16-bit timer counter mode
Timer operation start
Count register (8)
Comparator (8)
MPX (8)
Match
TOUT
F/F
T2
High-level period
setting modulo register (8)
Modulo register (8)
Reset
TOE2 REMC NRZB NRZ
8
TMOD2
TMODH
TC2
Reload
Overflow
Carrier generator mode
PORT3.2 PMGA bit 2
P32
output
latch
Port 3
input/output
mode
Output buffer
P32/PTO2
Timer counter
(channel 1)
clock input
INTT2
IRQT2
set signal
RESET
IRQT2 clear signal
Timer counter (channel 1) match signal
(When 16-bit timer counter mode)
Timer counter (channel 1)
clear signal
(When 16-bit timer counter
mode)
Timer counter (channel 1) match signal
(When carrier generator mode)
TM2
Clear
Selector
Selector
f
x
f
x
/2
f
x
/2
4
f
x
/2
6
f
x
/2
8
f
x
/2
10
SET1
Note
0
Note Instruction execution
Caution Always set bit 7 to 0 when setting data to TC2.
24
PD754202, 754202(A)
6.5 Bit Sequential Buffer ....... 16 Bits
The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be
easily performed by changing the address specification and bit specification in sequence, therefore it is useful
when processing large data bit-wise.
Figure 6-6. Bit Sequential Buffer Format
Remarks 1.
In the pmem.@L addressing, the specified bit moves corresponding to the L register.
2.
In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification.
Address
Bit
Symbol
L register
L = FH
L = CH L = BH
L = 8H L = 7H
L = 4H L = 3H
L = 0H
DECS L
INCS L
BSB3
BSB2
BSB1
BSB0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
FC3H
FC2H
FC1H
FC0H
25
PD754202, 754202(A)
7. INTERRUPT FUNCTION AND TEST FUNCTION
The
PD754202 is provided with five types of interrupt sources and one test source to enable a variety of
applications.
The interrupt control circuit of the
PD754202 has the following functions.
(1) Interrupt function
Vectored interrupt function for hardware control, enabling/disabling the interrupt acknowledgement by
the interrupt enable flag (IE
) and interrupt master enable flag (IME).
Can set any interrupt start address.
Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register
(IPS).
Test function of interrupt request flag (IRQ
). An interrupt generated can be checked by software.
Release the standby mode. The interrupt to be released can be selected by the interrupt enable flag.
(2) Test function
Test request flag (IRQ2) generation can be checked by software.
Release the standby mode. The test source to be released can be selected by the test enable flag.
26
PD754202, 754202(A)
Figure 7-1. Interrupt Control Circuit Block Diagram
Internal bus
Interrupt enable flag (IE
)
2
4
IM2
IM0
Note1
Edge
detector
INT0/P61
INTBT
INTT0
INTT1
INTT2
IRQBT
IRQ0
IRQT0
IRQT1
IRQT2
IRQ2
KR4/P70
KR7/P73
Falling edge
detector
Note 2
Key return reset circuit
IM2
IME
IPS
IST1
IST0
Decoder
VRQn
Priority control
circuit
Standby release
signal
Selector
Vector table
address
generator
Notes 1.
Noise eliminator (Standby release is disabled when noise eliminator is selected.)
2.
The INT2 pin is not available. Interrupt request flag (IRQ2) is set at the KRn pin falling edge when IM20 = 1 and IM21 = 0.
27
PD754202, 754202(A)
8. STANDBY FUNCTION
In order to reduce power dissipation while a program is in standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the
PD754202.
Table 8-1. Operation Status in Standby Mode
Item
Mode
STOP mode
HALT mode
Set instruction
STOP instruction
HALT instruction
Operation
Clock generator
Operation stops.
Only the CPU clock
halts (oscillation
status
continues).
Basic interval timer/
Operation stops.
Operable
watchdog timer
BT mode : The IRQBT is set in the
reference time interval.
WT mode: Reset signal generation
by BT overflow.
Timer counter
Operation stops.
Operable.
External interrupt
The INT0 is not operable
Note
.
The INT2 is operable at the falling edge of KRn.
CPU
Operation stops.
Release signal
Reset signal
Reset signal
Interrupt request signal sent from
Interrupt request signal sent from
interrupt enabled hardware
interrupt enabled hardware
System reset signal (key return reset)
generated by KRn falling edge when
KRREN pin = 1.
Note
Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode
register (IM0).
28
PD754202, 754202(A)
9. RESET FUNCTION
9.1 Configuration and Operation Status of Reset Function
There are three kinds of reset input: the external reset signal (RESET), the reset signal sent from the basic
interval/watchdog timer, and the reset signal generated by a falling edge signal from KRn in the STOP mode. When
any of these reset signals is input, an internal reset signal is generated. The configuration is shown in Figure
9-1.
Figure 9-1. Configuration of Reset Function
V
DD
Mask option
KRREN
RESET
Q R
S
Q
S
R
Q
S
R
Instruction
STOP mode
KRF
WDF
Watchdog timer overflow
Internal reset signal
Instruction
V
DD
Mask option
P70/KR4
P71/KR5
P72/KR6
P73/KR7
Internal bus
Falling edge detector
Interrupt
One-shot pulse generator
29
PD754202, 754202(A)
The RESET signal generation initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing
chart of the reset operation.
Figure 9-2. Reset Operation by RESET Signal Generation
Note
The following 2 time modes can be specified with mask option.
2
17
/f
x
(21.8 ms: at 6.0-MHz operation, 31.3 ms: at 4.19-MHz operation)
2
15
/f
x
(5.46 ms: at 6.0-MHz operation, 7.81 ms: at 4.19-MHz operation)
Operation mode or
standby mode
Wait
Note
RESET
signal
generated
Operation mode
HALT mode
Internal reset operation
30
PD754202, 754202(A)
Table 9-1. Hardware Status After Reset (1/3)
Hardware
RESET signal generation
RESET signal generation
in the standby mode
in operation
Program counter (PC)
Sets the low-order 3 bits of
Sets the low-order 3 bits of
program memory's address
program memory's address
0000H to the PC10-PC8 and the
0000H to the PC10-PC8 and the
contents of address 0001H to
contents of address 0001H to
the PC7-PC0.
the PC7-PC0.
PSW
Carry flag (CY)
Held
Undefined
Skip flag (SK0-SK2)
0
0
Interrupt status flag (IST0, IST1)
0
0
Bank enable flag (MBE, RBE)
Sets the bit 6 of program
Sets the bit 6 of program
memory's address 0000H to
memory's address 0000H to
the RBE and bit 7 to the MBE.
the RBE and bit 7 to the MBE.
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
1000B
1000B
Data memory (RAM)
Held
Undefined
General-purpose register (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
0, 0
Basic interval
Counter (BT)
Undefined
Undefined
timer/watchdog
Mode register (BTM)
0
0
timer
Watchdog timer enable flag (WDTM)
0
0
Timer counter
Counter (T0)
0
0
(T0)
Modulo register (TMOD0)
FFH
FFH
Mode register (TM0)
0
0
TOE0, TOUT F/F
0, 0
0, 0
Timer counter
Counter (T1)
0
0
(T1)
Modulo register (TMOD1)
FFH
FFH
Mode register (TM1)
0
0
TOE1, TOUT F/F
0, 0
0, 0
Timer counter
Counter (T2)
0
0
(T2)
Modulo register (TMOD2)
FFH
FFH
High-level period setting modulo
FFH
FFH
register (TMOD2H)
Mode register (TM2)
0
0
TOE2, TOUT F/F
0, 0
0, 0
REMC, NRZ, NRZB
0, 0, 0
0, 0, 0
31
PD754202, 754202(A)
Table 9-1. Hardware Status After Reset (2/3)
Hardware
RESET signal generation
RESET signal generation
in the standby mode
in operation
Clock generator
Processor clock control register (PCC)
0
0
Interrupt
Interrupt request flag (IRQ
)
Reset (0)
Reset (0)
function
Interrupt enable flag (IE
)
0
0
Interrupt master enable flag (IME)
0
0
Interrupt priority selection register (IPS)
0
0
INT0, 2 mode registers (IM0, IM2)
0, 0
0, 0
Digital port
Output buffer
Off
Off
Output latch
Cleared (0)
Cleared (0)
I/O mode registers (PMGA, PMGC)
0
0
Pull-up resistor setting register (POGA, POGB)
0
0
Bit sequential buffer (BSB0-BSB3)
Held
Undefined
Table 9-1. Hardware Status After Reset (3/3)
RESET signal
RESET signal
RESET signal
RESET signal
Hardware
generation by key
generation in the
generation by WDT
generation during
return reset
standby mode
during operation
operation
Watchdog flag (WDF)
Hold the previous status
0
1
0
Key return flag (KRF)
1
0
Hold the previous status
0
32
PD754202, 754202(A)
9.2 Watchdog Flag (WDF), Key Return Flag (KRF)
The WDF is set by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by the
KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset signal
is generated.
As the WDF and KRF are cleared only by external signal or instruction execution, if once these flags are set,
they are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the
contents of WDF and KRF after reset start operation by executing SKTCLR instruction and so on.
Table 9-2 lists the contents of WDF and KRF corresponding to each signal. Figure 9-3 shows the WDF operation
in generating each signal, and Figure 9-4 shows the KRF operation in generating each signal.
Table 9-2. WDF and KRF Contents Correspond to Each Signal
External RESET
Reset signal
Reset signal
WDF clear
KRF clear
Hardware
signal generation
generation by watch-
generation by the
instruction
instruction
dog timer overflow
KRn input
execution
execution
Watchdog flag (WDF)
0
1
Hold
0
Hold
Key return flag (KRF)
0
Hold
1
Hold
0
Figure 9-3. WDF Operation in Generating Each Signal
External RESET
WDF
Operation mode
Reset signal generation by
watchdog timer overflow
External RESET
signal generation
WDF clear
instruction
execution
Operation mode
HALT
mode
Operation
mode
HALT
mode
Operation
mode
HALT
mode
Operation mode
Internal reset operation
Internal reset operation
Internal reset operation
Reset signal generation by
watchdog timer overflow
33
PD754202, 754202(A)
Figure 9-4. KRF Operation in Generating Each Signal
External RESET
KRF
Operation mode
Operation mode
HALT
mode
Operation
mode
Internal reset operation
STOP
mode
Internal reset operation
Internal reset operation
HALT
mode
Operation
mode
STOP
mode
HALT
mode
Operation mode
STOP instruction
execution
Reset signal
generation by
the KRn input
External RESET
signal generation
STOP instruction
execution
KRF clear instruction
execution
Reset signal
generation by
the KRn input
34
PD754202, 754202(A)
10. MASK OPTION
The
PD754202 has the following mask options:
Mask option of P70/KR4 through P73/KR7
Pull-up resistors can be connected to these pins.
(1) No pull-up resistor connection
(2) Connection of a 30-k
(typ.) pull-up resistor in 1-bit units.
(3) Connection of a 100-k
(typ.) pull-up resistor in 1-bit units.
Mask option of RESET pin
Pull-up resistors can be connected to these pins.
(1) No pull-up resistor connection
(2) Connection of a 100-k
(typ.) pull-up resistor.
Standby function mask option
The wait time after RESET signal can be selected.
(1) 2
17
/f
x
(21.8 ms: f
x
= 6.0-MHz operation, 31.3 ms: f
x
= 4.19-MHz operation)
(2) 2
15
/f
x
(5.46 ms: f
x
= 6.0-MHz operation, 7.81 ms: f
x
= 4.19-MHz operation)
35
PD754202, 754202(A)
11. INSTRUCTION SETS
(1) Expression formats and description methods of operands
The operand is described in the operand column of each instruction in accordance with the description
method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER
PACKAGE USERS' MANUAL -- LANGUAGE (EEU-1363)". If there are several elements, one of them
is selected. Capital letters and the + and symbols are key words and are described as they are.
For immediate data, appropriate numbers and labels are described.
Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described.
However, there are restrictions in the labels that can be described for fmem and pmem. For details, see
PD754202 User's Manual (U11132E).
Expression
Description method
format
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp'
XA, BC, DE, HL, XA', BC', DE', HL'
rp'1
BC, DE, HL, XA', BC', DE', HL'
rpa
HL, HL+, HL, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or label
Note
bit
2-bit immediate data or label
fmem
FB0H-FBFH, FF0H-FFFH immediate data or label
pmem
FC0H-FFFH immediate data or label
addr
0000H-07FFH immediate data or label
addr1(only in
0000H-07FFH immediate data or label
Mk II mode)
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H-7FH immediate data (where bit0 = 0) or label
PORTn
PORT3, 6, 7, 8
IE
IEBT, IET0-IET2, IE0, IE2
RBn
RB0-RB3
MBn
MB0, MB15
Note mem can be only used for even address in 8-bit data processing.
36
PD754202, 754202(A)
(2) Legend in explanation of operation
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: XA register pair; 8-bit accumulator
BC
: BC register pair
DE
: DE register pair
HL
: HL register pair
XA'
: XA' extended register pair
BC'
: BC' extended register pair
DE'
: DE' extended register pair
HL'
: HL' extended register pair
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn
: Port n (n = 3, 6, 7, 8)
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IE
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Separation between address and bit
(
)
: The contents addressed by
H
: Hexadecimal data
37
PD754202, 754202(A)
(3) Explanation of symbols under addressing area column
*1
MB = MBEMBS
(MBS = 0, 15)
*2
MB = 0
*3
MBE = 0 : MB = 0 (000H-07FH)
MB = 15 (F80H-FFFH)
Data memory addressing
MBE = 1 : MB = MBS (MBS = 0, 15)
*4
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
*5
MB = 15, pmem = FC0H-FFFH
*6
addr = 0000H-07FFH
*7
addr
= (Current PC) 15 to (Current PC) 1
(Current PC) + 2 to (Current PC) + 16
addr1 = (Current PC) 15 to (Current PC) 1
(Current PC) + 2 to (Current PC) + 16
Program memory addressing
*8
caddr = 0000H-07FFH
*9
faddr = 0000H-07FFH
*10
taddr = 0020H-007FH
*11
addr1 = 0000H-07FFH
Remarks 1.
MB indicates memory bank that can be accessed.
2.
In *2, MB = 0 independently of how MBE and MBS are set.
3.
In *4 and *5, MB = 15 independently of how MBE and MBS are set.
4.
*6 to *11 indicate the areas that can be addressed.
(4) Explanation of number of machine cycles column
S denotes the number of machine cycles required by skip operation when a skip instruction is executed.
The value of S varies as follows.
When no skip is made: S = 0
When the skipped instruction is a 1- or 2-byte instruction: S = 1
When the skipped instruction is a 3-byte instruction
Note
: S = 2
Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction
Caution The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle of the CPU clock (= t
CY
); time can be selected from among four
types by setting PCC.
38
PD754202, 754202(A)
Instruction
Number
Number
Addressing
Mnemonic
Operand
of machine
Operation
Skip condition
group
of bytes
cycles
area
Transfer
MOV
A, #n4
1
1
A
n4
String effect A
instruction
reg1, #n4
2
2
reg1
n4
XA, #n8
2
2
XA
n8
String effect A
HL, #n8
2
2
HL
n8
String effect B
rp2, #n8
2
2
rp2
n8
A, @HL
1
1
A
(HL)
*1
A, @HL+
1
2+S
A
(HL), then L
L+1
*1
L = 0
A, @HL
1
2+S
A
(HL), then L
L1
*1
L = FH
A, @rpa1
1
1
A
(rpa1)
*2
XA, @HL
2
2
XA
(HL)
*1
@HL, A
1
1
(HL)
A
*1
@HL, XA
2
2
(HL)
XA
*1
A, mem
2
2
A
(mem)
*3
XA, mem
2
2
XA
(mem)
*3
mem, A
2
2
(mem)
A
*3
mem, XA
2
2
(mem)
XA
*3
A, reg
2
2
A
reg
XA, rp'
2
2
XA
rp'
reg1, A
2
2
reg1
A
rp'1, XA
2
2
rp'1
XA
XCH
A, @HL
1
1
A
(HL)
*1
A, @HL+
1
2+S
A
(HL), then L
L+1
*1
L = 0
A, @HL
1
2+S
A
(HL), then L
L1
*1
L = FH
A, @rpa1
1
1
A
(rpa1)
*2
XA, @HL
2
2
XA
(HL)
*1
A, mem
2
2
A
(mem)
*3
XA, mem
2
2
XA
(mem)
*3
A, reg1
1
1
A
reg1
XA, rp'
2
2
XA
rp'
Table
MOVT
XA, @PCDE
1
3
XA
(PC
108
+DE)
ROM
reference
instructions
XA, @PCXA
1
3
XA
(PC
108
+XA)
ROM
XA, @BCDE
1
3
XA
(BCDE)
ROM
Note
*6
XA, @BCXA
1
3
XA
(BCXA)
ROM
Note
*6
Note
"0" must be set to the B register.
39
PD754202, 754202(A)
Instruction
Number
Number
Addressing
Mnemonic
Operand
of machine
Operation
Skip condition
group
of bytes
cycles
area
Bit transfer
MOV1
CY, fmem.bit
2
2
CY
(fmem.bit)
*4
instructions
CY, pmem.@L
2
2
CY
(pmem
72
+L
32
.bit(L
10
))
*5
CY, @H+mem.bit
2
2
CY
(H+mem
30
.bit)
*1
fmem.bit, CY
2
2
(fmem.bit)
CY
*4
pmem.@L, CY
2
2
(pmem
72
+L
32
.bit(L
10
))
CY
*5
@H+mem.bit, CY
2
2
(H+mem
30
.bit)
CY
*1
Operation
ADDS
A, #n4
1
1+S
A
A+n4
carry
instructions
XA, #n8
2
2+S
XA
XA+n8
carry
A, @HL
1
1+S
A
A+(HL)
*1
carry
XA, rp'
2
2+S
XA
XA+rp'
carry
rp'1, XA
2
2+S
rp'1
rp'1+XA
carry
ADDC
A, @HL
1
1
A, CY
A+(HL)+CY
*1
XA, rp'
2
2
XA, CY
XA+rp'+CY
rp'1, XA
2
2
rp'1, CY
rp'1+XA+CY
SUBS
A, @HL
1
1+S
A
A(HL)
*1
borrow
XA, rp'
2
2+S
XA
XArp'
borrow
rp'1, XA
2
2+S
rp'1
rp'1XA
borrow
SUBC
A, @HL
1
1
A, CY
A(HL)CY
*1
XA, rp'
2
2
XA, CY
XArp'CY
rp'1, XA
2
2
rp'1, CY
rp'1XACY
AND
A, #n4
2
2
A
A
n4
A, @HL
1
1
A
A
(HL)
*1
XA, rp'
2
2
XA
XA
rp'
rp'1, XA
2
2
rp'1
rp'1
XA
OR
A, #n4
2
2
A
A
n4
A, @HL
1
1
A
A
(HL)
*1
XA, rp'
2
2
XA
XA
rp'
rp'1, XA
2
2
rp'1
rp'1
XA
XOR
A, #n4
2
2
A
A v n4
A, @HL
1
1
A
A v (HL)
*1
XA, rp'
2
2
XA
XA v rp'
rp'1, XA
2
2
rp'1
rp'1 v XA
Accumulator
RORC
A
1
1
CY
A
0
, A
3
CY, A
n1
A
n
manipulation
instructions
NOT
A
2
2
A
A
40
PD754202, 754202(A)
Instruction
Number
Number
Addressing
Mnemonic
Operand
of machine
Operation
Skip condition
group
of bytes
cycles
area
Increment
INCS
reg
1
1+S
reg
reg+1
reg = 0
and
Decrement
rp1
1
1+S
rp1
rp1+1
rp1 = 00H
instructions
@HL
2
2+S
(HL)
(HL)+1
*1
(HL) = 0
mem
2
2+S
(mem)
(mem)+1
*3
(mem) = 0
DECS
reg
1
1+S
reg
reg1
reg = FH
rp'
2
2+S
rp'
rp'1
rp' = FFH
Comparison
SKE
reg, #n4
2
2+S
Skip if reg = n4
reg = n4
instruction
@HL, #n4
1
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
2
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A = reg
XA, rp'
2
2+S
Skip if XA = rp'
XA = rp'
Carry flag
SET1
CY
1
1
CY
1
manipulation
instruction
CLR1
CY
1
1
CY
0
SKT
CY
1
1+S
Skip if CY = 1
CY = 1
NOT1
CY
1
1
CY
CY
Memory bit
SET1
mem.bit
2
2
(mem.bit)
1
*3
manipulation
instructions
fmem.bit
2
2
(fmem.bit)
1
*4
pmem.@L
2
2
(pmem
72
+L
32
.bit(L
10
))
1
*5
@H+mem.bit
2
2
(H+mem
30
.bit)
1
*1
CLR1
mem.bit
2
2
(mem.bit)
0
*3
fmem.bit
2
2
(fmem.bit)
0
*4
pmem.@L
2
2
(pmem
72
+L
32
.bit(L
10
))
0
*5
@H+mem.bit
2
2
(H+mem
30
.bit)
0
*1
SKT
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem
72
+L
32
.bit(L
10
)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem
30
.bit) = 1
*1
(@H+mem.bit) = 1
SKF
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem
72
+L
32
.bit(L
10
)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2+S
Skip if (H+mem
30
.bit) = 0
*1
(@H+mem.bit) = 0
41
PD754202, 754202(A)
Instruction
Number
Number
Addressing
Mnemonic
Operand
of machine
Operation
Skip condition
group
of bytes
cycles
area
Memory bit
SKTCLR
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
manipulation
instructions
pmem.@L
2
2+S
Skip if (pmem
72
+L
32
.bit(L
10
)) = 1 and clear
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem
30
.bit) = 1 and clear
*1
(@H+mem.bit) = 1
AND1
CY, fmem.bit
2
2
CY
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
(pmem
72
+L
32
.bit(L
10
))
*5
CY, @H+mem.bit
2
2
CY
CY
(H+mem
30
.bit)
*1
OR1
CY, fmem.bit
2
2
CY
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
(pmem
72
+L
32
.bit(L
10
))
*5
CY, @H+mem.bit
2
2
CY
CY
(H+mem
30
.bit)
*1
XOR1
CY, fmem.bit
2
2
CY
CY v (fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY v (pmem
72
+L
32
.bit(L
10
))
*5
CY, @H+mem.bit
2
2
CY
CY v (H+mem
30
.bit)
*1
Branch
BR
Note 1
addr
PC
100
addr
*6
instructions
Select appropriate instruction among
BR !addr, BRCB !caddr, and BR $addr
according to the assembler being used.
addr1
PC
10-0
addr1
*11
Select appropriate instruction among
BR !addr, BRA !addr1, BRCB !caddr, and
BR $addr1 according to the assembler
being used.
!addr
3
3
PC
100
addr
*6
$addr
1
2
PC
100
addr
*7
$addr1
1
2
PC
100
addr1
PCDE
2
3
PC
100
PC
10-8
+DE
PCXA
2
3
PC
100
PC
10-8
+XA
BCDE
2
3
PC
100
BCDE
Note 2
*6
BCXA
2
3
PC
100
BCXA
Note 2
*6
BRA
Note 1
!addr1
3
3
PC
100
addr1
*11
BRCB
!caddr
2
2
PC
100
caddr
100
*8
Notes 1.
The above operations in the shaded boxes can be performed only in the Mk II mode. The other
operations can be performed only in the MK I mode.
2.
"0" must be set to the B register.
42
PD754202, 754202(A)
Instruction
Number
Number
Addressing
Mnemonic
Operand
of machine
Operation
Skip condition
group
of bytes
cycles
area
Subroutine
CALLA
Note
!addr1
3
3
(SP2)
,
, MBE, RBE
*11
stack control
(SP6) (SP3) (SP4)
0, PC
100
instructions
(SP5)
0, 0, 0, 0
PC
100
addr1, SP
SP6
CALL
Note
!addr
3
3
(SP3)
MBE, RBE, 0, 0
*6
(SP4) (SP1) (SP2)
0, PC
100
PC
100
addr, SP
SP4
4
(SP2)
,
, MBE, RBE
(SP6) (SP3) (SP4)
0, PC
100
(SP5)
0, 0, 0, 0
PC
100
addr, SP
SP6
CALLF
Note
!faddr
2
2
(SP3)
MBE, RBE, 0, 0
*9
(SP4) (SP1) (SP2)
0, PC
100
PC
100
0+faddr, SP
SP4
3
(SP2)
,
, MBE, RBE
(SP6) (SP3) (SP4)
0, PC
100
(SP5)
0, 0, 0, 0
PC
100
0+faddr, SP
SP6
RET
Note
1
3
PC
100
(SP)
20
(SP+3) (SP+2)
MBE, RBE, 0, 0
(SP+1), SP
SP+4
,
, MBE, RBE
(SP+4)
0, 0, 0, 0,
(SP+1)
PC
100
(SP)
20
(SP+3) (SP+2), SP
SP+6
RETS
Note
1
3+S
MBE, RBE, 0, 0
(SP+1)
Unconditional
PC
100
(SP)
20
(SP+3) (SP+2)
SP
SP+4
then skip unconditionally
0, 0, 0, 0
(SP+1)
PC
100
(SP)
20
(SP+3) (SP+2)
,
, MBE, RBE
(SP+4)
SP
SP+6
then skip unconditionally
RETI
Note
1
3
MBE, RBE, 0, 0
(SP+1)
PC
100
(SP)
20
(SP+3) (SP+2)
PSW
(SP+4) (SP+5), SP
SP+6
0, 0, 0, 0
(SP+1)
PC
100
(SP)
20
(SP+3) (SP+2)
PSW
(SP+4) (SP+5), SP
SP+6
PUSH
rp
1
1
(SP1) (SP2)
rp, SP
SP2
BS
2
2
(SP1)
MBS, (SP2)
RBS, SP
SP2
POP
rp
1
1
rp
(SP+1) (SP), SP
SP+2
BS
2
2
MBS
(SP+1), RBS
(SP), SP
SP+2
Note
The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations
can be performed only in the Mk I mode.
43
PD754202, 754202(A)
Instruction
Number
Number
Addressing
Mnemonic
Operand
of machine
Operation
Skip condition
group
of bytes
cycles
area
Interrupt
EI
2
2
IME (IPS.3)
1
control
instructions
IE
2
2
IE
1
DI
2
2
IME (IPS.3)
0
IE
2
2
IE
0
Input/output
IN
Note 1
A, PORTn
2
2
A
PORTn
(n = 3, 6, 7, 8)
instructions
OUT
Note 1
PORTn, A
2
2
PORTn
A
(n = 3, 6, 8)
CPU control
HALT
2
2
Set HALT Mode (PCC.2
1)
instructions
STOP
2
2
Set STOP Mode (PCC.3
1)
NOP
1
1
No Operation
Special
SEL
RBn
2
2
RBS
n
(n = 0-3)
instructions
MBn
2
2
MBS
n
(n = 0, 15)
GETI
Notes 2, 3
taddr
1
3
When TBR instruction
*10
PC
100
(taddr)
20
+ (taddr+1)
When TCALL instruction
(SP4) (SP1) (SP2)
0, PC
100
(SP3)
MBE, RBE, 0, 0
PC
100
(taddr)
20
+ (taddr+1)
SP
SP4
When instruction other than TBR and
Depending on
TCALL instructions
the reference
(taddr) (taddr+1) instruction is executed.
instruction
3
When TBR instruction
*10
PC
100
(taddr)
20
+ (taddr+1)
4
When TCALL instruction
(SP6) (SP3) (SP4)
PC
100
(SP5)
0, 0, 0, 0
(SP2)
,
, MBE, RBE
PC
100
(taddr)
20
+ (taddr+1)
SP
SP6
3
When instruction other than TBR and
Depending on
TCALL instructions
the reference
(taddr) (taddr+1) instruction is executed.
instruction
Notes 1.
While the IN instruction and OUT instruction are being executed, MBS must be set to 0, or MBE must
be set to 1 and MBS must be set to 15.
2.
The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI
instruction.
3.
The above operations in the shaded boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.
44
PD754202, 754202(A)
12. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25
C)
Parameter
Symbol
Test Conditions
Ratings
Unit
Supply voltage
V
DD
0.3 to +7.0
V
Input voltage
V
I
0.3 to V
DD
+ 0.3
V
Output voltage
V
O
0.3 to V
DD
+ 0.3
V
Output current, high
I
OH
Per pin Pins except P32
10
mA
Only P32
20
mA
All pins total
30
mA
Output current, low
I
OL
Per pin
20
mA
All pins total
90
mA
Operating ambient
T
A
40 to +85
C
temperature
Storage temperature
T
stg
65 to +150
C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality
of the product may be impaired. The absolute maximum ratings are values that may physically
damage the products. Be sure to use the products within the ratings.
Capacitance (T
A
= 25
C, V
DD
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
f = 1 MHz
15
pF
Output capacitance
C
OUT
Unmeasured pins returned to 0 V
15
pF
I/O capacitance
C
IO
15
pF
45
PD754202, 754202(A)
X1
X2
X1
X2
C1
C2
X1
X2
C1
C2
System Clock Oscillator Characteristics (T
A
= 40 to +85
C, V
DD
= 1.8 to 6.0 V)
Resonator
Recommended Constant
Parameter
Testing Conditions
MIN.
TYP.
MAX.
Unit
Ceramic
Oscillation
1.0
6.0
Note 2
MHz
resonator
frequency (f
X
)
Note 1
Oscillation
After V
DD
reaches MIN.
4
ms
stabilization
value of oscillation
time
Note 3
voltage range
Crystal
Oscillation
1.0
6.0
Note 2
MHz
resonator
frequency(f
X
)
Note 1
Oscillation
V
DD
= 4.5 to 6.0 V
10
ms
stabilization time
Note 3
30
ms
External
X1 input
1.0
6.0
Note 2
MHz
clock
frequency (f
X
)
Note 1
X1 input high- and
83.3
500
ns
low-level widths
(t
XH
, t
XL
)
Notes 1.
Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Charac-
teristics.
2.
If the oscillation frequency is 4.19 MHz < f
X
6.0 MHz at 1.8 V
V
DD
< 2.7 V, set the processor clock
control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated machine cycle
time of 0.95
s is not satisfied.
3.
The oscillation stabilization time is the time required for oscillation to stabilize after application of V
DD
,
or after the STOP mode has been released.
Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines
in the figures as follows to avoid adverse influences on the wiring capacitance:
Keep the wire length as short as possible.
Do not cross other signal lines.
Do not route the wiring in the vicinity of lines though which a high fluctuating current flows.
Always keep the ground point of the capacitor of the oscillation circuit as the same potential
as V
SS
.
Do not connect the power source pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
46
PD754202, 754202(A)
RECOMMENDED CIRCUIT CONSTANTS
Ceramic Resonator (T
A
= 20 to +80 C)
Circuit constant (pF)
Oscillation voltage
Manufacturer
Product
Frequency
range (V
DD
)
Remark
(MHz)
C1
C2
MIN.(V)
MAX.(V)
Murata Mfg.
CSB1000J
Note
1.0
100
100
2.0
6.0
Rd = 2.2 k
Co., Ltd.
CSA2.00MG040
2.0
100
100
CST2.00MG040
Capacitor incorporated
CSA4.00MG
4.0
30
30
CST4.00MGW
Capacitor incorporated
CSA4.00MGU
30
30
1.8
CST4.00MGWU
Capacitor incorporated
CSA4.19MG
4.19
30
30
2.0
CST4.19MGW
Capacitor incorporated
CSA4.19MGU
30
30
1.8
CST4.19MGWU
Capacitor incorporated
CSA6.00MG
6.0
30
30
2.9
CST6.00MGW
Capacitor incorporated
CSA6.00MGU
30
30
2.4
CST6.00MGWU
Capacitor incorporated
Kyocera Corp.
KBR-1000F/Y
1.0
100
100
1.8
6.0
KBR-2.0MS
2.0
68
68
2.0
KBR-4.19MKC
4.19
1.8
Capacitor incorporated
KBR-4.19MSB
33
33
PBRC4.19A
PBRC4.19B
Capacitor incorporated
KBR-6.0MKC
6.0
KBR-6.0MSB
33
33
PBRC6.00A
PBRC6.00B
Capacitor incorporated
Note
If using Murata's CSB1000J (1.0 MHz) as the ceramic resonator, a limited resistor (Rd = 2.2 k
) is required
(see figure below). If using any other recommended resonator, no limited resistor is needed.
X1
X2
C1
C2
Rd
CSB1000J
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable
oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency
accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the
resonator in the circuit. Please inquire directly to the maker of the resonator for data as needed.
47
PD754202, 754202(A)
DC Characteristics (T
A
= 40 to +85 C, V
DD
= 1.8 to 6.0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
High-level output current
I
OH
Per pin
Pins except P32
5
mA
Only P32,
7
15
mA
V
DD
= 3.0 V,
V
OH
= V
DD
2.0 V
All pins total
20
mA
Low-level output current
I
OL
Per pin
15
mA
All pins total
45
mA
High-level input voltage
V
IH1
Port 3
2.7 V
V
DD
6.0 V
0.7 V
DD
V
DD
V
1.8 V
V
DD
< 2.7 V
0.9 V
DD
V
DD
V
V
IH2
Ports 6-8, KRREN,
2.7 V
V
DD
6.0 V
0.8 V
DD
V
DD
V
RESET
1.8 V
V
DD
< 2.7 V
0.9 V
DD
V
DD
V
V
IH3
X1
V
DD
0.1
V
DD
V
Low-level input voltage
V
IL1
Port 3
2.7 V
V
DD
6.0 V
0
0.3 V
DD
V
1.8 V
V
DD
< 2.7 V
0
0.1 V
DD
V
V
IL2
Ports 6-8, KRREN,
2.7 V
V
DD
6.0 V
0
0.2 V
DD
V
RESET
1.8 V
V
DD
< 2.7 V
0
0.1 V
DD
V
V
IL3
X1
0
0.1
V
High-level output voltage
V
OH
V
DD
= 4.5 to 6.0 V, I
OH
= 1.0 mA
V
DD
1.0
V
V
DD
= 1.8 to 6.0 V, I
OH
= 100
A
V
DD
0.5
V
Low-level output voltage
V
OL
V
DD
= 4.5 to 6.0 V
Port 3, I
OL
= 15 mA
0.6
2.0
V
Ports 6, 8,
0.4
V
I
OL
= 1.6 mA
V
DD
= 1.8 to 6.0 V, I
OL
= 400
A
0.5
V
High-level input leak
I
LIH1
V
IN
= V
DD
Pins except X1
3.0
A
current
I
LIH2
X1
20
A
Low-level input leak
I
LIL1
V
IN
= 0 V
Pins except X1
3.0
A
current
I
LIL2
X1
20
A
High-level output
I
LOH
V
OUT
= V
DD
3.0
A
leak current
Low-level output
I
LOL
V
OUT
= 0 V
3.0
A
leak current
On-chip pull-up resistance
R
L1
V
IN
= 0 V
Ports 3, 6, 8
50
100
200
k
R
L2
Port 7 (mask option)
15
30
60
k
50
100
200
k
RESET (mask option)
50
100
200
k
48
PD754202, 754202(A)
DC Characteristics (T
A
= 40 to +85
C, V
DD
= 1.8 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Supply current
Note 1
I
DD1
4.19 MHz
V
DD
= 5.0 V
10 %
Note 2
1.5
5.0
mA
Crystal resonator
V
DD
= 3.0 V
10 %
Note 3
0.23
1.0
mA
I
DD2
C1 = C2 = 22 pF
HALT
V
DD
= 5.0 V
10 %
0.64
3.0
mA
mode
V
DD
= 3.0 V
10 %
0.20
0.9
mA
I
DD3
X1 = 0 V
V
DD
= 1.8 to 6.0 V
5
A
STOP
T
A
= 25
C
1
A
mode
V
DD
= 3.0 V
10 %
0.1
3
A
T
A
= 40 to
0.1
1
A
+40
C
Notes 1. Does not include current fed to on-chip pull-up resistor.
2. When processor clock control register (PCC) is set to 0011, during high-speed mode.
3. When PCC is set to 0000, during low-speed mode.
49
PD754202, 754202(A)
0.5
0
1
2
3
4
5
6
1
2
3
4
5
6
60
64
Supply voltage V
DD
[V]
(During system clock operation)
t
CY
vs V
DD
Operation
guaranteed range
Cycle time t
CY
[ s]
AC Characteristics (T
A
= 40 to +85
C, V
DD
= 1.8 to 6.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time
Note 1
t
CY
When system
2.7 V
V
DD
6.0 V
0.67
64.0
s
(Minimum instruction execution
clock is used
time = 1 machine cycle)
1.8 V
V
DD
< 2.7 V
0.95
64.0
s
Interrupt input high- and
t
INTH
, t
INTL
INT0
IM02 = 0
Note 2
s
low-level widths
IM02 = 1
10
s
KR4-KR7
10
s
RESET low-level width
t
RSL
10
s
Notes 1.
The CPU clock (
) cycle time (minimum
instruction execution time) is determined
by the oscillation frequency of the con-
nected resonator (and external clock) and
the processor clock control register (PCC).
The figure on the right shows the cycle
time t
CY
characteristics against the supply
voltage V
DD
when the system clock is used.
2.
2t
CY
or 128/fx depending on the setting of
the interrupt mode register (IM0).
50
PD754202, 754202(A)
t
XL
t
XH
1/f
X
V
DD
0.1 V
0.1 V
X1 input
V
IH
(MIN.)
V
IL
(MAX.)
V
IH
(MIN.)
V
IL
(MAX.)
V
OH
(MIN.)
V
OL
(MAX.)
V
OH
(MIN.)
V
OL
(MAX.)
AC Timing Test Points (Excluding X1 Input)
Clock Timing
Interrupt Input Timing
RESET Input Timing
INT0,
KR4-7
t
INTL
t
INTH
RESET
t
RSL
51
PD754202, 754202(A)
Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (T
A
= 40 to +85
C)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Release signal set time
t
SREL
0
s
Oscillation stabilization
t
WAIT
Release by RESET
Note 2
ms
wait time
Note 1
Release by interrupt request
Note 3
ms
Notes 1.
The oscillation stabilization wait time is the time during which the CPU operation is stopped to
avoid unstable operation at oscillation start.
2.
2
17
/fx and 2
15
/fx can be selected with mask option.
3.
Depends on setting of basic interval timer mode register (BTM) (see table below).
BTM3
BTM2
BTM1
BTM0
Wait Time
When f
X
= 4.19 MHz
When f
X
= 6.0 MHz
0
0
0
2
20
/f
X
(Approx. 250 ms)
2
20
/f
X
(Approx. 175 ms)
0
1
1
2
17
/f
X
(Approx. 31.3 ms)
2
17
/f
X
(Approx. 21.8 ms)
1
0
1
2
15
/f
X
(Approx. 7.81 ms)
2
15
/f
X
(Approx. 5.46 ms)
1
1
1
2
13
/f
X
(Approx. 1.95 ms)
2
13
/f
X
(Approx. 1.37 ms)
Data Retention Timing (on releasing STOP mode by RESET)
STOP mode
Data retention mode
Execution of STOP instruction
t
WAIT
t
SREL
HALT mode
Operation mode
V
DD
RESET
Internal reset operation
52
PD754202, 754202(A)
Data Retention Timing (Standby release signal: on releasing STOP mode by interrupt signal)
STOP mode
Data retention mode
Execution of STOP instruction
V
DD
Standby release signal
(interrupt request)
t
WAIT
t
SREL
HALT mode
Operation mode
53
PD754202, 754202(A)
13. CHARACTERISTIC CURVES (REFERENCE VALUES)
I
DD
vs V
DD
(System clock: 6.0-MHz crystal resonator)
0
1
2
3
4
5
6
7
8
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
X1
X2
6.0 MHz
22 pF
22 pF
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
HALT mode
System clock
Crystal
resonator
Supply Voltage V
DD
(V)
Supply Current I
DD
(mA)
(T
A
= 25 C)
54
PD754202, 754202(A)
I
DD
vs V
DD
(System clock: 4.19-MHz crystal resonator)
0
1
2
3
4
5
6
7
8
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
System clock
HALT mode
X1
X2
4.19 MHz
22 pF
22 pF
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
Crystal
resonator
Supply Voltage V
DD
(V)
Supply Current I
DD
(mA)
(T
A
= 25 C)
55
PD754202, 754202(A)
14. PACKAGE DRAWINGS
20 PIN PLASTIC SOP (300 mil)
ITEM
MILLIMETERS
INCHES
A
B
C
E
F
G
H
I
J
13.00 MAX.
1.27 (T.P.)
1.8 MAX.
1.55
7.70.3
0.78 MAX.
0.12
1.1
5.6
M
0.10.1
N
0.512 MAX.
0.031 MAX.
0.0040.004
0.071 MAX.
0.061
0.3030.012
0.220
0.043
0.005
0.050 (T.P.)
P20GM-50-300B, C-4
P
3
3
+7
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
D
0.40
0.016
+0.10
0.05
K
0.20
0.008
+0.10
0.05
L
0.60.2
0.024
0.10
3
+7
3
0.004
+0.008
0.009
+0.004
0.002
+0.004
0.003
A
C
D
G
P
detail of lead end
F
E
B
H
I
L
K
M
J
N
M
1
10
11
20
56
PD754202, 754202(A)
20 PIN PLASTIC SHRINK SOP (300 mil)
A
20
11
F
B
G
E
H
K
L
1
10
detail of lead end
J
I
3
+7 3
M
M
D
N
P20GM-65-300B-2
ITEM
MILLIMETERS
INCHES
A
B
C
D
E
F
G
H
I
J
K
7.00 MAX.
0.65 (T.P.)
2.0 MAX.
1.7
8.10.3
0.575 MAX.
0.276 MAX.
0.0050.003
0.079 MAX.
0.3190.012
0.2400.008
0.023 MAX.
NOTE
L
M
0.12
0.50.2
1.00.2
6.10.2
0.005
0.020
+0.008
0.009
Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
0.039
0.067
0.026 (T.P.)
0.15
+0.10
0.05
0.006
+0.004
0.002
N
0.10
0.004
0.012
+0.004
0.005
0.300.10
0.1250.075
+0.009
0.008
C
57
PD754202, 754202(A)
15. RECOMMENDED SOLDERING CONDITIONS
The
PD754202 should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Table 15-1. Surface Mounting Type Soldering Conditions
PD754202GS-
-BA5
: 20-pin plastic SOP (300 mil, 1.27-mm pitch)
PD754202GS-
-GJG
: 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
PD754202GS(A)-
-BA5 : 20-pin plastic SOP (300 mil, 1.27-mm pitch)
PD754202GS(A)-
-GJG : 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235
C, Reflow time: 30 seconds or below
IR35-00-2
(at 210
C or higher), Number of reflow processes: Twice or less
VPS
Package peak temperature: 215
C, Reflow time: 40 seconds or below
VP15-00-2
(at 200
C or higher), Number of reflow processes: Twice or less
Wave soldering
Solder temperature: 260
C or below, Flow time: 10 seconds or below,
WS60-00-1
Number of flow processes: 1
Preheating temperature: 120
C or below (package surface temperature)
Partial heating
Pin temperature: 300
C or below, Time: 3 seconds or below (per side of device)
--
Caution
Do not use different soldering methods together (except for partial heating).
58
PD754202, 754202(A)
APPENDIX A.
PD754202, 75F4264 FUNCTION LIST
Item
PD754202
PD75F4264
Note
Program memory
Mask ROM
Flash memory
0000H-07FFH
0000H-0FFFH
(2048
8 bits)
(4096
8 bits)
Data memory
Static RAM
000H-07FH (128
4 bits)
EEPROM
TM
None
400H-43FH (32
8 bits)
CPU
75XL CPU
General-purpose register
(4 bits
8 or 8 bits
4 )
4 banks
Instruction execution time
0.95, 1.91, 3.81, 15.3
s (system clock: at 4.19-MHz operation)
0.67, 1.33, 2.67, 10.7
s (system clock: at 6.0-MHz operation)
I/O port
CMOS input
4 (on-chip pull-up resistor can be connected by mask option)
CMOS input/output
9 (on-chip pull-up resistor can be specified by software)
Total
13
System clock oscillator
Ceramic/crystal oscillator
Boot time after reset
2
17
/f
X
or 2
15
/f
X
2
15
/f
X
(selected by mask option)
Timer
4 channels
8-bit timer counter: 3 channels (can be used for 16-bit timer counter)
Basic interval timer/watchdog timer: 1 channel
A/D converter
None
8-bit resolution
2 channels
(successive approximation register)
Operable V
DD
= 1.8 V or higher
Programmable threshold port
None
2 channels
Vectored interrupt
External: 1, Internal: 4
External: 1, Internal: 5
Test input
External: 1 (key return reset function provided)
Supply voltage
V
DD
= 1.8 to 6.0 V
Operating ambient temperature
T
A
= 40 to +85 C
Package
20-pin plastic SOP
20-pin plastic SOP
(300 mil, 1.27-mm pitch)
(300 mil, 1.27-mm pitch)
20-pin plastic shrink SOP
(300 mil, 0.65-mm pitch)
Note Under development
59
PD754202, 754202(A)
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are provided for system development using the
PD754202.
In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the
device file of each product.
Language processor
RA75X relocatable assembler
Host machine
Part number
OS
Supply media
(product name)
PC-9800 Series
MS-DOS
TM
3.5-inch 2HD
S5A13RA75X
Ver. 3.30 to
5-inch 2HD
S5A10RA75X
Ver. 6.2
Note
IBM PC/AT
TM
and
Refer to
3.5-inch 2HC
S7B13RA75X
compatible machines
"OS for IBM PC"
5-inch 2HC
S7B10RA75X
Device file
Host machine
Part number
OS
Supply media
(product name)
PC-9800 Series
MS-DOS
3.5-inch 2HD
S5A13DF754202
Ver. 3.30 to
5-inch 2HD
S5A10DF754202
Ver. 6.2
Note
IBM PC/AT and
Refer to
3.5-inch 2HC
S7B13DF754202
compatible machines
"OS for IBM PC"
5-inch 2HC
S7B10DF754202
Note
Ver. 5.00 or later have the task swap function, but it cannot be used for this software.
Remark Operations of the assembler and device file are guaranteed only on the above host machines and OSs.
60
PD754202, 754202(A)
Debugging tool
The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the
PD754202.
The system configurations are described as follows.
Hardware
IE-75000-R
Note 1
In-circuit emulator for debugging the hardware and software when developing applica-
tion systems that use the 75X Series and 75XL Series. When developing a
PD754202, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R
that are sold separately must be used with the IE-75000-R.
By connecting with the host machine, efficient debugging can be made.
It contains the emulation board IE-75000-R-EM which is connected.
IE-75001-R
In-circuit emulator for debugging the hardware and software when developing applica-
tion systems that use the 75X Series and 75XL Series. When developing a
PD754202, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R
which are sold separately must be used with the IE-75001-R.
By connecting with the host machine, efficient debugging can be made.
IE-75300-R-EM
Emulation board for evaluating the application systems that use a
PD754202.
It must be used with the IE-75000-R or IE-75001-R.
EP-754144GS-R
Emulation probe for the
PD754202.
It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM.
It is supplied with the 20-pin flexible boards EV-9500GS-20 (compatible with 20-pin
plastic shrink SOP) and EV-9501GS-20 (compatible with 20-pin plastic SOP) which
facilitate connection to a target system.
Software
IE control program
Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and
Centronics I/F and controls the IE-75000-R or IE-75001-R on a host machine.
Host machine
Part number
OS
Supply media
(product name)
PC-9800 Series
MS-DOS
3.5-inch 2HD
S5A13IE75X
Ver. 3.30 to
5-inch 2HD
S5A10IE75X
Ver. 6.2
Note 2
IBM PC/AT and
Refer to
3.5-inch 2HC
S7B13IE75X
compatible machines
"OS for IBM PC"
5-inch 2HC
S7B10IE75X
Notes 1.
Maintenance product
2.
Ver. 5.00 or later have the task swap function, but it cannot be used for this software.
Remark Operation of the IE control program is guaranteed only on the above host machines and OSs.
EV-9500GS-20
EV-9501GS-20
61
PD754202, 754202(A)
OS for IBM PC
The following IBM PC OS's are supported.
OS
Version
PC DOS
TM
Ver. 5.02 to Ver. 6.3
J6.1/V
Note
to J6.3/V
Note
MS-DOS
Ver. 5.0 to Ver. 6.22
5.0/V
Note
to J6.2/V
Note
IBM DOS
TM
J5.02/V
Note
Note
Only English mode is supported.
Caution Ver. 5.0 or later have the task swap function, but it cannot be used for this software.
62
PD754202, 754202(A)
APPENDIX C. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Device related documents
Document Name
Document Number
Japanese
English
PD754202, 754202(A) Data Sheet
U12181J
This document
PD754202 User's Manual
U11132J
U11132E
75XL Series Selection Guide
U10453J
U10453E
Development tool related documents
Document Name
Document Number
Japanese
English
Hardware
IE-75000-R/IE-75001-R User's Manual
EEU-846
EEU-1416
IE-75300-R-EM User's Manual
U11354J
U11354E
EP-754144GS-R User's Manual
U10695J
U10695E
Software
RA75X Assembler Package User's Manual
Operation
EEU-731
EEU-1346
Language
EEU-730
EEU-1363
Other related documents
Document Name
Document Number
Japanese
English
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Electrostatic Discharge (ESD) Test
MEM-539
Guide to Quality Assurance for Semiconductor Devices
C11893J
MEI-1202
Microcomputer Product Series Guide
U11416J
Caution These documents are subject to change without notice. Be sure to read the latest documents for
designing, etc.
63
PD754202, 754202(A)
[MEMO]
64
PD754202, 754202(A)
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools includ-
ing work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with
bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry.
Each unused pin should be connected to V
DD
or GND with a resistor, if it is
considered to have a possibility of being an output pin. All handling related
to the unused pins must be judged device by device and related specifications
governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immedi-
ately after power-on for devices having reset function.
65
PD754202, 754202(A)
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J96. 8
2
PD754202, 754202(A)
EEPROM is a trademark of NEC Corporation.
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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