Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PIN CONFIGURATION (Top View)
- PHOTOCELL STRUCTURE DIAGRAM (4800 dpi, for each color)
- PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing)
- PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Dummy, OB, for each color)
- ABSOLUTE MAXIMUM RATINGS (TA = +25 degrees)
- RECOMMENDED OPERATING CONDITIONS (TA = +25 degrees)
- ELECTRICAL CHARACTERISTICS
- INPUT PIN CAPACITANCE (TA = +25 degrees, VOD = 12 V)
- INPUT SIGNAL TABLE
- TIMING CHART 1-1 (4800 dpi, for each color)
- TIMING CHART 1-2 (2400 dpi, for each color)
- TIMING CHART 1-3 (1200 dpi, for each color)
- TIMING CHART 1-4 (600 dpi, for each color)
- TIMING CHART 2-1 (4800 dpi / 2400 dpi, for each color)
- TIMING CHART 2-2 (1200 dpi, for each color)
- TIMING CHART 2-3 (600 dpi, for each color)
- TIMING CHART 3 (readout)
- PHI 1, PHI 2 CROSS POINTS
- DEFINITIONS OF CHARACTERISTIC ITEMS
- STANDARD CHARACTERISTIC CURVES (Reference Value)
- APPLICATION CIRCUIT EXAMPLE
- PACKAGE DRAWING
- RECOMMENDED SOLDERING CONDITIONS
MOS INTEGRATED CIRCUIT
PD8884A
(10680 PIXELS
4 LINES) 3 COLOR CCD LINEAR IMAGE SENSOR
DATA SHEET
Document No. S17546EJ1V0DS00 (1st edition)
Date Published May 2005 NS CP (K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
2005
DESCRIPTION
The
PD8884A is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
PD8884A has 3 rows of (10680
4) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
4800 dpi/A4 color image scanners.
FEATURES
Valid photocell : (10680 pixels 4) 3
Photocell's size : 4
m
Line spacing
: Quad staggered pixels
96
m (24 lines) Red line - Green line, Green line - Blue line
Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lxhour)
Resolution
: 192 dot/mm A4 (210
297 mm) size (shorter side)
4800 dpi US letter (8.5"
11") size (shorter side)
Drive clock level : CMOS output under 5 V operation
Data rate
: 5.0 MHz Max.
Power supply
: +12 V
On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
PD8884ACY-A
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Remark The
PD8884ACY-A is a lead-free product.
Data Sheet S17546EJ1V0DS
2
PD8884A
BLOCK DIAGRAM
11
30
29
18
17
16
19
15
22
TG1
(Blue)
TG2
(Green)
TG3
(Red)
2-2
SEL2
1-2
SEL1
SEL3
5
28
2-1
1-1
2
3
14
4
1
CLB
RB
GND
V
OD
V
OUT
1
(Blue)
32
31
V
OUT
2
(Green)
V
OUT
3
(Red)
GND
Photocell
(Blue)
Transfer gate
Transfer gate
CCD analog shift register
Transfer gate
Transfer gate
CCD analog shift register
Drain gate
Drain gate
Photocell
(Green)
Transfer gate
Transfer gate
CCD analog shift register
Transfer gate
Transfer gate
CCD analog shift register
Drain gate
Drain gate
Photocell
(Red)
Transfer gate
Transfer gate
CCD analog shift register
Transfer gate
Transfer gate
CCD analog shift register
Drain gate
Drain gate
Data Sheet S17546EJ1V0DS
3
PD8884A
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
PD8884ACY-A
1
2
3
4
5
6
7
8
9
10
11
NC
V
OUT
1
IC
SEL1
TG1
No connection
NC
No connection
NC
No connection
Output signal 1 (Blue)
Output drain voltage
Internal connection
Dpi selector 1
SEL2
Dpi selector 2
Transfer gate clock 2
(for Green)
V
OUT
2
V
OUT
3
2-1
TG3
Output signal 2 (Green)
Output signal 3 (Red)
Reset gate clock
IC
Internal connection
IC
Internal connection
IC
Internal connection
IC
Internal connection
Shift register clock 2-2
21360
2
21360
2
21360
2
Red
Green
Blue
1
1
1
Internal connection
Transfer gate clock 1
(for Blue)
Transfer gate clock 3
(for Red)
V
OD
IC
2-2
1-2
Shift register clock 1-2
1-1
Shift register clock 1-1
GND
Ground
GND
Ground
RB
Reset feed-through level
clamp clock
CLB
No connection
NC
No connection
NC
No connection
NC
TG2
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
IC
Internal connection
IC
Internal connection
Dpi selector 3
SEL3
Shift register clock 2-1
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Data Sheet S17546EJ1V0DS
4
PD8884A
PHOTOCELL STRUCTURE DIAGRAM (4800 dpi, for each color)
m
4
m
33.5
m
33.5
m
8
m
3.0
m
1.0
CCD
CCD
1
5
9
13
17
21
3
7
11
15
19
23
4
8
12
16
20
24
2
6
10
14
18
22
Data Sheet S17546EJ1V0DS
5
PD8884A
PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing)
m
4
m
4
m
4
m
4
m
4
m)
(33.5
m)
(96
m)
(33.5
m)
(8
2 lines
24 lines
m
271
m)
(96
24 lines
m)
(21
m
4
m
4
m
4
m
4
m
4
m)
(33.5
m)
(33.5
m)
(8
2 lines
m)
(21
m
4
m
4
m
4
m
4
m
4
m)
(33.5
m)
(33.5
m)
(8
2 lines
Blue photocell array
Blue photocell array
Blue photocell array
Blue photocell array
CCD analog shift register
CCD analog shift register
Drain gate
Drain gate
Resolution Select
Blue photocell array
Blue photocell array
Blue photocell array
Blue photocell array
CCD analog shift register
CCD analog shift register
Drain gate
Drain gate
Resolution Select
Blue photocell array
Blue photocell array
Blue photocell array
Blue photocell array
CCD analog shift register
CCD analog shift register
Drain gate
Drain gate
Resolution Select
PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Dummy, OB, for each color)
1
157 161
349 353
361 365
373
43081 43085
369
357
2
158 162
350 354
362 366
374
43082 43086
370
358
3
159 163
351 355
363 367
375
43083 43087
371
359
4
160 164
352 356
364 368
376
43084 43088
372
360
Optical black
(192 pixels)
Invalid photocell
(16 pixels)
Invalid photocell
(8 pixels)
Dummy
(160 pixels)
Valid photocell
(42720 pixels)
4800 dpi
2400 dpi
4800 dpi
Data Sheet S17546EJ1V0DS
6
PD8884A
ABSOLUTE MAXIMUM RATINGS (T
A
=
+25C)
Parameter Symbol
Ratings
Unit
Output drain voltage
V
OD
-0.3 to +15 V
Shift register clock voltage
V
1
, V
2
-0.3 to +8 V
Reset gate clock voltage
V
RB
-0.3 to +8 V
Reset feed-through level clamp clock voltage
V
CLB
-0.3 to +8 V
Dpi select signal voltage
V
SEL1
to V
SEL3
-0.3 to +8 V
Transfer gate clock voltage
V
TG1
to V
TG3
-0.3 to +8 V
Operating ambient temperature
Note
T
A
0
to
+60
C
Storage temperature
T
stg
-40 to +70
C
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+25C)
Parameter Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
V
OD
11.5
12.0
12.5
V
Shift register clock high level
V
1H
, V
2H
4.75
5.0
5.5
V
Shift register clock low level
V
1L
, V
2L
-0.3 0 +0.3 V
Reset gate clock high level
V
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
RBL
-0.3 0 +0.3 V
Reset feed-through level clamp clock high level
V
CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock low level
V
CLBL
-0.3 0 +0.3 V
Dpi select signal high level
V
SEL1H
to V
SEL3H
4.5 5.0 5.5
V
Dpi select signal low level
V
SEL1L
to V
SEL3L
-0.3 0 +0.3 V
Transfer gate clock high level
V
TG1H
to V
TG3H
4.5 5.0 5.5
V
Transfer gate clock low level
V
TG1L
to V
TG3L
-0.3 0 +0.3 V
Data rate
f
RB
-
2.0 5.0
MHz
Clock pulse frequency
f
1
, f
2
-
1.0 10.0
MHz
Data Sheet S17546EJ1V0DS
7
PD8884A
ELECTRICAL CHARACTERISTICS
T
A
=
+25C, V
OD
= 12 V, data rate (f
RB
) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 V
p-p
,
light source : 3200 K halogen lamp
+ C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Symbol
Test
Conditions Min.
Typ.
Max.
Unit
Saturation voltage
V
sat
2.3 2.7
-
V
Red SER
-
0.79
-
lxs
Green SEG
-
0.87
-
lxs
Saturation exposure
Blue SEB
-
1.35
-
lxs
Photo response non-uniformity
PRNU
V
OUT
= 1.0 V
-
6 20 %
Average dark signal
ADS
Light shielding
-
0.1 4.0 mV
Dark signal non-uniformity DSNU
Light
shielding
-
2.0 8.0 mV
Power consumption
P
W
-
380 540 mW
Output impedance
Z
O
-
0.4 1.0 k
Red R
R
2.38 3.40 4.42 V/lxs
Green R
G
2.17 3.10 4.03 V/lxs
Response
Blue R
B
1.40 2.00 2.60 V/lxs
Offset level
Note
V
OS
4.5 6.0 7.5 V
Total transfer efficiency
TTE
V
OUT
= 1.0 V
Clock pulse frequency = 10 MHz
92 98
-
%
Red
-
630
-
nm
Green
-
540
-
nm
Response peak
Blue
-
460
-
nm
Image lag
IL
V
OUT
= 1.0 V
-
0.05 3.0 %
Response difference between
inside and outside
RDIO V
OUT
= 1.0 V
-
1.0 6.0 %
Potocell array imbalance
PAI
IN
V
OUT
= 1.0 V
-
1.0 6.0 %
PAI
OUT
V
OUT
= 1.0 V
-
1.0 6.0 %
Reset feed-through noise
Note
RFTN
Light
shielding
- -500
+1000 mV
Random noise (CDS)
CDS Light
shielding
-
1.2
-
mV
Note Refer
to
TIMING CHART 2-1 to 2-3.
Data Sheet S17546EJ1V0DS
8
PD8884A
INPUT PIN CAPACITANCE (T
A
=
+25C, V
OD
= 12 V)
Parameter
Symbol
Pin name
Pin No.
Min.
Typ.
Max.
Unit
Shift register clock pin capacitance 1
C
1-1
1-1 28
-
750
-
pF
Shift register clock pin capacitance 2
C
1-2
1-2 22
-
750
-
pF
Shift register clock pin capacitance 3
C
2-1
2-1 5
-
750
-
pF
Shift register clock pin capacitance 4
C
2-2
2-2 11
-
750
-
pF
Reset gate clock pin capacitance
C
RB
RB 3
-
20
-
pF
Reset feed-through level clamp clock pin capacitance
C
CLB
CLB
2
-
20
-
pF
Select signal and gain pin capacitance
C
SEL1
SEL1
19
-
20
-
pF
C
SEL2
SEL2
30
-
20
-
pF
C
SEL3
SEL3
15
-
20
-
pF
Transfer gate clock pin capacitance
TG1 18
-
20
-
pF
TG2 17
-
20
-
pF
C
TG
TG3 16
-
20
-
pF
Remark C
1-1
to C
2-2
show the equivalent capacity of the real drive including the capacity of between each clock
pin (
1-1,
1-2,
2-1 and
2-2).
INPUT SIGNAL TABLE
Mode
SEL1
(Even-line enable
switch)
SEL2
(CCD-drain switch)
SEL3
(TG-select switch)
Note
4800 dpi
High level
High level
High level
Even-line electron read photodiode to CCD
High level
High level
Low level
Odd-line electron read photodiode to CCD
2400 dpi
Low level
High level
Low level
Odd-line electron read photodiode to CCD
Even-line electron sink to drain
1200 dpi
Low level
Low level
Low level
600
dpi
1, 5, 9, 13, ... : Line photodiode use
2 to 4, 6 to 8, 10 to 12, ... : Sink to drain
Data S
heet
S1754
6EJ1V0DS
9
PD8884A
TIMING CHART 1-1 (4800 dpi, for each color)
"H"
1-2400
2-2400
TG1 to
TG3
SEL3
SEL2
SEL1,
Storage time (l1, l3)
Storage time (l2, l4)
2400 dpi cycle
Odd line read
2400 dpi cycle
Even line read
21360 pixels
Odd 2400 dpi
Data read
21360 pixels
Even 2400 dpi
Data read
21360 pixels
Even 2400 dpi
Data read
21360 pixels
Odd 2400 dpi
Data read
Remark Above means, storage time of each photocell array is "TG period
2". And storage time of (l1, l3) and (l2, l4) is a half overlap each other.
Data S
heet
S1754
6EJ1V0DS
10
PD8884A
TIMING CHART 1-2 (2400 dpi, for each color)
1
3
5
7
9
347
349
367
369
371
353
351
365
11
157
163
159
161
43085
43083
43087
43093
43095
43089
43091
V
OUT
1 to V
OUT
3
RB
CLB
SEL2
"H"
Optical black
(96 pixels)
1
2
TG1 to
TG3
Invalid photocell
(8 pixels)
Storage time
Valid photocell
(21360 pixels)
Invalid photocell
(4 pixels)
Note
Note
SEL3
"L"
SEL1
"L"
Note Set the
RB and the
CLB to high level during this period.
Data S
heet
S1754
6EJ1V0DS
11
PD8884A
TIMING CHART 1-3 (1200 dpi, for each color)
1
5
9
13
17
345
349
373
357
353
365
361
369
21
153
165
157
161
43081
43093
43097
43085
43089
V
OUT
1 to V
OUT
3
RB
CLB
SEL2
Optical black
(48 pixels)
1
2
TG1 to
TG3
Invalid photocell
(4 pixels)
Storage time
Valid photocell
(10680 pixels)
Invalid photocell
(2 pixels)
Note
Note
SEL3
"L"
SEL1
"L"
"L"
Note Set the
RB and the
CLB to high level during this period.
Data S
heet
S1754
6EJ1V0DS
12
PD8884A
TIMING CHART 1-4 (600 dpi, for each color)
V
OUT
1 to V
OUT
3
RB
CLB
SEL2
1
2
TG1 to
TG3
Storage time
Note
Note
SEL3
"L"
SEL1
"L"
"L"
1+5
9+13
345+349
369+373
353+357
361+365
153+157
161+165
42973+
42977
42981+
42985
42989+
42993
Optical black
(24 pixels)
Invalid photocell
(2 pixels)
Valid photocell
(5340 pixels)
Invalid photocell
(1 pixels)
N Note Set the
RB and the
CLB to high level during this period.
Remark 2 pixels data merge at the charge detected capacitance.
Data Sheet S17546EJ1V0DS
13
PD8884A
TIMING CHART 2-1 (4800 dpi / 2400 dpi, for each color)
t5
t3
t4
90%
10%
90%
10%
90%
10%
10%
10%
90%
t9
t10
t11
t1
t2
t7
t8
t6
t5
t3
t4
t9
t10
t11
t7
t8
t6
t
d
t
d
V
OS
10%
V
OUT
CLB
RB
2
1
RFTN
Symbol Min. Typ. Max. Unit
t1, t2
0
30
-
ns
t3 20
100
-
ns
t4
40
150
-
ns
t5, t6
0
10
-
ns
t7
-10
+25
-
ns
t8
20
100
-
ns
t9, t10
0
10
-
ns
t11 10
25
-
ns
t
d
- 15 -
ns
Data Sheet S17546EJ1V0DS
14
PD8884A
TIMING CHART 2-2 (1200 dpi, for each color)
t5
t3
t4
90%
10%
90%
10%
90%
10%
10%
90%
t9
t10
t11
t1
t2
t7
t8
t6
t
d
V
OS
10%
V
OUT
CLB
RB
2
1
RFTN
Symbol Min. Typ. Max. Unit
t1, t2
0
30
-
ns
t3 20
100
-
ns
t4
40
150
-
ns
t5, t6
0
10
-
ns
t7
-10
+25
-
ns
t8
20
100
-
ns
t9, t10
0
10
-
ns
t11 10
25
-
ns
t
d
- 15 -
ns
Data Sheet S17546EJ1V0DS
15
PD8884A
TIMING CHART 2-3 (600 dpi, for each color)
t5
t3
t4
90%
10%
90%
10%
90%
10%
10%
90%
t9
t10
t11
t1
t2
t7
t8
t6
t
d
V
OS
10%
V
OUT
CLB
RB
2
1
RFTN
Symbol Min. Typ. Max. Unit
t1, t2
0
30
-
ns
t3 20
100
-
ns
t4
40
150
-
ns
t5, t6
0
10
-
ns
t7
-10
+25
-
ns
t8
20
100
-
ns
t9, t10
0
10
-
ns
t11 10
25
-
ns
t
d
- 15 -
ns
Data Sheet S17546EJ1V0DS
16
PD8884A
TIMING CHART 3 (readout)
RB,
CLB
2
TG1 to
TG3
SEL3
1
90%
90%
10%
10%
t12
t13
t16
t15
t14
90%
t17
t18
90%
t19
t20
Symbol Min. Typ. Max. Unit
t12 8000
15000
(50000)
ns
t13, t14
0
50
-
ns
t15, t16
1000
2000
-
ns
t17 1000
2000
-
ns
t18 7000
10000
-
ns
t19, t20
500
1000
-
ns
1,
2 CROSS POINTS
1
2
2.0 V or more
2.0 V or more
Remark Adjust cross points of
1 and
2 with input resistance of each pin.
Data Sheet S17546EJ1V0DS
17
PD8884A
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : V
sat
Output signal voltage at which the response linearity is lost.
Photo pixel and CCD register electron saturate level.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. PRNU of 4800 dpi is calculated by the following formula.
PRNU
OUT
(%) =
y =
y
j
: Output voltage of valid pixel number j
IO : Number of outside valid pixels (21360 bits)
y
x : maximum of
y
j
- y
y
IO
j = 1
IO
y
j
100
PRNU
IN
(%) =
x =
x
j
: Output voltage of valid pixel number j
IV : Number of inside valid pixels (21360 bits)
x
x : maximum of
x
j
- x
x
IV
j = 1
IV
x
j
100
The following figure shows output waveform of 4800 dpi mode.
x
Register Dark
DC level
V
OUT
x
y
y
Inside 2400 dpi data set
Outnside 2400 dpi data set
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
ADS (mV) =
d
j
: Dark signal of valid pixel number j
Valid pixels
j = 1
Vaild pixels
d
j
Data Sheet S17546EJ1V0DS
18
PD8884A
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
d
j
: Dark signal of valid pixel number j
DSNU (mV) : maximum of
d
j
- ADS
j = 1 to Valid pixels
ADS
DSNU
Register Dark
DC level
V
OUT
6. Output impedance : Z
O
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lxs).
Note that the response varies with a light source (spectral
characteristic). R of 4800 dpi is defined as following (refer to 3. Photo response non-uniformity).
R
IN
:
x divided by exposure (lxs)
R
OUT
:
y divided by exposure (lxs)
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
V
OUT
TG
Light
V
OUT
ON
OFF
V
1
IL (%) =
V
1
V
OUT
100
Data Sheet S17546EJ1V0DS
19
PD8884A
9. Response difference between inside and outside : RDIO
Difference of average output voltage between inside 2400 dpi and outside 2400 dpi (refer to 3. Photo
response non-uniformity).
RDIO (%) =
2
x - y
x + y
100
10. Photocell array imbalance : PAI
PAI is calculated by following formula (refer to 3. Photo response non-uniformity).
PAI
IN
(%) =
2
n
j = 1
j = 1
n
2
(
x
2j 1
x
2j
)
1
n
n
x
j
100
x
j
n
: Output voltage of each pixel
: Number of valid pixels (21360 bits)
PAI
OUT
(%) =
2
m
j = 1
j = 1
m
2
(
y
2j 1
y
2j
)
1
n
m
y
j
100
y
j
m
: Output voltage of each pixel
: Number of valid pixels (21360 bits)
11. Offset level : V
OS
DC level of output signal is defined as follows.
12. Reset feed-through noise : RFTN
Reset feed-through noise (RFTN) are defined as follows.
V
OS
V
OUT
RFTN
Data Sheet S17546EJ1V0DS
20
PD8884A
13. Random noise (CDS) :
CDS
Random
noise
CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding).
CDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
"VD
i
".
3. The output level is measured during the video output time averaged over 100 ns to get "VO
i
".
4. The correlated double sampling output is defined by the following formula.
VCDS
i
= VD
i
VO
i
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation
CDS using the following formula equation.
CDS (mV) =
, V =
i
=
1
100
(VCDS
i
V)
2
i
=
1
100
VCDS
i
100
100
1
The following figure shows output waveform (valid photocell under dark condition).
Reset feed-through
Video output
Data Sheet S17546EJ1V0DS
21
PD8884A
STANDARD CHARACTERISTIC CURVES (Reference Value)
400
500
600
700
800
100
80
60
40
20
0
B
B
G
R
G
Response Ratio (%)
Wavelength (nm)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T
A
= +25
C)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
= +25
C)
Operating Ambient Temperature T
A
(
C)
Storage Time (ms)
8
4
2
1
0.5
0.25
0.1
10
0
20
30
40
50
Relative Output Voltage
Relative Output Voltage
2
1
0.2
0.1
1
5
10
Data Sheet S17546EJ1V0DS
22
PD8884A
APPLICATION CIRCUIT EXAMPLE
28
PD8884A
47
5.1
5.1
47
47
+12 V
0.1 F
47 F/25 V
+
B2
B1
47
47
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
27
26
25
24
23
22
21
20
19
18
17
47
47
NC
V
OUT
1
IC
SEL1
SEL2
SEL2
TG1
1-1
1-2
NC
NC
V
OUT
2
V
OUT
3
TG3
IC
IC
IC
IC
V
OD
IC
GND
GND
RB
CLB
TG
NC
NC
NC
TG2
IC
IC
RB
CLB
SEL1
1-1
1-2
5.1
2-2
2-1
SEL3
SEL3
2-2
2-1
5.1
47
B3
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Remarks 1.
RB,
CLB,
TG1 to
TG3 and
SEL1 to
SEL3 driving inverters shown in the above application
circuit example are the 74HC04.
1-1 to
2-2 driving inverters shown in the above application circuit example are the 74HC04 (
2.0
MHz) or the 74AC04 (
> 2.0 MHz).
2. Inverters B1 to B3 in the above application circuit example are shown in the figure below.
47 F/25 V
B1 to B3 EQUIVALENT CIRCUIT
+
12 V
100
100
CCD
V
OUT
2SC1842
2 k
Data Sheet S17546EJ1V0DS
23
PD8884A
PACKAGE DRAWING
55.2
0.5
54.8
0.5
12.6
0.5
9.05
0.3
9.25
0.3
4.1
0.5
1st valid pixel
5.85
0.3
1
4
4
32
17
16
1
2.0
46.7
2.54
0.25
0.46
0.1
1.02
0.15
(5.42)
4.21
0.5
4.55
0.5
(1.775)
2.725
0.3
0.25
0.05
10.16
0.20
3
5
2
10.16
+0.70
-0.20
Name
Dimensions
Refractive index
Plastic cap
52.2
6.40.8 (0.7 )
1.5
1 1st valid pixel The center of the pin1
2 The surface of the CCD chip The top of the cap
3 The bottom of the package The surface of the CCD chip
4 Mirror finishied surface
5 Thickness of mirror finished surface
(Unit : mm)
PD8884ACY
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400))
Data Sheet S17546EJ1V0DS
24
PD8884A
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Through-hole Device
PD8884ACY-A : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process Conditions
Partial heating method
Pin temperature : 300
C or below, Heat time : 3 seconds or less (per pin)
Cautions 1.
During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
2.
Soldering by the solder flow method may have deleterious effects on prevention of plastic
cap soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S17546EJ1V0DS
25
PD8884A
NOTES ON HANDLING THE PACKAGES
CLEANING THE PLASTIC CAP
DUST AND DIRT PROTECTING
MOUNTING OF THE PACKAGE
OPERATE AND STORAGE ENVIRONMENTS
Ethyl Alcohol
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
EtOH
MeOH
IPA
NMP
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
1
2
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 M
.
4
3
RECOMMENDED SOLVENTS
Solvents
Symbol
Data Sheet S17546EJ1V0DS
26
PD8884A
[MEMO]
Data Sheet S17546EJ1V0DS
27
PD8884A
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
PD8884A
The information in this document is current as of May, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
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