April 1996
NEC Electronics Inc.
CMOS-8LH
3.3-Volt, 0.5-Micron
CMOS Gate Arrays
Preliminary
Description
NEC's CMOS-8LH gate-array family consists of ultra-high
performance, sub-micron gate arrays, targeted for
applications requiring extensive integration and high
speeds. With the CMOS-8LH family, NEC delivers its
second generation 0.5-micron gate arrays. This family is
fabricated in a high-speed, 0.5-micron, drawn gate length
(Leff=0.35-micron), two- and three-level metal titanium-
silicide CMOS process which provides improved
performance and reduced power consumption. It features
channelless (sea-of-gates) architecture with an enhanced
pad layout for support of high-performance I/Os.
The CMOS-8LH family is provided with an extensive family
of macros. I/O macros include GTL, HSTL, and pECL.
TTL and CMOS I/Os are provided with 5-V tolerance for
applications requiring interface to 5-V logic. PCI signaling
standards are also supported including 3.3-V 66 MHz PCI.
The technology is enhanced by a set of advanced features
including phase-locked loops, clock tree synthesis, and
high-speed memory. The CMOS-8LH gate-array family of
3.3-V devices consists of 22 masters, offered in densities
of 31K raw gates to 329K raw gates. Usable gates range
from 20K to 214K used gates in two-level metal and from
24K to 264K used gates in three-level metal.
Figure 1. CMOS-8LH Package Options: BGA & QFP
Table 1. CMOS-8LH Family Features and Benefits
CMOS-8LH Family Features
CMOS-8LH Family Benefits
Second generation 0.5-micron (drawn), 3-level metal CMOS
Delivers up to 75 MHz system clock speed
24 base arrays with raw gates from 30K to 475K
Provides base sizes to give best fit in core-limited designs
Optimized pad pitch for low-cost packaging
Minimizes assembly cost for popular BGA and PQFPs
High-density, high-speed RAM compiler
Provides high-density RAM in fast gate-array design time
PCI, GTL, and HSTL interface buffers
Supports popular high-speed interface standards
Full range of 5-V-protected I/O drive strengths
Allows interface with 5-V logic while protecting 3.3-V ASIC
Phase-Locked Loop (DPLL) macros in development
Eliminates clock insertion delay, reduces total clock skew
Low power dissipation: 0.4 W/MHz/gate
Provides low power consumption at high system clock rates
Extensive package offering: PQFP, BGA, PGA
Delivers user-specific package requirements
Clock tree synthesis tool for automated clock tree design
Minimizes on-chip clock skew for high performance
Floorplanner-supplied layout information for resynthesis
Reduces design time and improves device performance
Popular, third-party EDA tools
Enables a smooth flow from user design to silicon
Extra routing channel for increased utilization
Achieves up to 80% utilization in 3-layer metal
A11169EU1V0DS00
The gate-array family is supported by NEC's OpenCAD
design system, a mixture of popular third-party EDA tools,
and proprietary NEC tools. NEC proprietary tools include
the GALET floorplanner, which helps to reduce design
time and improve design speed, and a clock tree synthesis
tool that automatically builds a balanced-buffer clock tree
to minimize on-chip clock skew.
OpenCAD is a registered trademark of NEC Electronics Inc.
CMOS-8LH
2
CMOS-8LH Applications
The CMOS-8LH family is ideal for use in personal
computer systems, engineering workstations, and tele-
communications switching and transmission systems,
where moderate integration and high speeds are primary
design goals. CMOS-8LH is targeted to support
applications with system speeds of 75-100 MHz. With
power dissipation of 0.4 W/MHz/gate, CMOS-8LH is also
suited for lower-power applications where high
performance is required.
Circuit Architecture
As shown in Figure 2, CMOS-8LH devices are divided into
I/O and internal cell regions. The I/O region contains input
and output buffers. The internal cell area is an array of
basic cells, each composed of two p-channel MOS
transistors and two n-channel transistors, as well as four
additional small n-channel MOS transistors for compact
RAM design. These p-channel and n-channel transistors
are sized to offer a superb ratio of speed to silicon area.
The four additional small RAM transistors, when not being
used for RAM, provide additional area for signal routing,
thus allowing exceptionally high utilization rates for a
channelless architecture.
The I/O region consists of a single line of pads. The I/O
buffer design allows all PCI, GTL, and HSTL class 1
buffers to fit into a single I/O slot. This layout also
enhances support for low-cost PBGA and wire-bonded
PQFP assembly techniques.
Figure 2. CMOS-8LH Layout and Cell Configuration
Table 2. CMOS-8LH Base Array Line-up
Device
(1)
(PD663xx)
Available
Used Gates
(2)
Max
2LM
3LM
Gates
2LM
3LM
Pads
42
62
30528
19843
24422
164
43
63
40992
26644
32794
188
45
65
51136
33238
40909
212
46
66
72576
47174
58061
236
48
68
83520
54288
66816
268
49
69
110400
71760
88320
308
50
70
120960
78624
96768
324
51
71
145360
94484
116288
356
52
72
204544
132953
163635
412
53
73
252928
164403
202342
468
55
75
329392
214104
263514
532
(1)
2LM represents two-layer metal; 3LM represents three-layer metal.
(2)
Actual gate utilization varies depending on circuit implementation.
Based on utilization rate of 65% for 2LM and 80% for 3LM.
Internal
Cell Area
N-Channel
N-Channel
N-Channel
P-Channel
RAM
Logic
Basic Cell
I/O Cel
Area
GND
VDD2
VDD1
Power Rail Architecture
CMOS-8LH provides additional flexibility for mixed voltage
system designs. As shown in Figure 2, the arrays contain
two power rails: a 3.3-V rail and V
DD2
. The V
DD2
rail is
used for interfaces such as 5-V PCI buffers where a
clamping diode allows protection for up to an 11-V voltage
spike, per the PCI revision 2.1 specification.
Packaging and Test
NEC utilizes BIST test structures for RAM testing. NEC
also offers advanced packaging solutions including Plastic
Ball Grid Arrays (PBGA), Plastic Quad Flat Packs (PQFP),
and Pin Grid Arrays (PGA). Please call your local NEC
ASIC design center representative for a listing of available
master/package combinations.
3
CMOS-8LH
Input/Output Capacitance
V
DD
= V
I
= 0-V; f = 1 MHz
Terminal
Symbol
Typ
Max
Unit
Input
C
IN
10
20
pF
Output
C
OUT
10
20
pF
I/O
C
I/ O
10
20
pF
(1) Values include package pin capacitance
Power Consumption
Description
Limits
Unit
Internal gate
(1)
0.21
W/MHz
Input buffer
2.546
W/MHz
Output buffer
10.60
W/MHz
Absolute Maximum Ratings
Power supply voltage, V
DD
0.5 to +4.6-V
Input voltage, V
I
3.3-V input buffer (at V
I
< V
DD
+ 0.5-V)
0.5 to +4.6-V
3.3-V fail-safe input buffer (at V
I
< V
DD
+ 0.5-V)
0.5 to +4.6-V
5-V-tolerant (at V
I
< V
DD
+ 3.0-V)
0.5 to +4.6-V
Output Voltage, V
O
3.3-V output buffer (at V
O
< V
DD
+ 0.5-V)
0.5 to +4.6-V
5-V-tolerant output buffer (at V
O
< V
DD
+ 3.0-V)
0.5 to +4.6-V
5-V open-drain output buffer (at V
O
< V
DD
+ 3.0-V)
0.5 to +4.6-V
Latch-up current, I
LATCH
>1 A (typ)
Operating temperature, T
OPT
40 to +85C
Storage temperature, T
STG
65 to +150C
(1)
Assumes 30% internal gate switching at one time
Caution: Exposure to absolute maximum ratings for extended periods may affect
device reliability; exceeding the ratings could cause permanent damage. The
device should not be operated outside the recommended operating conditions.
Recommended Operating Conditions
V
DD
= 3.3-V 0.3-V; T
j
= 40 to +125C
3.3-V Interface 5-V Interface
5-V PCI 3.3-V PCI
Block
Block
Level
Level
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
I/O power supply voltage
V
DD
3.0
3.6
3.0
3.6
3.0
5.5
3.0
3.6
V
Junction temperature
T
J
0
+100
0
+100
0
+100
0
+100
C
High-level input voltage
V
IH
2.0
V
DD
2.0
5.5
2.0
V
CC
0.5 V
CC
V
CC
V
Low-level input voltage
V
IL
0
0.8
0
0.8
0
0.8
0
0.3 V
CC
V
Positive trigger voltage
V
P
1.50
2.70
1.50
2.70
--
--
--
--
V
Negative trigger voltage
V
N
0.60
1.6
0.60
1.6
--
--
--
--
V
Hysteresis voltage
V
H
1.10
1.3
1.10
1.3
--
--
--
--
V
Input rise/fall time
t
R
, t
F
0
200
0
200
0
200
0
200
ns
Input rise/fall time, Schmitt
t
R
, t
F
0
10
0
10
--
--
--
--
ns
AC Characteristics
V
DD
= 3.3-V 0.3-V; T
j
= 40 to +125C
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Toggle frequency (F611)
f
TOG
477
MHz
D-F/F; F/O = 1; L = 0 mm
Delay time
2-input NAND (L302)
t
PD
104
ps
F/O = 1; L = 0 mm
(F302)
t
PD
120
ps
F/O = 2; L = typ = 0.6 mm
Flip-flop (L611)
t
PD
457
ps
F/O = 1; L = 0 mm
t
PD
579
ps
F/O = 2; L = typ
t
SETUP
510
ps
--
t
HOLD
430
ps
--
Input buffer (FI01)
t
PD
200
ps
F/O = 1; L = 0 mm
t
PD
249
ps
F/O = 2; L = typ
Output buffer (9 mA) 3.3-V
t
PD
1.16
ns
C
L
= 15 pF
Output buffer (9 mA) 5-V-tolerant
t
PD
1.428
ns
C
L
= 15 pF
Output buffer (9 mA) 5-V-swing
t
PD
1.577
ns
C
L
= 15 pF
Output rise time (9 mA)
t
R
1.47
ns
C
L
= 15 pF
Output fall time (9 mA)
t
F
1.08
ns
C
L
= 15 pF
CMOS-8LH
4
(3) Rating is for only one output operating in this mode for less than 1 second.
(4) Normal type buffer: I
OH
< I
OL
.
(5) Balanced buffer: I
OH
= I
OL
.
(6) Resistor is called 50k
to maintain consistency with previous families.
Notes:
(1) Static current consumption increases if an I/O block with on-chip pull-up/pull-
down resistor or an oscillator is used. Call an NEC ASIC design center repre-
sentative for assistance in calculation.
(2) Leakage current is limited by tester capabilities. Specification listed represents
this measurement limitation. Actual values will be significantly lower.
DC Characteristics
V
DD
= 3.3-V 0.3-V; T
j
= 40 to +125C
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Quiescent current
(1)
PD66358, 66378
I
DDS
2.0
300
A
V
I
= V
DD
or GND
PD66355, 66353, 66352, 66375, 66373, 66372
I
DDS
1.0
300
A
V
I
= V
DD
or GND
Remaining masters
I
DDS
0.5
200
A
V
I
= V
DD
or GND
Off-state output leakage current
3.3-V buffers, 3.3-V PCI
I
OZ
10
A
V
O
= V
DD
or GND
5-V-tolerant buffers, 5-V PCI
I
OZ
14
A
V
O
= V
DD
or GND
5-V CMOS
I
OZ
14
A
V
O
= V
DD
or GND
Output short circuit current
(3)
I
OS
250
mA
V
O
= GND
Input leakage current
(2)
5-V PCI
I
IH
+70, 70
A
V
IN
= 2.7-V, 0.5-V
3.3-V PCI
I
I
10
A
V
IN
= V
DD
or GND
Regular
I
I
10
5
10
A
V
I
= V
DD
or GND
50 k
pull-up
I
I
180
100
40
A
V
I
= GND
5 k
pull-up
I
I
1400
850
350
mA
V
I
= GND
50 k
pull-down
I
I
30
80
160
A
V
I
= V
DD
Resistor values
50 k
pull-up (6)
R
pu
20
33
75
k
5 k
pull-up
R
pu
2.6
3.9
8.6
k
50 k
pull-down (6)
R
pu
22.5
41.3
100
k
Input clamp voltage
V
IC
1.2
V
I
I
= 18 mA
Low-level output current (ALL buffer types)
3 mA
I
OL
3
mA
V
OL
= 0.4-V
6 mA
I
OL
6
mA
V
OL
= 0.4-V
9 mA
I
OL
9
mA
V
OL
= 0.4-V
12 mA
I
OL
12
mA
V
OL
= 0.4-V
18 mA
I
OL
18
mA
V
OL
= 0.4-V
24 mA
I
OL
24
mA
V
OL
= 0.4-V
High-level output current (5-V-tolerant block)
3 mA
I
OH
3
mA
V
OH
= V
DD
0.4-V
6 mA
I
OH
3
mA
V
OH
= V
DD
0.4-V
9 mA
I
OH
3
mA
V
OH
= V
DD
0.4-V
12 mA
I
OH
3
mA
V
OH
= V
DD
0.4-V
18 mA
I
OH
4
mA
V
OH
= V
DD
0.4-V
24 mA
I
OH
4
mA
V
OH
= V
DD
0.4-V
High-level output current (3.3-V interface block)
3 mA
I
OH
3
mA
V
OH
= V
DD
0.4-V
6 mA
I
OH
6
mA
V
OH
= V
DD
0.4-V
9 mA
I
OH
9
mA
V
OH
= V
DD
0.4-V
12 mA
I
OH
12
mA
V
OH
= V
DD
0.4-V
18 mA
I
OH
18
mA
V
OH
= V
DD
0.4-V
24 mA
I
OH
24
mA
V
OH
= V
DD
0.4-V
Output voltage (5-V PCI)
High-level output voltage
V
OH
2.4
mA
I
OH
= 2 mA
Low-level output voltage
V
OL
0.55
mA
I
OL
= 3 mA, 6 mA
Output voltage (3.3-V PCI)
High-level output voltage
V
OH
0.9 V
DD
mA
I
OH
= 500 A
Low-level output voltage
V
OL
0.1 V
DD
mA
I
OL
= 1500 A
Low-level output voltage
V
OL
0.1
V
I
OL
= 0 mA
High-level output voltage, 5-V TTL
V
OH
V
DD
0.2
V
I
OL
= 0 mA
High-level output voltage, 3.3-V
V
OH
V
DD
0.1
V
I
OH
= 0 mA
5
CMOS-8LH
Publications
This data sheet contains preliminary specifications for
the CMOS-8LH gate-array family. Additional infor-
mation will be available in NEC's
CMOS-8LH Block
Library and CMOS-8LH Design Manual. Call your local
NEC ASIC design center representative or the NEC
literature line for additional ASIC design information; see
the back of this data sheet for locations and phone
numbers.
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