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Электронный компонент: 54AC191D

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54AC191
Up/Down Counter with Preset and Ripple Clock
General Description
The 'AC191 is a reversible modulo 16 binary counter. It fea-
tures synchronous counting and asynchronous presetting.
The preset feature allows the 'AC191 to be used in program-
mable dividers. The Count Enable input, the Terminal Count
output and the Ripple Clock output make possible a variety
of methods of implementing multistage counters. In the
counting modes, state changes are initiated by the rising
edge of the clock.
Features
n
I
CC
reduced by 50%
n
High speed -- 133 MHz typical count frequency
n
Synchronous counting
n
Asynchronous parallel load
n
Cascadable
n
Outputs source/sink 24 mA
n
Standard Military Drawing (SMD)
-- 'AC191: 5962-89749
Logic Symbols
Pin Names
Description
CE
Count Enable Input
CP
Clock Pulse Input
P
0
P
3
Parallel Data Inputs
PL
Asynchronous Parallel Load Input
U/D
Up/Down Count Control Input
Q
0
Q
3
Flip-Flop Outputs
RC
Ripple Clock Output
TC
Terminal Count Output
Connection Diagrams
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
DS100279-1
IEEE/IEC
DS100279-2
Pin Assignment
for DIP and Flatpack
DS100279-3
Pin Assignment for LCC
DS100279-4
July 1998
54AC191
Up/Down
Counter
with
Preset
and
Ripple
Clock
1998 National Semiconductor Corporation
DS100279
www.national.com
Functional Description
The 'AC191 is a synchronous up/down counter. The 'AC191
is organized as a 4-bit binary counter. It contains four
edge-triggered flip-flops with internal gating and steering
logic to provide individual preset, count-up and count-down
operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired number.
When the Parallel Load (PL) input is LOW, information
present on the Parallel Load inputs (P
0
P
3
) is loaded into
the counter and appears on the Q outputs. This operation
overrides the counting functions, as indicated in the Mode
Select Table.
A HIGH signal on the CE input inhibits counting. When CE is
LOW, internal state changes are initiated synchronously by
the LOW-to-HIGH transition of the clock input. The direction
of counting is determined by the U/D input signal, as indi-
cated in the Mode Select Table. CE and U/D can be changed
with the clock in either state, provided only that the recom-
mended setup and hold times are observed.
Two types of outputs are provided as overflow/underflow in-
dicators. The terminal count (TC) output is normally LOW. It
goes HIGH when the circuits reach zero in the count down
mode or 15 in the count up mode. The TC output will then re-
main HIGH until a state change occurs, whether by counting
or presetting or until U/D is changed. The TC output should
not be used as a clock signal because it is subject to decod-
ing spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH. When
CE is LOW and TC is HIGH, RC output wil go LOW when the
clock next goes LOW and will stay LOW until the clock goes
HIGH again. This feature simplifies the design of multistage
counters, as indicated in
Figure 1 and Figure 2. In Figure 1,
each RC output is used as the clock input for the next higher
stage. This configuration is particularly advantageous when
the clock source has a limited drive capability, since it drives
only the first stage. To prevent counting in all stages it is only
necessary to inhibit the first stage, since a HIGH signal on
CE inhibits the RC output pulse, as indicated in the RC Truth
Table. A disadvantage of this configuration, in some applica-
tions, is the timing skew between state changes in the first
and last stages. This represents the cumulative delay of the
clock as it ripples through the preceding stages.
A method of causing state changes to occur simultaneously
in all stages is shown in
Figure 2. All clock inputs are driven
in parallel and the RC outputs propagate the carry/borrow
signals in ripple fashion. In this configuration the LOW state
duration of the clock must be long enough to allow the
negative-going edge of the carry/borrow signal to ripple
through to the last stage before the clock goes HIGH. There
is no such restriction on the HIGH state duration of the clock,
since the RC output of any device goes HIGH shortly after its
CP input goes HIGH.
The configuration shown in
Figure 3 avoids ripple delays and
their associated restrictions. The CE input for a given stage
is formed by combining the TC signals from all the preceding
stages. Note that in order to inhibit counting an enable signal
must be included in each carry gate. The simple inhibit
scheme of
Figure 1 and Figure 2 doesn't apply, because the
TC output of a given stage is not affected by its own CE.
Mode Select Table
Inputs
Mode
PL
CE
U/D
CP
H
L
L
N
Count Up
H
L
H
N
Count Down
L
X
X
X
Preset (Asyn.)
H
H
X
X
No Change (Hold)
RC Truth Table
Inputs
Outputs
PL
CE
TC
*
CP
RC
H
L
H
J
J
H
H
X
X
H
H
X
L
X
H
L
X
X
X
H
*
TC is generated internally
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
= LOW-to-HIGH Transition
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2
Functional Description
(Continued)
DS100279-7
FIGURE 1. N-Stage Counter Using Ripple Clock
DS100279-8
FIGURE 2. Synchronous N-Stage Counter Using Ripple Carry/Borrow
DS100279-9
FIGURE 3. Synchronous N-Stage Counter with Parallel Gated Carry/Borrow
3
www.national.com
State Diagram
Logic Diagram
DS100279-5
DS100279-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
2.0V to 6.0V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54AC
-55C to +125C
Minimum Input Edge Rate (
V/
t)
'AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.3V 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, output/input loading variables. National does not recommend
operation of FACT
TM
circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
Symbol
Parameter
V
CC
(V)
54AC
Units
Conditions
T
A
= -55C to +125C
Guaranteed Limits
V
IH
Minimum High Level Input
Voltage
3.0
2.1
V
OUT
= 0.1V
4.5
3.15
V
or V
CC
- 0.1V
5.5
3.85
V
IL
Maximum Low Level Input
Voltage
3.0
0.9
V
OUT
= 0.1V
4.5
1.35
V
or V
CC
- 0.1V
5.5
1.65
V
OH
Minimum High Level Output
Voltage
3.0
2.9
I
OUT
= -50 A
4.5
4.4
V
5.5
5.4
(Note 2) V
IN
= V
IL
or V
IH
3.0
2.4
-12 mA
4.5
3.7
V
I
OH
-24 mA
5.5
4.7
-24 mA
V
OL
Maximum Low Level Output
Voltage
3.0
0.1
I
OUT
= 50 A
4.5
0.1
V
5.5
0.1
(Note 2) V
IN
= V
IL
or V
IH
3.0
0.50
12 mA
4.5
0.50
V
I
OL
24 mA
5.5
0.50
24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
OLD
(Note 3) Minimum Dynamic
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
Output Current
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
Supply Current
or GND
5
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