54AC273
Octal D Flip-Flop
General Description
The '273 has eight edge-triggered D-type flip-flops with indi-
vidual D inputs and Q outputs. The common buffered Clock
(CP) and Master Reset (MR) input load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Features
n
Ideal buffer for microprocessor or memory
n
Eight edge-triggered D flip-flops
n
Buffered common clock
n
Buffered, asynchronous master reset
n
See '377 for clock enable version
n
See '373 for transparent latch version
n
See '374 for TRI-STATE
version
n
Outputs source/sink 24 mA
n
'ACT has TTL-compatible inputs
n
Standard Military Drawing (SMD)
-- 'AC273: 5962-87756
Logic Symbols
Pin Names
Description
D
0
D
7
Data Inputs
MR
Master Reset
CP
Clock Pulse Input
Q
0
Q
7
Data Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
TM
is a trademark of National Semiconductor Corporation.
DS100288-1
IEEE/IEC
DS100288-2
July 1998
54AC273
Octal
D
Flip-Flop
54AC273
1998 National Semiconductor Corporation
DS100288
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1
PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1
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Proof
1
Connection Diagrams
Mode Select-Function Table
Operating Mode
Inputs
Outputs
MR
CP
D
n
Q
n
Reset (Clear)
L
X
X
L
Load `1'
H
N
H
H
Load `0'
H
N
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
= LOW-to-HIGH Transition
Logic Diagram
Pin Assignment
for DIP and Flatpak
DS100288-3
Pin Assignment
for LCC
DS100288-4
DS100288-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
PrintDate=1998/07/27 PrintTime=08:02:05 44014 ds100288 Rev. No. 1
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'AC
2.0V to 6.0V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54AC
-55C to +125C
Minimum Input Edge Rate (
V/
t)
'AC Devices
V
IN
from 30% to 70% of V
CC
V
CC
@
3.3V, 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
TM
circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
54AC
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed
Limits
V
IH
Minimum High Level
3.0
2.1
V
OUT
= 0.1V
Input Voltage
4.5
3.15
V
or V
CC
- 0.1V
5.5
3.85
V
IL
Maximum Low Level
3.0
0.9
V
OUT
= 0.1V
Input Voltage
4.5
1.35
V
or V
CC
- 0.1V
5.5
1.65
V
OH
Minimum High Level
3.0
2.9
I
OUT
= -50 A
Output Voltage
4.5
4.4
V
5.5
5.4
(Note 2)
V
IN
= V
IL
or V
IH
3.0
2.4
I
OH
= -12 mA
4.5
3.7
V
I
OH
= -24 mA
5.5
4.7
I
OH
= -24 mA
V
OL
Maximum Low Level
3.0
0.1
I
OUT
= 50 A
Output Voltage
4.5
0.1
V
5.5
0.1
(Note 2)
V
IN
= V
IL
or V
IH
3.0
0.50
I
OL
= 12 mA
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
OLD
(Note 3)
Minimum Dynamic
Output Current
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
5.5
-50
mA
V
OHD
= 3.85V Min
3
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DC Characteristics for 'AC Family Devices
(Continued)
54AC
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed
Limits
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
IN
and I
CC
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V V
CC
.
I
CC
for 54AC
@
25C is identical to 74AC
@
25C.
AC Electrical Characteristics
54AC
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 5)
C
L
= 50 pF
Min
Max
f
max
Maximum Clock
3.3
75
MHz
Frequency
5.0
90
t
PLH
Propagation Delay
3.3
1.0
15.0
ns
Clock to Output
5.0
1.0
11.0
t
PHL
Propagation Delay
3.3
1.0
16.0
ns
Clock to Output
5.0
1.0
11.5
t
PHL
Propagation Delay
3.3
1.0
16.0
ns
MR to Output
5.0
1.0
11.5
Note 5: Voltage Range 3.3 is 3.3V
0.3V. Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
54AC
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 6)
C
L
= 50 pF
Guaranteed
Minimum
t
s
Setup Time, HIGH or LOW
3.3
8.0
ns
Data to CP
5.0
5.0
t
h
Hold Time, HIGH or LOW
3.3
0
ns
Data to CP
5.0
1.0
t
w
Clock Pulse Width
3.3
6.5
ns
HIGH or LOW
5.0
5.0
t
w
MR Pulse Width
3.3
10.0
ns
HIGH or LOW
5.0
6.5
t
rec
Recovery Time
3.3
6.0
ns
MR to CP
5.0
4.0
Note 6: Voltage Range 3.3 is 3.3V
0.3V. Voltage Range 5.0 is 5.0V
0.5V
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4
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= Open
C
PD
Power Dissipation
50.0
pF
V
CC
= 5.0V
Capacitance
5
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PrintDate=1998/07/27 PrintTime=08:02:06 44014 ds100288 Rev. No. 1
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