ADC1005
10-Bit P Compatible A/D Converter
General Description
The ADC1005 is a CMOS 10-bit successive approximation
A/D converter. The 20-pin ADC1005 outputs 10-bit data in a
two-byte format for interface with 8-bit microprocessors.
The ADC1005 has differential inputs to permit rejection of
common-mode signals, allow the analog input range to be
offset, and also to permit the conversion of signals not re-
ferred to ground. In addition, the reference voltage can be
adjusted, allowing smaller voltage spans to be measured
with 10-bit resolution.
Features
n
Easy interface to all microprocessors
n
Differential analog voltage inputs
n
Operates ratiometrically or with 5 V
DC
voltage reference
or analog span adjusted voltage reference
n
0V to 5V analog input voltage range with single 5V
supply
n
On-chip clock generator
n
TLL/MOS input/output compatible
n
0.3" standard width 20-pin DIP
Key Specifications
n
Resolution
10 bits
n
Linearity Error
1
/
2
LSB and
1 LSB
n
Conversion Time
50 s
Connection Diagram
Ordering Information
Part Number
Package
Temperature
Linearity
Outline
Range
Error
ADC1005BCJ-1
J20A
0C to +70C
1
/
2
LSB
ADC1005BCJ
J20A
-40C to +85C
ADC1005CCJ-1
J20A
0C to +70C
1 LSB
ADC1005CCJ
J20A
-40C to +85C
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
ADC 1005 (for an 8bit data bus)
Dual-In-Line Package
DS005261-1
Top View
June 1999
ADC1005
10-Bit
P
Compatible
A/D
Converter
1999 National Semiconductor Corporation
DS005261
www.national.com
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
6.5V
Logic Control Inputs
-0.3V to +15V
Voltage at Other Inputs and Outputs
-0.3V to V
CC
+0.3V
Input Current Per Pin
5 mA
Input Current Per Package
20 mA
Storage Temperature Range
-65C to +150C
Package Dissipation at T
A
=25C
875 mW
Lead Temperature
(Soldering, 10 seconds)
Dual-In-Line Package (Ceramic)
300C
Surface Mount Package
Vapor Phase (60 seconds)
215C
Infrared (15 seconds)
220C
ESD Susceptibility (Note 8)
800V
Operating Ratings
(Notes 1, 2)
Supply Voltage (V
CC
)
4.5V to 6.0V
Temperature Range
T
MN
T
A
T
MAX
ADC1005BCJ, ADC1005CCJ
-40C
T
A
+85C
ADC1005BCJ-1, ADC1005CCJ-1
Electrical Characteristics
The following specifications apply for V
CC
= 5V, V
REF
= 5V, f
CLK
= 1.8 MHz unless otherwise specified. Boldface limits apply
from T
MIN
to T
MAX
; All other limits T
A
= T
j
= 25C.
Parameter
Conditions
ADC1005BCJ
ADC1005BCJ-1,
Limit
Units
ADC1005CCJ
ADC1005CCJ-1
Typ
Tested
Design
Typ
Tested
Design
(Note 5)
Limit
Limit
(Note 5)
Limit
Limit
(Note 6)
(Note 7)
(Note 6)
(Note 7)
Converter Characteristics
Linearity Error (Note 3)
ADC1005BCJ
0.5
LSB
ADC1005BCJ-1
0.5
0.5
LSB
ADC1005CCJ
1
LSB
ADC1005CCJ-1, CCV
1
1
LSB
Zero Error
ADC1005BCJ
0.5
LSB
ADC1005BCJ-1
0.5
0.5
LSB
ADC1005CCJ
1
LSB
ADC1005CCJ-1, CCV
1
1
LSB
Fullscale Error
ADC1005BCJ
0.5
LSB
ADC1005BCJ-1
0.5
0.5
LSB
ADC1005CCJ
1
LSB
ADC1005CCJ-1, CCV
1
1
LSB
Reference
MIN
4.8
2.2
4.8
2.4
2.2
k
Input
MAX
4.8
8.3
4.8
7.6
8.3
k
Resistance
Common-Mode
MIN
V
CC
+0.05
V
CC
+0.05
V
CC
+0.05
V
Input (Note 4)
MAX
V
IN
(+) or V
IN
(-)
GND-0.05
GND-0.05
GND-0.05
V
DC Common-Mode
Over
Common-Mode
1
/
8
1
/
4
1
/
8
1
/
4
1
/
4
LSB
Error
Input Range
Power Supply Sensitivity
V
CC
=5 V
DC
5%
1
/
8
1
/
4
1
/
8
1
/
4
1
/
4
LSB
V
REF
= 4.75V
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2
Electrical Characteristics
(Continued)
The following specifications apply for V
CC
= 5V, V
REF
= 5V, f
CLK
= 1.8 MHz unless otherwise specified. Boldface limits apply
from T
MIN
to T
MAX
; All other limits T
A
= T
j
= 25C.
Parameter
Conditions
ADC1005BCJ
ADC1005BCJ-1,
Limit
Units
ADC1005CCJ
ADC1005CCJ-1
Typ
Tested
Design
Typ
Tested
Design
(Note 5)
Limit
Limit
(Note 5)
Limit
Limit
(Note 6)
(Note 7)
(Note 6)
(Note 7)
DC Characteristics
V
IN(1)
Logical "1" Input
V
CC
=5.25V
2.0
2.0
2.0
V
Voltage
MIN
(except CLK
IN
)
V
IN(0)
, Logical "0" Input
V
CC
=4.75V
0.8
0.8
0.8
V
Voltage
MAX (Except CLK
IN
)
I
IN
, Logical "1" Input
V
IN
=5.0V
0.005
1
0.005
1
1
A
Current
MAX
I
IN
, Logical "0" Input
V
IN
=0V
-0.005
-1
-0.005
-1
-1
A
Current
MAX
V
T+(MIN)
, Minimum CLK
IN
Positive going Threshold
3.1
2.7
3.1
2.7
2.7
V
Voltage
V
T(MAX)
, Maximum CLK
IN
Positive going Threshold
3.1
3.5
3.1
3.5
3.5
V
Voltage
V
T-(MIN)
, Minimum CLK
IN
Negative going Threshold
1.8
1.5
1.8
1.5
1.5
V
Voltage
V
T-(MAX)
, Maximum CLK
IN
Negative going Threshold
1.8
2.1
1.8
2.1
2.1
V
Voltage
V
H(MIN)
, Minimum CLK
IN
1.3
0.6
1.3
0.6
0.6
V
Hysteresis (V
T+
-V
T-
)
V
H(MAX)
, Maximum CLK
IN
1.3
2.0
1.3
2.0
2.0
V
Hysteresis (V
T+
-V
T-
)
V
OUT(1)
, Logical "1"
V
CC
=4.75V
Output Voltage
MIN
I
OUT
=-360 A
2.4
2.8
2.4
V
I
OUT
=-10 A
4.5
4.6
4.5
V
V
OUT(0)
, Logical "0"
V
CC
=4.75V
0.4
0.34
0.4
V
Output Voltage
MAX I
OUT
=1.6 mA
I
OUT
, TRI-STATE Output
V
OUT
= 0V
-0.01
-3
-0.01
-0.3
-3
A
Current
MAX V
OUT
= 5V
0.01
3
0.01
0.3
3
A
I
SOURCE
, Output Source
V
OUT
=0V
-14
-6.5
-14
-7.5
-6.5
mA
Current
MIN
I
SINK
, Output Sink
V
OUT
=5V
16
8.0
16
9.0
8.0
mA
Current
MIN
I
CC
, Supply Current
MAX f
CLK
=1.8 MHz
1.5
3
1.5
2.5
3
mA
CS ="1"
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3
AC Electrical Characteristics
The following specifications apply for V
CC
= 5V, V
REF
= 5V,V
REF
= 5V, t
r
= t
f
= 20 ns unless otherwise specified. Boldface lim-
its apply from T
MIN
to T
MAX
; All other limits T
A
= T
j
= 25C.
Typ
Tested
Design
Limit
Parameter
Conditions
(Note 5)
Limit
Limit
Units
(Note 6)
(Note 7)
f
CLK
, Clock Frequency
MIN
0.2
0.2
MHz
MAX
2.6
2.6
MHz
Clock Duty Cycle
MIN
40
40
%
MAX
60
60
%
t
C
, Conversion Time
MIN
80
80
1/f
CLK
MAX
90
90
1/f
CLK
MIN
f
CLK
=1.8 MHz
45
45
s
MAX
f
CLK
=1.8 MHz
50
50
s
t
W(WR)L
, Minimum WR Pulse
Width
CS =0
100
150
150
ns
t
ACC
, Access Time (Delay from
falling edge of RD to Output
Data Valid)
CS =0
170
300
300
ns
C
L
=100 pF, R
L
= 2k
t
1H
, t
0H
, TRI-STATE Control
(Delay from Rising Edge of RD
to Hi-Z State)
R
L
=10k, C
L
=10 pF
125
200
ns
R
L
=2k, C
L
=100 pF
145
230
230
ns
t
WI
, t
RI
, Delay from Falling
Edge of WR or RD to Reset of
INTR
300
450
450
ns
t
IRS
, INTR to 1st Read Set-up
Time
400
550
550
ns
C
IN
, Capacitance of Logic
Inputs
5
7.5
pF
C
OUT
, Capacitance of Logic
Outputs
5
7.5
pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to ground.
Note 3: Linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line which passes through the end points of the transfer
characteristic.
Note 4: For V
IN(-)
V
IN(+)
the digital output code will be 00 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input
voltages one diode drop below ground or one diode drop greater than V
CC
supply. Be careful, during testing at low V
CC
levels (4.5V), as high level analog inputs (5V)
can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias
of either diode. This means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an
absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Note 5: Typicals are at 25C and represent most likely parametric norm.
Note 6: Tested and guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 7: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 8: Human body model, 100 pF discharged through a 1.5 k
resistor.
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4
Functional Diagram
Typical Performance Characteristics
DS005261-3
Logic Input Threshold
Voltage vs Supply Voltage
DS005261-21
Delay from Falling Edge of
RD to Output data Valid vs
Load Capacitance
DS005261-22
CLK IN Schmitt Trip Levels
vs Supply Voltage
DS005261-23
Output Current vs
Temperature
DS005261-24
Typical Linearity Error
vs Clock Frequency
DS005261-25
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5
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