TL H 10556
ADC1031ADC1034ADC1038
10-Bit
Serial
IO
AD
Converters
with
Analog
Multiplexer
and
TrackHold
Function
January 1995
ADC1031 ADC1034 ADC1038 10-Bit Serial
I O A D Converters with Analog Multiplexer
and Track Hold Function
General Description
The ADC1031 ADC1034 and ADC1038 are 10-bit succes-
sive approximation A D converters with serial I O The seri-
al input for the ADC1034 and ADC1038 controls a single-
ended analog multiplexer that selects one of 4 input chan-
nels (ADC1034) or one of 8 input channels (ADC1038) The
ADC1034 and ADC1038 serial output data can be config-
ured into a left- or right-justified format
An input track hold is implemented by a capacitive refer-
ence ladder and sampled-data comparator This allows the
analog input to vary during the A D conversion cycle
Separate serial I O and conversion clock inputs are provid-
ed to facilitate the interface to various microprocessors
Applications
Y
Engine control
Y
Process control
Y
Instrumentation
Y
Test equipment
Features
Y
Serial I O (MICROWIRE
TM
compatible)
Y
Separate asynchronous converter clock and serial data
I O clock
Y
Analog input track hold function
Y
Ratiometric or absolute voltage referencing
Y
No zero or full scale adjustment required
Y
0V to 5V analog input range with single 5V power
supply
Y
TTL MOS input output compatible
Y
No missing codes
Key Specifications
Y
Resolution
10 bits
Y
Total unadjusted error
g
1 LSB (max)
Y
Single supply
5V
g
5%
Y
Power dissipation
20 mW (max)
Y
Max conversion time (f
C
e
3 MHz)
13 7 ms (max)
Y
Serial data exchange time (f
S
e
1 MHz)
10 ms (max)
TRI-STATE
is a registered trademark of National Semiconductor Corporation
MICROWIRE
TM
is a trademark of National Semiconductor Corporation
Connection Diagrams
Dual-In-Line and SO Packages
TL H 10556 4
Top View
ADC1031 In NS Package N08E
TL H 10556 3
Top View
ADC1034 In NS Packages
J16A M16B or N16E
TL H 10556 2
Top View
ADC1038 In NS Packages
J20A M20B or N20A
Ordering Information
Industrial
b
40 C
s
T
A
s
a
85 C
Package
ADC1031CIN
N08E
ADC1034CIN
N16E
ADC1034CIWM
M16B
ADC1038CIN
N20A
ADC1038CIWM
M20B
Military
b
55 C
s
T
A
s
a
125 C
Package
ADC1034CMJ
J16A
ADC1038CMJ
J20A
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Absolute Maximum Ratings
(Notes 1
3)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
)
6 5V
Voltage at Inputs and Outputs
b
0 3V to V
CC
a
0 3V
Input Current at Any Pin (Note 4)
g
5 mA
Package Input Current (Note 4)
g
20 mA
Package Dissipation
at T
A
e
25 C (Note 5)
500 mW
ESD Susceptability (Note 6)
2000V
Soldering Information
N Package (10 sec )
260 C
J Package (10 sec )
300 C
SO Package (Note 7)
Vapor Phase (60 sec )
215 C
Infrared (15 sec )
220 C
Storage Temperature
b
65 C to
a
150 C
Operating Ratings
(Notes 2
3)
Temperature Range
T
MIN
s
T
A
s
T
MAX
ADC1031CIN
b
40 C
s
T
A
s
a
85 C
ADC1034CIN
ADC1034CIWM
ADC1038CIN
ADC1038CIWM
ADC1034CMJ ADC1038CMJ
b
55 C
s
T
A
s
a
125 C
Supply Voltage (V
CC
)
4 75 V
DC
to 5 25 V
DC
Reference Voltage
(V
REF
e
V
REF
a
b
V
REF
b
)
2 0 V
DC
to V
CC
a
0 05V
Electrical Characteristics
The following specifications apply for V
CC
e
a
5 0V V
REF
e
a
4 6V f
S
e
700 kHz and f
C
e
3 MHz unless otherwise
specified Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 8)
(Note 9)
(Limits)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted
CIN CIWM CMJ
(Note 10)
g
1
LSB (max)
Error
Differential Linearity
10
Bits (min)
R
REF
Reference Input Resistance
8
kX
5
kX (min)
11
kX (max)
V
REF
Reference Voltage
(V
CC
a
0 05)
V (max)
V
IN
Analog Input Voltage
(Note 11)
(V
CC
a
0 05)
V (max)
(GND
b
0 05)
V (min)
On Channel Leakage Current
On Channel
e
5 V
DC
5 0
200
nA (max)
Off Channel
e
0 V
DC
500
nA (max)
(Note 12)
On Channel
e
0 V
DC
5 0
b
200
nA (max)
Off Channel
e
5 V
DC
b
500
nA (max)
Off Channel Leakage Current
On Channel
e
5 V
DC
5 0
b
200
nA (max)
Off Channel
e
0 V
DC
b
500
nA (max)
(Note 12)
On Channel
e
0 V
DC
5 0
200
nA (max)
Off Channel
e
5 V
DC
500
nA (max)
Power Supply
Zero Error
4 75 V
DC
s
V
CC
s
5 25 V
DC
g
1 4
LSB (max)
Sensitivity
Full Scale Error
g
1 4
LSB (max)
2
Electrical Characteristics
(Continued)
The following specifications apply for V
CC
e
a
5 0V V
REF
e
a
4 6V f
S
e
700 kHz and f
C
e
3 MHz unless otherwise
specified Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 8)
(Note 9)
(Limits)
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
Logical ``1'' Input Voltage
V
CC
e
5 25 V
DC
2 0
V (min)
V
IN(0)
Logical ``0'' Input Voltage
V
CC
e
4 75 V
DC
0 8
V (max)
I
IN(1)
Logical ``1'' Input Current
V
IN
e
5 0 V
DC
0 005
2 5
m
A (max)
I
IN(0)
Logical ``0'' Input Current
V
IN
e
0 V
DC
b
0 005
b
2 5
m
A (max)
V
OUT(1)
Logical ``1'' Output Voltage
V
CC
e
4 75 V
DC
I
OUT
e b
360 mA
2 4
V (min)
I
OUT
e b
10 mA
4 5
V (min)
V
OUT(0)
Logical ``0'' Output Voltage
V
CC
e
4 75 V
DC
0 4
V (max)
I
OUT
e
1 6 mA
I
OUT
TRI-STATE Output Current
V
OUT
e
0V
b
0 01
b
3
m
A (max)
V
OUT
e
5V
0 01
3
m
A (max)
I
SOURCE
Output Source Current
V
OUT
e
0V
b
14
b
6 5
mA (min)
I
SINK
Output Sink Current
V
OUT
e
V
CC
16
8 0
mA (min)
I
CC
Supply Current
CS
e
HIGH V
REF
Open
1 5
3
mA (max)
AC CHARACTERISTICS
f
C
Conversion Clock (C
CLK
)
0 7
MHz (min)
Frequency
4 0
3 0
MHz (max)
f
S
Serial Data Clock (S
CLK
)
f
C
e
3 MHz R L
e
``0''
183
kHz (min)
Frequency (Note 13)
f
C
e
3 MHz R L
e
``1''
622
kHz (min)
f
C
e
3 MHz R L
e
``0'' or R L
e
``1''
2
1 0
MHz (max)
T
C
Conversion Time
Not Including MUX Addressing and
41 (1 f
C
)
(max)
Analog Input Sampling Times
a
200 ns
t
CA
Analog Sampling Time
After Address is Latched CS
e
Low
4 5 (1 f
S
)
(max)
a
200 ns
t
ACC
Access Time Delay from CS or OE
OE
e
``0''
100
200
ns (max)
Falling Edge to DO Data Valid
t
SET-UP
Set-up Time of CS Falling
75
150
ns (min)
Edge to S
CLK
Rising Edge
t
1H
t
0H
Delay from OE or CS Rising
R
L
e
3 kX C
L
e
100 pF
100
120
ns (max)
Edge to DO TRI-STATE
t
HDI
DI Hold Time from S
CLK
Rising Edge
0
50
ns (min)
t
SDI
DI Set-up Time to S
CLK
Rising Edge
50
100
ns (min)
3
Electrical Characteristics
(Continued)
The following specifications apply for V
CC
e
a
5 0V V
REF
e
a
4 6V f
S
e
700 kHz and f
C
e
3 MHz unless otherwise
specified Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 8)
(Note 9)
(Limits)
AC CHARACTERISTICS
(Continued)
t
HDO
DO Hold Time from S
CLK
Falling Edge
R
L
e
30 kX C
L
e
100 pF
70
10
ns (min)
t
DDO
Delay from S
CLK
Falling
R
L
e
30 kX C
L
e
100 pF
150
250
ns (max)
Edge to DO Data Valid
t
RDO
DO Rise Time
R
L
e
30 kX
TRI-STATE to High
35
75
ns (max)
C
L
e
100 pF
Low to High
75
150
ns (max)
t
FDO
DO Fall Time
R
L
e
30 kX
TRI-STATE to Low
35
75
ns (max)
C
L
e
100 pF
High to Low
75
150
ns (max)
C
IN
Input Capacitance
Analog Inputs (CH0 CH7)
50
pF
All Other Inputs
7 5
pF
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur
Note 2
Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications
and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics
may degrade when the device is not operated under the listed test conditions
Note 3
All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 4
When the input voltage (V
IN
) at any pin exceeds the power supplies (V
IN
k
DGND or V
IN
l
V
CC
) the current at that pin should be limited to 5 mA The
20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins
Note 5
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
i
JA
and the ambient temperature T
A
The maximum
allowable power dissipation at any temperature is P
D
e
(T
Jmax
b
T
A
) i
JA
or the number given in the Absolute Maximum Ratings whichever is lower For this
device T
Jmax
e
125 C The typical thermal resistance (i
JA
) of these parts when board mounted follow ADC1031 with CIN suffixes 71 C W ADC1034 with CMJ
suffixes 52 C W ADC1034 with CIN suffixes 54 C W ADC1034 with CIWM suffixes 70 C W ADC1038 with CMJ suffixes 53 C W ADC1038 with CIN suffixes
46 C W ADC1038 with CIWM suffixes 64 C W
Note 6
Human body model 100 pF capacitor discharged through a 1 5 kX resistor
Note 7
See AN450 ``Surface Mounting Methods and Their Effect on Product Reliability'' or
Linear Databook section ``Surface Mount'' for other methods of
soldering surface mount devices
Note 8
Typicals are at T
J
e
25 C and represent most likely parametric norm
Note 9
Limits are guaranteed to National's AOQL (Average Outgoing Quality Level)
Note 10
Total unadjusted error includes offset full-scale linearity multiplexer and hold step errors
Note 11
Two on-chip diodes are tied to each analog input They will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than V
CC
supply Be careful during testing at low V
CC
levels (4 5V) as high level analog inputs (5V) can cause an input diode to conduct especially at
elevated temperatures which will cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode this means that as long as the
analog V
IN
does not exceed the supply voltage by more than 50 mV the output code will be correct Exceeding this range on an unselected channel will corrupt the
reading of a selected channel To achieve an absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4 950 V
DC
over
temperature variations initial tolerance and loading
Note 12
Channel leakage current is measured after the channel selection
Note 13
In order to synchronize the serial data exchange properly SARS needs to go low after completion of the serial I O data exchange If this does not occur
the output shift register will be reset and the correct output data lost The minimum limit for S
CLK
will depend on C
CLK
frequency and whether right-justified or left-
justified and can be determined by the following equations
f
S
l
(8 5 41) (f
C
) with right-justification (R L
e
``1'') and f
S
l
(2 5 41) (f
C
) with left-justification (R L
e
``0'')
4
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