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Электронный компонент: ADC1173

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ADC1173
8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter
General Description
The ADC1173 is a low power, 15 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
33 mW of power (typ). The ADC1173 uses a unique architec-
ture that achieves 7.6 Effective Bits. Output formatting is
straight binary coding.
The excellent DC and AC characteristics of this device, to-
gether with its low power consumption and +3V single supply
operation, make it ideally suited for many video, imaging and
communications applications, including use in portable
equipment. Furthermore, the ADC1173 is resistant to latchup
and the outputs are short-circuit proof. The top and bottom of
the ADC1173's reference ladder is available for connections,
enabling a wide range of input possibilities.
The ADC1173 is offered in SOIC (EIAJ) and TSSOP. It is de-
signed to operate over the commercial temperature range of
-20C to +75C.
Features
n
Internal Sample-and-Hold Function
n
Single +3V Operation
n
Internal Reference Bias Resistors
n
Industry Standard Pinout
n
TRI-STATE
Outputs
Key Specifications
n
Resolution
8 Bits
n
Maximum Sampling Frequency
15 MSPS (min)
n
THD
-56 dB (typ)
n
DNL
0.8 LSB (max)
n
ENOB at 3.58 MHz Input
7.6 Bits (typ)
n
Guaranteed No Missing Codes
n
Differential Phase
0.5 Degree (max)
n
Differential Gain
1.5% (typ)
n
Power Consumption
33mW (typ)
(excluding reference current)
Applications
n
Video Digitization
n
Digital Still Cameras
n
Set Top Boxes
n
Camcorders
n
Personal Computer Video
n
Digital Television
n
CCD Imaging
n
Electro-Optics
Ordering Information
ADC1173CIJM
SOIC (EIAJ)
ADC1173CIJMX
SOIC (EIAJ) (tape & reel)
ADC1173CIMTC
TSSOP
ADC1173CIMTCX
TSSOP (tape & reel)
Pin Configuration
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS100890-1
February 1999
ADC1
173
8-Bit,
3-V
olt,
15MSPS,
33mW
A/D
Converter
1999 National Semiconductor Corporation
DS100890
www.national.com
Block Diagram
Pin Descriptions and Equivalent Circuits
Pin
No.
Symbol
Equivalent Circuit
Description
19
V
IN
Analog signal input. Conversion range is V
RB
to
V
RT
.
16
V
RTS
Reference Top Bias with internal pull-up resistor.
Short this pin to V
RT
to self bias the reference
ladder.
17
V
RT
Analog Input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
to AV
DD
. Voltage on V
RT
and V
RB
inputs define the
V
IN
conversion range. Bypass well. See Section 2.0
for more information.
23
V
RB
Analog Input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0V
to 2.0V. Voltage on V
RT
and V
RB
inputs define the
V
IN
conversion range. Bypass well. See Section 2.0
for more information.
DS100890-2
www.national.com
2
Pin Descriptions and Equivalent Circuits
(Continued)
Pin
No.
Symbol
Equivalent Circuit
Description
22
V
RBS
Reference Bottom Bias with internal pull down
resistor. Short to V
RB
to self bias the reference
ladder.
1
OE
CMOS/TTL compatible Digital input that, when low,
enables the digital outputs of the ADC1173. When
high, the outputs are in a high impedance state.
12
CLK
CMOS/TTL compatible digital clock Input. V
IN
is
sampled on the falling edge of CLK input.
3 thru
10
D0-D7
Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are
enabled by bringing the OE pin low.
11, 13
DV
DD
Positive digital supply pin. Connect to a clean, quiet
voltage source of +3V. AV
DD
and DV
DD
should have
a common source and be separately bypassed with
a 10F capacitor and a 0.1F ceramic chip
capacitor. See Section 3.0 for more information.
2, 24
DV
SS
The ground return for the digital supply. AV
SS
and
DV
SS
should be connected together close to the
ADC1173.
14,
15, 18
AV
DD
Positive analog supply pin. Connected to a clean,
quiet voltage source of +3V. AV
DD
and DV
DD
should
have a common source and be separately bypassed
with a 10 F capacitor and a 0.1 F ceramic chip
capacitor. See Section 3.0 for more information.
20, 21
AV
SS
The ground return for the analog supply. AV
SS
and
DV
SS
should be connected together close to the
ADC1173 package.
www.national.com
3
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
AV
DD
, DV
DD
6.5V
Voltage on Any Pin
-0.3V to 6.5V
V
RT
, V
RB
AV
DD
to V
SS
CLK, OE Voltage
-0.05 to (AV
DD
+ 0.05V)
Digital Output Voltage
DV
SS
to DV
DD
Input Current (Note 3)
25mA
Package Input Current
(Note 3)
50mA
Package Dissipation at 25C
(Note 4)
ESD Susceptibility (Note 5)
Human Body Model
2000V
Machine Model
200V
Soldering Temp., Infared, 10
sec. (Note 6)
300C
Storage Temperature
-65C to +150C
Operating Ratings
(Notes 1, 2)
Temperature Range
-20C
T
A
+75C
AV
DD
, DV
DD
+2.7V to +3.6V
|AV
SS
-DV
SS
|
0V to 100 mV
V
RT
1.0V to AV
DD
V
RB
0V to 2.0V
V
IN
Voltage Range
V
RB
to V
RT
Converter Electrical Characteristics
The following specifications apply for AV
DD
= DV
DD
= +3.0V
DC
, OE = 0V, V
RT
= +2.0V, V
RB
= 0V, C
L
= 20 pF, f
CLK
= 15MHz
at 50% duty cycle. Boldface limits apply for T
A
= T
MIN
to T
MAX
; all other limits T
A
= 25C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
Units
DC Accuracy
INL
Integral Non Linearity
0.5
1.3
LSB( max)
DNL
Differential Non Linearity
0.4
0.85
LSB( max)
Missing Codes
0
(max)
E
OT
Top Offset
-12
mV
E
OB
Bottom Offset
+1.0
mV
Video Accuracy
DP
Differential Phase Error
f
in
= 3.58 MHz sine wave
0.5
Degree
DG
Differential Gain Error
f
in
= 3.58 MHz sine wave
1.5
%
Analog Input and Reference Characteristics
V
IN
Input Range
2.0
V
RB
V
RT
V(min)
V(max)
C
IN
V
IN
Input Capacitance
V
IN
= 1.5V + 0.7Vrms
(CLK
LOW)
4
pF
(CLK
HIGH)
11
R
IN
Input Resistance
>
1
M
BW
Analog Input Bandwidth
120
MHz
R
RT
Top Reference Resistor
360
R
REF
Reference Ladder
Resistance
V
RT
to V
RB
300
200
(min)
400
(max)
R
RB
Bottom Reference Resistor
90
I
REF
Reference Ladder Current
V
RT
=V
RTS
, V
RB
=V
RBS
4.2
mA
V
RT
=V
RTS
,V
RB
=AV
SS
4.8
mA
V
RT
Reference Top Self Bias
Voltage
V
RT
connected to V
RTS
V
RB
connected to V
RBS
1.56
1.45
1.65
V(min)
V(max)
V
RB
Reference Bottom Self Bias
Voltage
V
RT
connected to V
RTS
0.36
0.32
V(min)
V
RB
connected to V
RBS
0.40
V(max)
V
RTS
-
V
RBS
Self Bias Voltage Delta
V
RT
connected to V
RTS
,
V
RB
connected to V
RBS
1.2
1.1
1.3
Amin
Amax
V
RT
connected to V
RTS
,
V
RB
connected to V
SS
1.38
V
www.national.com
4
Converter Electrical Characteristics
(Continued)
The following specifications apply for AV
DD
= DV
DD
= +3.0V
DC
, OE = 0V, V
RT
= +2.0V, V
RB
= 0V, C
L
= 20 pF, f
CLK
= 15MHz
at 50% duty cycle. Boldface limits apply for T
A
= T
MIN
to T
MAX
; all other limits T
A
= 25C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
Units
Analog Input and Reference Characteristics
V
RT
-
V
RB
Reference Voltage Delta
2
1.0
V(min)
V
A
V(max)
Power Supply Characteristics
IA
DD
Analog Supply Current
DV
DD
= AV
DD
= 3.6V
6.8
mA
ID
DD
Digital Supply Curretn
DV
DD
= AV
DD
= 3.6V
2.3
mA
IAV
DD
+
IDV
DD
Total Operating Current
DV
DD
AV
DD
= 3.6V,
9.1
11
mA
DV
DD
= AV
DD
= 3.6V, CLK Low
(Note 10)
5.8
mA
Power Consumption
DV
DD
= AV
DD
= 3.6V
33
40
mW
CLK, OE Digital Input Characteristics
V
IH
Logical High Input Voltage
DV
DD
= AV
DD
= 3.6V
2.2
V (min)
V
IL
Logical Low Input Voltage
DV
DD
= AV
DD
= 3.6V
0.8
V (max)
I
IH
Logical High Input Current
V
IH
= DV
DD
= AV
DD
= 3.6V
5
A
I
IL
Logic Low Input Current
V
IL
= 0V, DV
DD
= AV
DD
= 3.6V
-5
A
C
IN
Logic Input Capacitance
5
pF
Digital Output Characteristics
V
OH
High Level Output Voltage
DV
DD
= 2.7V, I
OH
= -360A
2.4
V(min)
DV
DD
= 2.7V, I
OH
= -1.1mA
2.1
1.9
V(min)
V
OL
Low Level Output Voltage
DV
DD
= 2.7V, I
OL
= 1.6mA
0.32
0.6
V(max)
I
OZH
,
I
OZL
Tri-State
Leakage Current
DV
DD
= 3.6V, OE = DV
DD
,
V
OL
= 0V or V
OH
= DV
DD
20
A
AC Electrical Characteristics
f
C1
Maximum Conversion Rate
20
15
MHz(min)
f
C2
Minimum Conversion Rate
1
MHz
t
OD
-0
Output Delay
CLK high to low data valid
28
ns(max)
t
OD
-1
Output Delay
CLK low to high data valid
24
ns(max)
Pipline Delay (Latency)
2.5
Clock
Cycles
t
DS
Sampling (Aperture) Delay
CLK low to acquissition of data
3
ns
t
AJ
Aperture Jitter
30
ps rms
t
OH
Output Hold Time
CLK high to data invalid
15
ns
t
EN
OE Low to Data Valid
Loaded as in
Figure 2
22
ns
t
DIS
OE High to High Z State
Loaded as in
Figure 2
12
ns
ENOB
Effective Number of Bits
f
IN
= 1.31 MHz
f
IN
= 3.58 MHz
f
IN
= 7.5 MHz
7.7
7.6
7.4
7.0
Bits (min)
SINAD
Signal-to- Noise & Distortion
f
IN
= 1.31 MHz
f
IN
= 3.58 MHz
f
IN
= 7.5 MHz
49
47.7
46.5
43
dB(min)
SNR
Signal-to-Noise Ratio
f
IN
= 1.31 MHz
f
IN
= 3.58 MHz
f
IN
= 7.5 MHz
49
48.7
48.0
44
dB(min)
SFDR
Spurious Free Dynamic
Range
f
IN
= 1.31 MHz
f
IN
= 3.58 MHz
f
IN
= 7.5 MHz
65
55
51
dB
THD
Total Harmonic Distortion
f
IN
= 1.31 MHz
f
IN
= 3.58 MHz
f
IN
= 7.5 MHz
-62
-54
-51
dB
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5