ChipFind - документация

Электронный компонент: ADC11DL066CIVS

Скачать:  PDF   ZIP

Document Outline

ADC11DL066
Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D
Converter w/Internal Reference
General Description
The ADC11DL066 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 11-bit digital words at 66 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipeline architecture with digital error correction and an on-
chip sample-and-hold circuit to minimize die size and power
consumption while providing excellent dynamic performance
and a 450 MHz Full Power Bandwidth. Operating on a single
3.3V power supply, the ADC11DL066 achieves 10.3 effective
bits and consumes just 686 mW at 66 MSPS, including the
reference current. The Power Down feature reduces power
consumption to 75 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
REF
with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADCs are available on separate 11-bit buses with an
output data format choice of offset binary or two's comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC11DL066 can be con-
nected to a separate supply voltage in the range of 2.4V to
the digital supply voltage.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of -40C to
+85C. An evaluation board is available to ease the evalua-
tion process.
Features
n
Single +3.3V supply operation
n
Internal sample-and-hold
n
Outputs 2.4V to 3.3V compatible
n
Power down mode
n
On-chip reference
Key Specifications
n
Resolution
11 Bits
n
DNL
0.25 LSB (typ)
n
SNR (f
IN
= 10 MHz)
64 dB (typ)
n
SFDR (f
IN
= 10 MHz)
80 dB (typ)
n
Data Latency
6 Clock Cycles
n
Power Consumption
-- Operating
686 mW (typ)
-- Power Down
75 mW (typ)
Applications
n
Ultrasound and Imaging
n
Instrumentation
n
Communications Receivers
n
Sonar/Radar
n
xDSL
n
Cable Modems
n
DSP Front Ends
Connection Diagram
20077301
20040326
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
March 2004
ADC1
1DL066
Dual
1
1-Bit,
66
MSPS,
450
MHz
Input
Bandwidth
A/D
Converter
w/Internal
Reference
2004 National Semiconductor Corporation
DS200773
www.national.com
Ordering Information
Industrial (-40C
T
A
+85C)
Package
ADC11DL066CIVS
64 Pin TQFP
Block Diagram
20077302
ADC1
1DL066
www.national.com
2
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
15
2
V
INA+
V
INB+
Differential analog Inputs. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 V
P-P
with each
input pin voltage centered on a common mode voltage, V
CM
.
The negative input pins may be connected to V
CM
for
single-ended operation, but a differential input signal is
required for best performance.
16
1
V
INA-
V
INB-
7
V
REF
Reference input. This pin should be bypassed to AGND with
a 0.1 F capacitor when an external reference is used. V
REF
is 1.0V nominal and should be between 0.8V to 1.5V.
11
INT/EXT REF
Reference source select pin. With a logic low at this pin the
internal 1.0V reference is selected and the V
REF
pin need
not be driven. With a logic high on this pin an external
reference voltage should be applied to V
REF
input pin 7.
13
5
V
RPA
V
RPB
These pins are high impedance reference bypass pins.
Bypass per Section 1.2. DO NOT LOAD these pins.
14
4
V
RMA
V
RMB
12
6
V
RNA
V
RNB
DIGITAL I/O
60
CLK
Digital clock input. The range of frequencies for this input is
as specified in the electrical tables with guaranteed
performance at 66 MHz. The input is sampled on the rising
edge of this input.
22
41
OEA
OEB
OEA and OEB are the output enable pins that, when low,
holds their respective data output pins in the active state.
When either of these pins is high, the corresponding outputs
are in a high impedance state.
59
PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
21
OF
Output Format pin. A logic low on this pin causes output
data to be in offset binary format. A logic high on this pin
causes the output data to be in 2's complement format.
ADC1
1DL066
www.national.com
3
Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
2529
3439
DA0DA10
Digital data output pins that make up the 11-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA10 and DB10 are the MSBs of the output
words. Output levels are TTL/CMOS compatible.
4347
5257
DB0DB10
ANALOG POWER
9, 18, 19,
62, 63
V
A
Positive analog supply pins. These pins should be connected
to a quiet +3.3V source and bypassed to AGND with 0.1 F
capacitors located within 1 cm of these power pins, and with
a 10 F capacitor.
3, 8, 10, 17,
20, 61, 64
AGND
The ground return for the analog supply.
DIGITAL POWER
33, 48
V
D
Positive digital supply pin. This pin should be connected to
the same quiet +3.3V source as is V
A
and be bypassed to
DGND with a 0.1 F capacitor located within 1 cm of the
power pin and with a 10 F capacitor.
32, 49
DGND
The ground return for the digital supply.
24, 42
DGND
These two pins are grounded internally and may be
grounded or left unconnected.
30, 51
V
DR
Positive digital supply pin for the ADC11DL066's output
drivers. This pin should be connected to a voltage source of
+2.4V to V
D
and be bypassed to DR GND with a 0.1 F
capacitor. If the supply for this pin is different from the
supply used for V
A
and V
D
, it should also be bypassed with
a 10 F tantalum capacitor. V
DR
should never exceed the
voltage on V
D
. All bypass capacitors should be located
within 1 cm of the supply pin.
23, 31, 40,
50, 58
DR GND
The ground return for the digital supply for the
ADC11DL066's output drivers. These pins should be
connected to the system digital ground, but not be
connected in close proximity to the ADC11DL066's DGND or
AGND pins. See Section 5 (Layout and Grounding) for more
details.
ADC1
1DL066
www.national.com
4
Absolute Maximum Ratings
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
A
, V
D
, V
DR
4.2V
|V
A
V
D
|
100 mV
Voltage on Any Input or Output Pin
-0.3V to (V
A
or V
D
+0.3V)
Input Current at Any Pin (Note 3)
25 mA
Package Input Current (Note 3)
50 mA
Package Dissipation at T
A
= 25C
See (Note 4)
ESD Susceptibility
Human Body Model (Note 5)
2500V
Machine Model (Note 5)
250V
Soldering Temperature,
Infrared, 10 sec. (Note 6)
235C
Storage Temperature
-65C to +150C
Operating Ratings
(Notes 1, 2)
Operating Temperature
-40C
T
A
+85C
Supply Voltage (V
A
, V
D
)
+3.0V to +3.6V
Output Driver Supply (V
DR
)
+2.4V to V
D
V
REF
Input
0.8V to 1.5V
CLK, PD, OE
-0.05V to (V
D
+ 0.05V)
Analog Input Pins
0V to (V
A
- 0.5V)
V
CM
0.5V to 1.8V
|AGNDDGND|
100mV
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
A
= V
D
= +3.3V,
V
DR
= +2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
REF
= +1.0V, f
CLK
= 66 MHz, f
IN
= 10 MHz, t
r
= t
f
= 2 ns, C
L
= 15 pF/pin.
Boldface limits apply for T
J
= T
MIN
to T
MAX
: all other limits T
J
= 25C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
11
Bits (min)
INL
Integral Non Linearity (Note 11)
0.5
1.6
LSB (max)
DNL
Differential Non Linearity
0.25
0.68
LSB (max)
PGE
Positive Gain Error
0.4
4
%FS (max)
NGE
Negative Gain Error
-0.1
3.6
%FS (max)
TC GE
Gain Error Tempco
-40C
T
A
+85C
0.5
ppm/C
V
OFF
Offset Error (V
IN
+ = V
IN
-)
-0.18
+1.3
-1.6
%FS (max)
%FS (min)
TC
V
OFF
Offset Error Tempco
-40C
T
A
+85C
0.1
ppm/C
Under Range Output Code
0
0
Over Range Output Code
2047
2047
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
Common Mode Input Voltage
1.0
0.5
V (min)
1.8
V (max)
C
IN
V
IN
Input Capacitance (each pin to
GND)
V
IN
= 2.5 Vdc
+ 0.7 V
rms
(CLK LOW)
8
pF
(CLK HIGH)
7
pF
V
REF
Reference Voltage (Note 13)
1.00
0.8
V (min)
1.5
V (max)
Reference Input Resistance
100
M
ADC1
1DL066
www.national.com
5