ADC12041
12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital
Converter
General Description
Operating from a single 5V power supply, the ADC12041 is a
12 bit + sign, parallel I/O, self-calibrating, sampling
analog-to-digital converter (ADC). The maximum sampling
rate is 216 kHz. On request, the ADC goes through a
self-calibration process that adjusts linearity, zero and
full-scale errors.
The ADC12041 can be configured to work with many popular
microprocessors/microcontrollers and DSPs including Na-
tional's HPC family, Intel386 and 8051, TMS320C25, Mo-
torola MC68HC11/16, Hitachi 64180 and Analog Devices
ADSP21xx.
For complementary voltage references see the LM4040,
LM4041 or LM9140.
Features
n
Fully differential analog input
n
Programmable acquisition times and user-controllable
throughput rates
n
Programmable data bus width (8/13 bits)
n
Built-in Sample-and-Hold
n
Programmable auto-calibration and auto-zero cycles
n
Low power standby mode
n
No missing codes
Key Specifications
(f
CLK
= 12 MHz)
n
Resolution
12-bits + sign
n
13-bit conversion time
3.6 s, max
n
13-bit throughput rate
216 ksamples/s, min
n
Integral Linearity Error (ILE)
1 LSB, max
n
Single supply
+5V
10%
n
V
IN
range
GND to V
A
+
n
Power consumption
-- Normal operation
33 mW, max
-- Stand-by mode
75 w, max
Applications
n
Medical instrumentation
n
Process control systems
n
Test equipment
n
Data logging
n
Inertial guidance
Block Diagram
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS012441-1
April 2000
ADC12041
12-Bit
Plus
Sign
216
kHz
Sampling
Analog-to-Digital
Converter
2000 National Semiconductor Corporation
DS012441
www.national.com
Connection Diagrams
Ordering Information
Industrial Temperature Range
-40C
T
A
+85C
NS
Package
Number
ADC12041CIV
PLCC
ADC12041CIMSA
SSOP
28-Pin SSOP
DS012441-2
Order Number ADC12041CIMSA
See NS Package Number MSA28
28-Pin PLCC
DS012441-3
Order Number ADC12041CIV
See NS Package Number V28A
ADC12041
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2
Pin Descriptions
PLCC and
Pin
SSOP Pkg.
Name
Description
Pin Number
5
6
V
IN
+
V
IN
-
The analog ADC inputs. V
IN
+ is the non-inverting (positive) input and V
IN
- is the inverting (negative)
input into the ADC.
10
V
REF
+
Positive reference input. The operating voltage range for this input is 1V
V
REF
+
V
A
+ (see
Figure
3 and Figure 4). This pin should be bypassed to AGND at least with a parallel combination of a 10
F and a 0.1 F (ceramic) capacitor. The capacitors should be placed as close to the part as
possible.
9
V
REF
-
Negative reference input. The operating voltage range for this input is 0V
V
REF
-
V
REF
+ -1 (see
Figure 3 and Figure 4). This pin should be bypassed to AGND at least with a parallel combination of
a 10 F and a 0.1 F (ceramic) capacitor. The capacitors should be placed as close to the part as
possible.
4
WMODE
The logic state of this pin at power-up determines which edge of the write signal (WR ) will latch in
data from the data bus. If tied low, the ADC12041 will latch in data on the rising edge of the WR
signal. If tied to a logic high, data will be latched in on the falling edge of the WR signal. The state of
this pin should not be changed after power-up.
27
SYNC
The SYNC pin can be programmed as an input or an output. The Configuration register's bit b4
controls the function of this pin. When programmed as an input pin (b4 = 1), a rising edge on this
pin causes the ADC's sample-and-hold to hold the analog input signal and begin conversion. When
programmed as an output pin (b4 = 0), the SYNC pin goes high when a conversion begins and
returns low when completed.
1220
2326
D0D8
D9D12
13-bit Data bus of the ADC12041. D12 is the most significant bit and D0 is the least significant. The
BW(bus width) bit of the Configuration register (b3) selects between an 8-bit or 13-bit data bus width.
When the BW bit is cleared (BW = 0), D7D0 are active and D12D8 are always in TRI-STATE
.
When the BW bit is set (BW = 1), D12D0 are active.
28
CLK
The clock input pin used to drive the ADC12041. The operating range is 0.05 MHz to 12 MHz.
1
WR
WR is the active low WRITE control input pin. A logic low on this pin and the CS will enable the
input buffers of the data pins D12D0. The signal at this pin is used by the ADC12041 to latch in
data on D12D0. The sense of the WMODE pin at power-up will determine which edge of the WR
signal the ADC12041 will latch in data. See WMODE pin description.
2
RD
RD is the active low read control input pin. A logic low on this pin and CS will enable the active
output buffers to drive the data bus.
3
CS
CS is the active low Chip Select input pin. Used in conjunction with the WR and RD signals to
control the active data bus input/output buffers of the data bus.
11
RDY
RDY is an active low output pin. The signal at this pin indicates when a requested function has
begun or ended. Refer to section Functional Description and the digital timing diagrams for more
detail.
7
V
A
+
Analog supply input pin. The device operating supply voltage range is +5V
10%. Accuracy is
guaranteed only if the V
A
+ and V
D
+ are connected to the same potential. This pin should be
bypassed to AGND with a parallel combination of a 10 F and a 0.1 F (ceramic) capacitor. The
capacitors should be placed as close to the supply pins of the part as possible.
8
AGND
Analog ground pin. This is the device's analog supply ground connection. It should be connected
through a low resistance and low inductance ground return to the system power supply.
21
V
D
+
Digital supply input pins. The device operating supply voltage range is +5V
10%. Accuracy is
guaranteed only if the V
A
+ and V
D
+ are connected to the same potential. This pin should be
bypassed to DGND with a parallel combination of a 10 F and a 0.1 F (ceramic) capacitor. The
capacitors should be placed as close to the supply pins of the part as possible.
22
DGND
Digital ground pin. This is the device's digital supply ground connection. It should be connected
through a low resistance and low inductance ground return to the system power supply.
ADC12041
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3
Absolute Maximum Ratings
(Notes 1, 2)
Supply Voltage (V
A
+ and V
D
+)
6.0V
Voltage at all Inputs
-0.3V to V
+
+ 0.3V
|V
A
+ - V
D
+|
300 mV
|AGND - DGND|
300 mV
Input Current at Any Pin (Note 3)
30 mA
Package Input Current (Note 3)
120 mA
Power Dissipation (Note 4)
at T
A
= 25C
500 mW
Storage Temperature
-65C to +150C
Lead Temperature
SSOP Package
Vapor Phase (60 sec.)
210C
Infared (15 sec.)
220C
V Package, Infared (15 sec.)
300C
ESD Susceptibility (Note 5)
3.0 kV
Operating Ratings
(Notes 1, 2, 6, 7, 8, 9)
Temperature Range
(T
min
T
A
T
max
)
-40C
T
A
85C
Supply Voltage
V
A
+, V
D
+
4.5V to 5.5V
|V
A
+ - V
D
+|
100 mV
|AGND - DGND|
100 mV
V
IN
Voltage
Range at all Inputs
GND
V
IN
+
V
A
+
V
REF
+ Input Voltage
1V
V
REF
+
V
A
+
V
REF
- Input Voltage
0
V
REF
-
V
REF
+ - 1V
V
REF
+ - V
REF
-
1V
V
REF
V
A
+
V
REF
Common Mode
(Note 16)
0.1 V
A
+
V
REFCM
0.6 V
A
+
Converter DC Characteristics
The following specifications apply to the ADC12041 for V
A
+ = V
D
+ = 5V, V
REF
+ = 4.096V, V
REF
- = 0.0V, 12-bit + sign con-
version mode, f
CLK
= 12.0 MHz, R
S
= 25
, source impedance for V
REF
+ and V
REF
-
1
, fully differential input with fixed
2.048V common-mode voltage (V
INCM
), and minimum acquisition time, unless otherwise specified. Boldface limits apply for
T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 10)
(Note 11)
(Limit)
Resolution with No Missing Codes
After Auto-Cal
13
Bits (max)
ILE
Positive and Negative Integral
After Auto-Cal
0.6
1
LSB (max)
Linearity Error
(Notes 12, 17)
DNL
Differential Non-Linearity
After Auto-Cal
1
LSB (max)
Zero Error
After Auto-Cal (Notes 13, 17)
V
INCM
= 5.0V
5.5
LSB (max)
V
INCM
= 2.048V
2.0
LSB (max)
V
INCM
= 0V
5.5
LSB (max)
Positive Full-Scale Error
After Auto-Cal (Notes 12, 17)
1.0
2.5
LSB (max)
Negative Full-Scale Error
After Auto-Cal (Notes 12, 17)
1.0
2.5
LSB (max)
DC Common Mode Error
After Auto-Cal (Note 14)
2
5.5
LSB (max)
TUE
Total Unadjusted Error
After Auto-Cal (Note 18)
1
LSB
Power Supply Characteristics
The following specifications apply to the ADC12041 for V
A
+ = V
D
+ = 5V, V
REF
+ = 4.096V, V
REF
- = 0.0V, 12-bit + sign conver-
sion mode, f
CLK
= 12.0 MHz, R
S
= 25
, source impedance for V
REF
+ and V
REF
- 1
, fully differential input with fixed 2.048V
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
PSS
Power Supply Sensitivity
V
D
+ = V
A
+ = 5.0V
10% (Note 15)
Zero Error
V
REF
+ = 4.096V
0.1
LSB
Full-Scale Error
V
REF
- = 0V
0.5
LSB
Linearity Error
0.1
LSB
I
D
+
V
D
+ Digital Supply Current
Start Command (Performing a conversion)
with SYNC configured as an input and driven
with a 214 kHz signal. Bus width set to 13.
f
CLK
= 12.0 MHz, Reset Mode
850
A
f
CLK
= 12.0 MHz, Conversion
2.45
2.6
mA (max)
ADC12041
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4
Power Supply Characteristics
(Continued)
The following specifications apply to the ADC12041 for V
A
+ = V
D
+ = 5V, V
REF
+ = 4.096V, V
REF
- = 0.0V, 12-bit + sign conver-
sion mode, f
CLK
= 12.0 MHz, R
S
= 25
, source impedance for V
REF
+ and V
REF
- 1
, fully differential input with fixed 2.048V
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
I
A
+
V
A
+ Analog Supply Current
Start Command (Performing a conversion)
with SYNC configured as an input and driven
with a 214 kHz signal. Bus width set to 13.
f
CLK
= 12.0 MHz, Reset Mode
2.3
mA
f
CLK
= 12.0 MHz, Conversion
2.3
4.0
mA (max)
I
ST
Standby Supply Current
Standby Mode
(I
D
+ + I
A
+)
f
CLK
= Stopped
5
15
A (max)
f
CLK
= 12.0 MHz
100
120
A (max)
Analog Input Characteristics
The following specifications apply to the ADC12041 for V
A
+ = V
D
+ = 5V, V
REF
+ = 4.096V, V
REF
- = 0.0V, 12-Bit + sign conver-
sion mode, f
CLK
= 12.0 MHz, R
S
= 25
, source impedance for V
REF
+ and V
REF
+
1
, fully differential input with fixed 2.048V
common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
I
IN
V
IN
+ and V
IN
- Input Leakage Current
V
IN
+ = 5V
0.05
2.0
A (max)
V
IN
- = 0V
R
ON
ADC Input On Resistance
V
IN
= 2.5V
1000
Refer to section titled INPUT CURRENT.
CV
IN
ADC Input Capacitance
10
pF
Reference Inputs
The following specifications apply to the ADC12041 for V
A
+ = V
D
+ = 5V, V
REF
+ = 4.096V, V
REF
- = 0.0V, 12-bit + sign con-
version mode, f
CLK
= 12.0 MHz, R
S
= 25
, source impedance for V
REF
+ and V
REF
-
1
, fully differential input with fixed
2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
I
REF
Reference Input Current
V
REF
+ 4.096V, V
REF
- = 0V
Analog Input Signal: 1 kHz
145
A
(Note 20) 80 kHz
136
A
C
REF
Reference Input Capacitance
85
pF
Digital Logic Input/Output Characteristics
The following specifications apply to the ADC12041 for V
A
+ = V
D
+ = 5V, V
REF
+ = 4.096V, V
REF
- = 0.0V, 12-bit + sign con-
version mode, f
CLK
= 12.0 MHz, R
S
= 25
, source impedance for V
REF
+ and V
REF
-
1
, fully differential input with fixed
2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C
Symbol
Parameter
Conditions
Typical
Limits
Unit
(Note 10)
(Note 11)
(Limit)
V
IH
Logic High Input Voltage
V
A
+ = V
D
+ = 5.5V
2.2
V (min)
V
IL
Logic Low Input Voltage
V
A
+ = V
D
+ = 4.5V
0.8
V (max)
I
IH
Logic High Input Current
V
IN
= 5V
0.035
2.0
A (max)
I
IL
Logic Low Input Current
V
IN
= 0V
-0.035
-2.0
A (max)
V
OH
Logic High Output Voltage
V
A
+ = V
D
+ = 4.5V
2.4
2.4
V (min)
I
OUT
= -1.6 mA
ADC12041
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