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Электронный компонент: ADC12062

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TL H 11490
ADC12062
12-Bit
1
MHz
75
mW
AD
Converter
with
Input
Multiplexer
and
SampleHold
December 1994
ADC12062
12-Bit 1 MHz 75 mW A D Converter
with Input Multiplexer and Sample Hold
General Description
Using an innovative multistep conversion technique the
12-bit ADC12062 CMOS analog-to-digital converter digitizes
signals at a 1 MHz sampling rate while consuming a maxi-
mum of only 75 mW on a single
a
5V supply
The
ADC12062 performs a 12-bit conversion in three lower-res-
olution ``flash'' conversions yielding a fast A D without the
cost and power dissipation associated with true flash ap-
proaches
The analog input voltage to the ADC12062 is tracked and
held by an internal sampling circuit allowing high frequency
input signals to be accurately digitized without the need for
an external sample-and-hold circuit The multiplexer output
is available to the user in order to perform additional exter-
nal signal processing before the signal is digitized
When the converter is not digitizing signals it can be placed
in the Standby mode typical power consumption in this
mode is 100 mW
Features
Y
Built-in sample-and-hold
Y
Single
a
5V supply
Y
Single channel or 2 channel multiplexer operation
Y
Low Power Standby mode
Key Specifications
Y
Sampling rate
1 MHz (min)
Y
Conversion time
740 ns (typ)
Y
Signal-to-Noise Ratio f
IN
e
100 kHz
69 5 dB (min)
Y
Power dissipation (f
s
e
1 MHz)
75 mW (max)
Y
No missing codes over temperature
Guaranteed
Applications
Y
Digital signal processor front ends
Y
Instrumentation
Y
Disk drives
Y
Mobile telecommunications
Y
Waveform digitizers
Block Diagram
TL H 11490 1
Ordering Information
Industrial
(
b
40 C
s
T
A
s
a
85 )
Package
ADC12062BIV
V44 Plastic Leaded Chip Carrier
ADC12062BIVF
VGZ44A Plastic Quad Flat Package
ADC12062CIV
V44 Plastic Leaded Chip Carrier
ADC12062CIVF
VGZ44A Plastic Quad Flat Package
ADC12062EVAL
Evaluation Board
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M75 Printed in U S A
Absolute Maximum Ratings
(Notes 1 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
CC
e
DV
CC
e
AV
CC
)
b
0 3V to
a
6V
Voltage at Any Input or Output
b
0 3V to V
CC
a
0 3V
Input Current at Any Pin (Note 3)
25 mA
Package Input Current (Note 3)
50 mA
Power Dissipation (Note 4)
875 mW
ESD Susceptibility (Note 5)
2000V
Soldering Information (Note 6)
V Package Infrared 15 seconds
a
300 C
VF Package
Vapor Phase (60 seconds)
a
215 C
Infrared (15 seconds)
a
220 C
Storage Temperature Range
b
65 C to
a
150 C
Maximum Junction Temperature (T
JMAX
)
150 C
Operating Ratings
(Notes 1 2)
Temperature Range
T
MIN
s
T
A
s
T
MAX
ADC12062BIV ADC12062CIV
ADC12062BIVF ADC12062CIVF
b
40 C
s
T
A
s
a
85 C
Supply Voltage Range (DV
CC
e
AV
CC
)
4 5V to 5 5V
Converter Characteristics
The following specifications apply for DV
CC
e
AV
CC
e
a
5V V
REFa(SENSE)
e
a
4 096V V
REFb(SENSE)
e
AGND and f
s
e
1 MHz unless otherwise specified Boldface limits apply for T
A
e
T
J
from
T
MIN
to T
MAX
all other limits T
A
e
T
J
e a
25 C
Symbol
Parameter
Conditions
Typ
Limit
Units
(Note 7)
(Note 8)
(Limit)
Resolution
12
Bits
Differential Linearity Error
T
A
e
25 C
g
0 4
g
0 8
LSB (max)
T
MIN
to T
MAX
g
0 95
LSB (max)
Integral Linearity Error
T
MIN
to T
MAX
(BIV Suffix)
g
0 4
g
1 0
LSB (max)
(Note 9)
T
A
e a
25 C (CIV Suffix)
g
0 4
g
1 0
LSB (max)
T
MIN
to T
MAX
(CIV Suffix)
g
1 5
LSB (max)
Offset Error
T
MIN
to T
MAX
(BIV Suffix)
g
0 3
g
1 25
LSB (max)
T
A
e a
25 C (CIV Suffix)
g
0 3
g
1 25
LSB (max)
T
MIN
to T
MAX
(CIV Suffix)
g
2 0
LSB (max)
Full Scale Error
T
MIN
to T
MAX
(BIV Suffix)
g
0 2
g
1 0
LSB (max)
T
A
e a
25 C (CIV Suffix)
g
0 2
g
1 0
LSB (max)
T
MIN
to T
MAX
(CIV Suffix)
g
1 5
LSB (max)
Power Supply Sensitivity
DV
CC
e
AV
CC
e
5V
g
10%
g
1 0
LSB (max)
(Note 15)
R
REF
Reference Resistance
750
500
X
(min)
1000
X
(max)
V
REF(a)
V
REFa(SENSE)
Input Voltage
AV
CC
V (max)
V
REF(b)
V
REFb(SENSE)
Input Voltage
AGND
V (min)
V
IN
Input Voltage Range
To V
IN1
V
IN2
or ADC IN
AV
CC
a
0 05V
V (max)
AGND
b
0 05V
V (min)
ADC IN Input Leakage
AGND to AV
CC
b
0 3V
0 1
3
m
A (max)
C
ADC
ADC IN Input Capacitance
25
pF
MUX On-Channel Leakage
AGND to AV
CC
b
0 3V
0 1
3
m
A (max)
MUX Off-Channel Leakage
AGND to AV
CC
b
0 3V
0 1
3
m
A (max)
C
MUX
Multiplexer Input Cap
7
pF
MUX Off Isolation
f
IN
e
100 kHz
92
dB
2
Dynamic Characteristics
(Note 10) The following specifications apply for DV
CC
e
AV
CC
e
a
5V
V
REFa(SENSE)
e a
4 096V V
REFb(SENSE)
e
AGND R
S
e
25X f
IN
e
100 kHz 0 dB from fullscale and f
s
e
1 MHz unless
otherwise specified Boldface limits apply for T
A
e
T
J
from T
MIN
to T
MAX
all other limits T
A
e
T
J
e a
25 C
Symbol
Parameter
Conditions
Typ
Limit
Units
(Note 7)
(Note 8)
(Limit)
SINAD
Signal-to-Noise Plus
T
MIN
to T
MAX
71
68 0
dB (min)
Distortion Ratio
SNR
Signal-to-Noise Ratio
T
MIN
to T
MAX
72
69 5
dB (min)
(Note 11)
THD
Total Harmonic Distortion
T
A
e a
25 C
b
82
b
74
dBc (max)
(Note 12)
T
MIN
to T
MAX
b
70
dBc (max)
ENOB
Effective Number of Bits
T
MIN
to T
MAX
11 5
11 0
Bits (min)
(Note 13)
IMD
Intermodulation Distortion
f
IN
e
102 3 kHz 102 7 kHz
b
80
dBc
DC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e
a
5V
V
REFa(SENSE)
e a
4 096V V
REFb(SENSE)
e
AGND and f
s
e
1 MHz unless otherwise specified Boldface limits apply
for T
A
e
T
J
from T
MIN
to T
MAX
all other limits T
A
e
T
J
e a
25 C
Symbol
Parameter
Conditions
Typ
Limit
Units
(Note 7)
(Note 8)
(Limit)
V
IN(1)
Logical ``1'' Input Voltage
DV
CC
e
AV
CC
e a
5 5V
2 0
V (min)
V
IN(0)
Logical ``0'' Input Voltage
DV
CC
e
AV
CC
e a
4 5V
0 8
V (max)
I
IN(1)
Logical ``1'' Input Current
0 1
1 0
m
A (max)
I
IN(0)
Logical ``0'' Input Current
0 1
1 0
m
A (max)
V
OUT(1)
Logical ``1'' Output Voltage
DV
CC
e
AV
CC
e a
4 5V
I
OUT
e b
360 mA
2 4
V (min)
I
OUT
e b
100 mA
4 25
V (min)
V
OUT(0)
Logical ``0'' Output Voltage
DV
CC
e
AV
CC
e a
4 5V
0 4
V (max)
I
OUT
e
1 6 mA
I
OUT
TRI-STATE Output
Pins DB0 DB11
0 1
3
m
A (max)
Leakage Current
C
OUT
TRI-STATE Output Capacitance
Pins DB0 DB11
5
pF
C
IN
Digital Input Capacitance
4
pF
DI
CC
DV
CC
Supply Current
2
3
mA (max)
AI
CC
AV
CC
Supply Current
10
12
mA (max)
I
STANDBY
Standby Current (DI
CC
a
AI
CC
)
PD
e
0V
20
m
A
3
AC Electrical Characteristics
The following specifications apply for DV
CC
e
AV
CC
e
a
5V
V
REFa(SENSE)
e a
4 096V V
REFb(SENSE)
e
AGND and f
s
e
1 MHz unless otherwise specified Boldface limits apply
for T
A
e
T
J
from T
MIN
to T
MAX
all other limits T
A
e
T
J
e a
25 C
Symbol
Parameter
Conditions
Typ
Limit
Units
(Note 7)
(Note 8)
(Limits)
f
s
Maximum Sampling Rate
1
MHz (min)
(1 t
THROUGHPUT
)
t
CONV
Conversion Time
740
600
ns (min)
(S H Low to EOC High)
980
ns (max)
t
AD
Aperture Delay
20
ns
(S H Low to Input Voltage Held)
t
S H
S H Pulse Width
5
ns (min)
550
ns (max)
t
EOC
S H Low to EOC Low
95
60
ns (min)
125
ns (max)
t
ACC
Access Time
C
L
e
100 pF
10
20
ns (max)
(RD Low or OE High to Data Valid)
t
1H
t
0H
TRI-STATE Control
R
L
e
1k C
L
e
10 pF
25
40
ns (max)
(RD High or OE Low to Databus TRI-STATE)
t
INTH
Delay from RD Low to INT High
C
L
e
100 pF
35
60
ns (max)
t
INTL
Delay from EOC High to INT Low
C
L
e
100 pF
b
25
b
35
ns (min)
b
10
ns (max)
t
UPDATE
EOC High to New Data Valid
5
15
ns (max)
t
MS
Multiplexer Address Setup Time
50
ns (min)
(MUX Address Valid to EOC Low)
t
MH
Multiplexer Address Hold Time
50
ns (min)
(EOC Low to MUX Address Invalid)
t
CSS
CS Setup Time
20
ns (min)
(CS Low to RD Low S H Low or OE High)
t
CSH
CS Hold Time
20
ns (min)
(CS High after RD High S H High or OE Low)
t
WU
Wake-Up Time
1
m
s
(PD High to First S H Low)
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional These ratings do not guarantee specific performance limits however For guaranteed specifications and test conditions see the Electrical Characteris-
tics The guaranteed specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under
the listed test conditions
Note 2
All voltages are measured with respect to GND (GND
e
AGND
e
DGND) unless otherwise specified
Note 3
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
k
GND or V
IN
l
V
CC
) the absolute value of current at that pin should be
limited to 25 mA or less The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two
Note 4
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
i
JA
and the ambient temperature T
A
The maximum
allowable power dissipation at any temperature is P
D
e
(T
JMAX
b
T
A
) i
JA
or the number given in the Absolute Maximum Ratings whichever is lower i
JA
for the V
(PLCC) package is 55 C W i
JA
for the VF (PQFP) package is 62 C W In most cases the maximum derated power dissipation will be reached only during fault
conditions
4
Note 5
Human body model 100 pF discharged through a 1 5 kX resistor Machine model ESD rating is 200V
Note 6
See AN-450 ``Surface Mounting Methods and Their Effect on Product Reliability'' or the section titled ``Surface Mount'' found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices
Note 7
Typicals are at
a
25 C and represent most likely parametric norm
Note 8
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level)
Note 9
Integral Linearity Error is the maximum deviation from a straight line between the
measured offset and full scale endpoints
Note 10
Dynamic testing of the ADC12062 is done using the ADC IN input The input multiplexer adds harmonic distortion at high frequencies See the graph in the
Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer
Note 11
The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level Harmonics of the input signal are not included in its calculation
Note 12
The contributions from the first nine harmonics are used in the calculation of the THD
Note 13
Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB
e
(SINAD
b
1 76) 6 02
Note 14
The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low This prohibits production testing of the standby
current Some parts may exhibit significantly higher standby currents than the 20 mA typical
Note 15
Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage
TRI-STATE Test Circuit and Waveforms
TL H 11490 2
TL H 11490 3
TL H 11490 4
TL H 11490 5
5