ADC12181
12-Bit, 10 MHz Self-Calibrating, Pipelined A/D Converter
with Internal Sample & Hold
General Description
The ADC12181 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 10 megasamples per second (MSPS). The
ADC12181 utilizes an innovative pipeline architecture to
minimize die size and power consumption. Self-calibration
and error correction maintain accuracy and performance
over temperature.
The ADC12181 converter operates on a 5V power supply
and can digitize analog input signals in the range of 0 to 2V.
A single convert clock controls the conversion operation. All
digital I/O is TTL compatible.
The ADC12181 is designed to minimize external compo-
nents necessary for the analog input interface. An internal
sample-and-hold circuit samples the analog input and an
internal amplifier buffers the reference voltage input.
The ADC12181 is available in the 32-lead TQFP package
and is designed to operate over the extended commercial
temperature range of -40C to +85C.
Features
n
Single 5V power supply
n
Simple analog input interface
n
Internal Sample-and-hold
n
Internal Reference buffer amplifier
n
Low power consumption
Key Specifications
n
Resolution
12 Bits
n
Conversion Rate
10 Msps (min)
n
DNL
0.4 LSB (typ)
n
SNR
65 dB (typ)
n
ENOB
10.4 Bits (typ)
n
Analog Input Range
2 Vpp (min)
n
Supply Voltage
+5V
5%
n
Power Consumption, 10 MHz
235 mW (typ)
Applications
n
Image processing front end
n
PC-based data acquisition
n
Scanners
n
Fax machines
n
Waveform digitizer
Connection Diagram
10103901
Ordering Information
Industrial
(-40C
TA +85C)
Package
ADC12181CIVT
32 pin TQFP
November 2002
ADC12181
12-Bit,
10
MHz
Self-Calibrating,
Pipelined
A/D
Converter
with
Internal
Sample
&
Hold
2002 National Semiconductor Corporation
DS101039
www.national.com
Ordering Information
(Continued)
Industrial
(-40C
TA +85C)
Package
ADC12181 EVAL
Evaluation Board
Simplified Block Diagram
10103902
ADC12181
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2
Pin Descriptions and Equivalent Circuits #2
No.
Symbol
Equivalent Circuit
Description
2
V
IN
Analog signal input. With a 2.0V reference voltage,
input signal voltages in the range of 0 to 2.0 Volts
will be converted. See section 1.2.
1
V
REF
Reference voltage input. This pin should be driven
from an accurate, stable reference source in the
range of 1.8 to 2.2V and bypassed to a low-noise
analog ground with a monolithic ceramic capacitor,
nominally 0.01F. See section 1.1.
32
V
RP
Positive reference bypass pin. Bypass with a 0.1F
capacitor. Do not connect anything else to this pin.
See section 3.1
31
V
RM
Reference midpoint bypass pin. Bypass with a 0.1F
capacitor. Do not connect anything else to this pin.
See section 3.1
30
V
RN
Negative reverence bypass pin. Bypass with a 0.1F
capacitor. Do not connect anything else to this pin.
See section 3.1
10
CLOCK
Sample Clock input, TTL compatible. Maximum
amplitude should not exceed 3V.
8
CAL
Calibration request, active High. Calibration cycle
starts when CAL returns to logic low. CAL is ignored
during power-down mode. See section 2.2.
7
PD
Power-down, active High, ignored during calibration
cycle. See paragraph 2.4
11
OE
Output enable control, active low. When this pin is
high the data outputs are in Tri-state
(high-impedance) mode.
28
OR
Over range indicator. This pin is at a logic High for
V
IN
<
0 or for V
IN
>
V
REF
.
29
READY
Device ready indicator, active High. This pin is at a
logic Low during a calibration cycle and while the
device is in the power down mode.
ADC12181
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3
Pin Descriptions and Equivalent Circuits #2
(Continued)
No.
Symbol
Equivalent Circuit
Description
14-19,
22-27
D0 - D11
Digital output word, CMOS compatible. D0 (pin 14) is
LSB, D11 (pin 27) is MSB. Load with no more than
50pF.
3
V
IN com
Analog input common. Connect to a quiet point in
analog ground near the driving device. See section
1.2.
5
V
A
Positive analog supply pin. Connect to a clean, quiet
voltage source of +5V. V
A
and V
D
should have a
common supply and be separately bypassed with a
5F to 10F capacitor and a 0.1F chip capacitor.
4, 6
AGND
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC12181 package. See section 5.0.
13
V
D
Positive analog supply pin. Connect to a clean, quiet
voltage source of +5V. V
A
and V
D
should have a
common supply and be separately bypassed with a
5F to 10F capacitor and a 0.1 F chip capacitor.
9, 12
DGND
The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC12181 package. See section 5.0
21
V
D
I/O
The digital output driver supply pin. This pin can be
operated from a supply voltage of 3V to 5V, but the
voltage on this pin should never exceed the V
D
supply pin voltage.
20
DGND I/O
The ground return for the output drivers. This pin
should be returned to a point in the digital ground
that is removed from the other ground pins of the
ADC12181.
ADC12181
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4
Absolute Maximum Ratings
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
6.5V
Voltage on Any Output
-0.3V to V
+
+0.3V
Input Current at Any Pin (Note 3)
25mA
Package Input Current (Note 3)
50mA
Package Dissipation
See (Note 4)
ESD Susceptibility
Human Body Model
1500V
Machine Model
200V
Soldering Temp., Infrared, 10
sec.(Note 6)
300C
Storage Temp.
-65C to +150C
Maximum Junction Temp.
150C
Operating Ratings
Operating Temp. Range
-40C
T
A
+85C
Supply Voltage
+4.75V to +5.25V
V
D
I/O
+2.7V to V
D
V
REF
Input
1.8V to 2.2V
CLOCK, CAL, PD, OE
-0.05V to V
D
+ 0.05V
|AGND -DGND|
100mV
Converter Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
A
= V
D
= V
D
I/O = +5V, PD = +5V, V
REF
= +2.0V,
f
CLK
= 10MHz, C
L
= 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for T
A
= T
J
to T
MIN
to T
MAX
: all other
limits T
A
= T
J
= 25C (Notes 7, 8) and (Note 9)
Symbol
Parameter
Conditions
Typical
(Note
10)
Limits
(Note
11)
Units
(Limits)
Static Converter Characteristics
Resolution with No Missing Codes
12
Bits(min)
INL
Integral Non Linearity
0.7
2.1
LSB( max)
DNL
Differential Non Linearity
0.4
0.8
LSB( max)
Full-Scale Error
0.05
0.24
%FS(max)
Zero Error
0.15
0.24
%FS(max)
Dynamic Converter Characteristics
BW
Full Power Bandwidth
100
MHz
SNR
Signal-to-Noise Ratio
f
in
= 5 MHz, V
IN
= 2.0V
P-P
65
62
dB
SINAD
Signal-to-Noise & Distortion
f
in
= 5 MHz, V
IN
= 2.0V
P-P
64.5
61.5
dB
ENOB
Effective Number of Bits
f
in
= 5 MHz, V
IN
= 2.0V
P-P
10.4
10
Bits
THD
Total Hamonic Distortion
f
in
= 5 MHz, V
IN
= 2.0V
P-P
74
dB
SFDR
Spurious Free Dynamic Range
f
in
= 5 MHz, V
IN
= 2.0V
P-P
73
dB
Reference and Analog Input Characteristics
V
IN
Input Voltage Range
V
REF
= 2.0V
0
V
REF
V(min)
V(max)
C
IN
V
IN
Input Capacitance
V
IN
= 1.0Vdc +
0.7Vrms
(CLK LOW)
10
pF
(CLK HIGH)
15
pF
V
REF
Reference Voltage (Note 14)
2.00
1.8
V(min)
2.2
V(max)
Reference Input Leakage Current
10
A
Reference Input Resistance
1
M
(min)
ADC12181
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