ADC12281
12-Bit, 20 MSPS Single-Ended Input, Pipelined A/D
Converter
General Description
The ADC12281 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 20 megasamples per second (MSPS). It
utilizes a pipeline architecture to minimize die size and
power dissipation. Self-calibration and error correction main-
tain accuracy and performance over temperature.
The ADC12281 operates on a 5V power supply and can
digitize single-ended analog input signals in the range of 0V
to 2V. A single convert clock controls the conversion opera-
tion and all digital I/O is TTL compatible.
The ADC12881 is designed to minimize external compo-
nents necessary for the analog input interface. An internal
sample-and-hold circuit samples the single-ended analog
input and an internal amplifier buffers the reference voltage
input.
The Power Down feature reduces power consumption to
20 mW, typical.
The ADC12281 is available in the 32-lead TQFP package
and is designed to operate over the industrial temperature
range of -40C to +85C.
Features
n
Single 5V power supply
n
Single-ended analog input
n
Internal sample-and-hold
n
Internal reference buffer amplifier
n
Low offset and gain errors
Key Specifications
n
Resolution
12 bits
n
Conversion rate
up to 20 MSPS
n
DNL
0.35 LSB (typ)
n
SNR
65.5 dB (typ)
n
ENOB
10.5 bits (typ)
n
Analog input range
2 V
PP
(min)
n
Supply voltage
+5V
5%
n
Power consumption, 20 MHz
443 mW (typ)
Applications
n
Digital signal processing front end
n
Digital television
n
Radar
n
High speed data links
n
Waveform digitizers
n
Quadrature demodulation
Connection Diagram
10102701
32-Lead TQFP Package
Order Number ADC12281CIVT
See NS Package Number VBE32A
TRISTATE&
is a registered trademark of National Semiconductor Corporation.
November 2002
ADC12281
12-Bit,
20
MSPS
Single-Ended
Input,
Pipelined
A/D
Converter
2002 National Semiconductor Corporation
DS101027
www.national.com
Ordering Information
Industrial (-40C
T
A
+85C)
Package
ADC12281CIVT
32-Pin TQFP
Simplified Block Diagram
10102702
Pin Descriptions and Equivalent Circuits
Pin
Symbol
Equivalent Circuit
Description
2
V
IN
Single-ended analog signal input. With a 2.0V
reference voltage, input signal voltages in the range
of 0V to 2.0V will be converted. See Section 1.2.
1
V
REF
Reference voltage input. This pin should be driven
from an accurate, stable reference source in the
range of 1.8V to 2.2V and bypassed to a low-noise
ground with a monolithic ceramic capacitor,
nominally 0.01 F. See Section 1.1.
ADC12281
www.national.com
2
Pin Descriptions and Equivalent Circuits
(Continued)
Pin
Symbol
Equivalent Circuit
Description
32
V
RP
Positive reference bypass pin. Bypass with a 0.1 F
capacitor. Do not connect anything else to this pin.
See Section 3.1.
31
V
RM
Reference midpoint bypass pin. Bypass with a
0.1 F capacitor. Do not connect anything else to
this pin. See Section 3.1.
30
V
RN
Negative reference bypass pin. Bypass with a
0.1 F capacitor. Do not connect anything else to
this pin. See Section 3.1.
10
CLOCK
Sample clock input, TTL compatible. Amplitude
should not exceed 3 V
P-P
.
8
CAL
Calibration request, active High. Calibration cycle
starts when CAL returns to logic low. CAL is
ignored during power-down mode. See Section 2.2.
7
PD
Power-down, active High, ignored during calibration
cycle. See paragraph 2.4.
11
OE
Output enable control, active low. When this pin is
high the data outputs are in TRI-STATE
(high-impedance) mode.
28
OR
Over-range indicator. This pin is at a logic High, for
V
IN
<
0 or for V
IN
>
V
REF
.
29
READY
Device ready indicator, active High. This pin will be
at a logic Low during a calibration cycle and while
the device is in the power down mode.
1419,
2227
D0D11
Digital output word, CMOS compatible. D0 (pin 19)
is LSB, D11 (pin 36) is MSB. Load with no more
than 25 pF.
ADC12281
www.national.com
3
Pin Descriptions and Equivalent Circuits
(Continued)
Pin
Symbol
Equivalent Circuit
Description
3
V
IN COM
Analog input common. Connect to a quiet point in
analog ground near the driving device. See Section
1.2.
5
V
A
Positive analog supply pin. Connect to a clean,
quiet voltage source of +5V. V
A
and V
D
should
have a common supply and be separately
bypassed with a 5 F to 10 F capacitor and a
0.1 F chip capacitor.
4, 6
AGND
The ground return for the analog supply, AGND and
DGND should be connected together close to the
ADC12281 package. See Section 5.0.
13
V
D
Positive digital supply pin. Connect to a clean, quiet
voltage source of +5V. V
A
and V
D
should have a
common supply and be separately bypassed with a
5 F to 10 F capacitor and a 0.1 F chip
capacitor.
9, 12
DGND
The ground return for the digital supply. AGND and
DGND should be connected together close to the
ADC12281 package. See Section 5.0.
21
V
D
I/O
The digital output driver supply pins. This pin can
be operated from a supply voltage of 3V to 5V, but
the voltage on this pin should never exceed the V
D
supply pin voltage. See Section 3.4.
20
DGND I/O
The ground return for the digital output drivers. This
pin should be returned to a point in the digital
ground that is removed from the other ground pins
of the ADC12281.
ADC12281
www.national.com
4
Absolute Maximum Ratings
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltages (V
A
, V
D
, V
D
I/O)
6.5V
|V
A
V
D
|
100 mV
V
D
I/OV
A
, V
D
I/OV
D
300 mV
Voltage on Any Input or Output Pin
-0.3V to V
A
+0.3V
Input Current at Any Pin (Note 3)
25 mA
Package Input Current (Note 3)
50 mA
Power Dissipation at T
A
= 25C
See (Note 4)
ESD Susceptibility
Human Body Model (Note 5)
2500V
Machine Model (Note 5)
250V
Soldering Temperature, Infrared,
(10 sec.) (Note 6)
300C
Storage Temperature
-65C to +150C
Operating Ratings
(Notes 1, 2)
Operating Temperature Range
-40C
T
A
+85C
Supply Voltage (V
A
, V
D
)
+4.75V to +5.25V
Output Driver Supply Voltage (V
D
I/O)
+2.7V to V
D
V
REF
Input
1.8V to 2.2V
CLOCK, CAL, PD, OE
-0.05V to V
D
+0.05V
Ground Difference |AGNDDGND|
100 mV
Converter Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
A
= V
D
= V
D
I/O = +5V, PD = +5V, V
REF
= +2.0V,
f
CLK
= 20 MHz, 3 V
P-P
at 50% duty cycle, C
L
= 25 pF/pin. After Auto-Cal. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C (Notes 7, 8, 9).
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12
Bits (min)
INL
Integral Non-Linearity
1.0
2.5
LSB (max)
DNL
Differential Non-Linearity
0.35
0.9
LSB (max)
Full-Scale Error
+3
10
LSB (max)
Zero Error
+7
17
LSB (max)
DYNAMIC CONVERTER CHARACTERISTICS
BW
Full Power Bandwidth
100
MHz
SNR
Signal-to-Noise Ratio
f
IN
= 4.43 MHz, V
IN
= 2.0 V
P-P
65.5
62.5
dB (min)
SINAD
Signal-to-Noise and Distortion
f
IN
= 4.43 MHz, V
IN
= 2.0 V
P-P
65
62
dB (min)
ENOB
Effective Number of Bits
f
IN
= 4.43 MHz, V
IN
= 2.0 V
P-P
10.5
10
Bits (min)
THD
Total Harmonic Distortion
f
IN
= 4.43 MHz, V
IN
= 2.0 V
P-P
-76
dB
SFDR
Spurious Free Dynamic Range
f
IN
= 4.43 MHz, V
IN
= 2.0 V
P-P
75
dB
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
IN
Input Voltage Range
V
REF
V (max)
C
IN
V
IN
Input Capacitance
(CLK LOW)
10
pF
(CLK HIGH)
15
pF
V
REF
Reference Voltage (Note 14)
2.00
1.8
V (min)
2.2
V (max)
Reference Input Leakage Current
10
A
Reference Input Resistance
1
M
DC and Logic Electrical Characteristics
The following specifications apply for AGND = DGND = DGND I/O = 0V, V
A
= V
D
= V
D
I/O = +5V, PD = +5V, V
REF
= +2.0V,
f
CLK
= 20 MHz, 3 V
P-P
at 50% duty cycle, C
L
= 25 pF/pin. After Auto-Cal. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C (Notes 7, 8, 9).
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
CLOCK, CAL, PD, OE DIGITAL INPUT CHARACTERISTICS
V
IH
Logical "1" Input Voltage
V
D
= 5.25V
2.0
V (min)
ADC12281
www.national.com
5
PDF 
ZIP