ADC12L066
12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with
Internal Sample-and-Hold
General Description
The ADC12L066 is a monolithic CMOS analog-to-digital con-
verter capable of converting analog input signals into 12-bit
digital words at 66 Megasamples per second (MSPS), mini-
mum, with typical operation possible up to 80 MSPS. This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize die size and power consumption while providing
excellent dynamic performance. A unique sample-and-hold
stage yields a full-power bandwidth of 450 MHz. Operating
on a single 3.3V power supply, this device consumes just
357 mW at 66 MSPS, including the reference current. The
Power Down feature reduces power consumption to just
50 mW.
The differential inputs provide a full scale input swing equal
to
V
REF
with the possibility of a single-ended input. Full use
of the differential input is recommended for optimum perfor-
mance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differ-
ential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of -40C to
+85C. An evaluation board is available to facilitate the
evaluation process.
Features
n
Single supply operation
n
Low power consumption
n
Power down mode
n
On-chip reference buffer
Key Specifications
n
Resolution
12 Bits
n
Conversion Rate
66 MSPS
n
Full Power Bandwidth
450 MHz
n
DNL
0.4 LSB (typ)
n
SNR (f
IN
= 10 MHz)
66 dB (typ)
n
SFDR (f
IN
= 10 MHz)
80 dB (typ)
n
Data Latency
6 Clock Cycles
n
Supply Voltage
+3.3V
300 mV
n
Power Consumption, 66 MHz
357 mW (typ)
Applications
n
Ultrasound and Imaging
n
Instrumentation
n
Cellular Base Stations/Communications Receivers
n
Sonar/Radar
n
xDSL
n
Wireless Local Loops
n
Data Acquisition Systems
n
DSP Front Ends
Connection Diagram
20032801
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
December 2003
ADC12L066
12-Bit,
66
MSPS,
450
MHz
Bandwidth
A/D
Converter
with
Internal
Sample-and-Hold
2003 National Semiconductor Corporation
DS200328
www.national.com
Ordering Information
Industrial (-40C
T
A
+85C)
Package
ADC12L066CIVY
32 Pin LQFP
ADC12L066CIVYX
32 Pin LQFP Tape and Reel
ADC12L066EVAL
Evaluation Board
Block Diagram
20032802
ADC12L066
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Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
2
V
IN+
Analog signal Input pins. With a 1.0V reference voltage the
differential input signal level is 2.0 V
P-P
. The V
IN
- pin may be
connected to V
CM
for single-ended operation, but a differential
input signal is required for best performance.
3
V
IN-
1
V
REF
Reference input. This pin should be bypassed to AGND with
a 0.1 F monolithic capacitor. V
REF
is 1.0V nominal and
should be between 0.8V and 1.5V.
31
V
RP
These pins are high impedance reference bypass pins.
Connect a 0.1 F capacitor from each of these pins to AGND.
DO NOT LOAD these pins.
32
V
RM
30
V
RN
DIGITAL I/O
10
CLK
Digital clock input. The range of frequencies for this input is
1 MHz to 80 MHz (typical) with guaranteed performance at 66
MHz. The input is sampled on the rising edge of this input.
11
OE
OE is the output enable pin that, when low, enables the
TRI-STATE
data output pins. When this pin is high, the
outputs are in a high impedance state.
8
PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
ADC12L066
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Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
1419,
2227
D0D11
Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word.
ANALOG POWER
5, 6, 29
V
A
Positive analog supply pins. These pins should be connected
to a quiet +3.3V source and bypassed to AGND with 0.1 F
monolithic capacitors located within 1 cm of these power pins,
and with a 10 F capacitor.
4, 7, 28
AGND
The ground return for the analog supply.
DIGITAL POWER
13
V
D
Positive digital supply pin. This pin should be connected to
the same quiet +3.3V source as is V
A
and bypassed to
DGND with a 0.1 F monolithic capacitor in parallel with a 10
F capacitor, both located within 1 cm of the power pin.
9, 12
DGND
The ground return for the digital supply.
21
V
DR
Positive digital supply pin for the ADC12L066's output drivers.
This pin should be connected to a voltage source of +1.8V to
V
D
and bypassed to DR GND with a 0.1 F monolithic
capacitor. If the supply for this pin is different from the supply
used for V
A
and V
D
, it should also be bypassed with a 10 F
tantalum capacitor. The voltage at this pin should never
exceed the voltage on V
D
by more than 300 mV. All bypass
capacitors should be located within 1 cm of the supply pin.
20
DR GND
The ground return for the digital supply for the ADC12L066's
output drivers. This pin should be connected to the system
digital ground, but not be connected in close proximity to the
ADC12L066's DGND or AGND pins. See Section 5.0 (Layout
and Grounding) for more details.
ADC12L066
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4
Absolute Maximum Ratings
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
A
, V
D
, V
DR
4.2V
|V
A
V
D
|
100 mV
Voltage on Any Pin
-0.3V to (V
A
or V
D
+0.3V)
Input Current at Any Pin (Note 3)
25 mA
Package Input Current (Note 3)
50 mA
Package Dissipation at T
A
= 25C
See (Note 4)
ESD Susceptibility
Human Body Model (Note 5)
2500V
Machine Model (Note 5)
250V
Soldering Temperature,
Infrared, 10 sec. (Note 6)
235C
Storage Temperature
-65C to +150C
Operating Ratings
(Notes 1, 2)
Operating Temperature
-40C
T
A
+85C
Supply Voltage (V
A
, V
D
)
+3.0V to +3.60V
Output Driver Supply (V
DR
)
+1.8V to V
D
V
REF
Input
0.8V to 1.5V
CLK, PD, OE
-0.05V to (V
D
+ 0.05V)
V
IN
Input
-0V to (V
A
- 0.5V)
V
CM
0.5V to (V
A
-1.5V)
|AGNDDGND|
100 mV
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
A
= V
D
= +3.3V,
V
DR
= +2.5V, PD = 0V, V
REF
= +1.0V, V
CM
= 1.0V, f
CLK
= 66 MHz, t
r
= t
f
= 2 ns, C
L
= 15 pF/pin. Boldface limits apply for T
J
= T
MIN
to T
MAX
: all other limits T
J
= 25C (Notes 7, 8, 9, 10)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
12
Bits
INL
Integral Non Linearity (Note 11)
1.2
+2.7
LSB (max)
-3
LSB (min)
DNL
Differential Non Linearity
0.4
+1
LSB (max)
-0.95
LSB (min)
GE
Gain Error
Positive Error
-0.15
3
%FS (max)
Negative Error
+0.4
+4
%FS (max)
-5
%FS (min)
Offset Error (V
IN
+ = V
IN
-)
+0.2
1.3
%FS (max)
Under Range Output Code
0
0
Over Range Output Code
4095
4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
Common Mode Input Voltage
1.0
0.5
V (min)
1.5
V (max)
C
IN
V
IN
Input Capacitance (each pin to
GND)
V
IN
+ 1.0 Vdc
+ 1 V
P-P
(CLK LOW)
8
pF
(CLK HIGH)
7
pF
V
REF
Reference Voltage (Note 13)
1.0
0.8
V (min)
1.5
V (max)
Reference Input Resistance
100
M
(min)
ADC12L066
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