TL F 5986
CD40160BMBC
Decade
Counter
with
Asynchronous
CD40162BMBC
Synchronous
Clear
CD40161BMBC
Binary
Counter
with
Asynchronous
CD40163BMBC
Synchronous
Clear
March 1988
CD40160BM CD40160BC
Decade Counter with Asynchronous Clear
CD40161BM CD40161BC
Binary Counter with Asynchronous Clear
CD40162BM CD40162BC
Decade Counter with Synchronous Clear
CD40163BM CD40163BC
Binary Counter with Synchronous Clear
General Description
These (synchronous presettable up) counters are monolith-
ic complementary MOS (CMOS) integrated circuits con-
structed with N- and P-channel enhancement mode transis-
tors They feature an internal carry look-ahead for fast
counting schemes and for cascading packages without ad-
ditional gating
A low level at the load input disables counting and causes
the outputs to agree with the data input after the next posi-
tive clock edge The clear function for the CD40162B and
CD40163B is synchronous and a low level at the clear input
sets all four outputs low after the next positive clock edge
The clear function for the CD40160B and CD40161B is
asynchronous and a low level at the clear input sets all four
outputs low regardless of the state of the clock
Counting is enabled when both count enable inputs are
high Input T is fed forward to also enable the carry out The
carry output is a positive pulse with a duration approximately
equal to the positive portion of Q
A
and can be used to en-
able successive cascaded stages Logic transitions at the
enable P or T inputs can occur when the clock is high or
low
Features
Y
Wide supply voltage range
3 0V to 15V
Y
High noise immunity
0 45 V
DD
(typ )
Y
Low power TTL
fan out of 2 driving 74L
compatibility
or 1 driving 74LS
Y
Internal look-ahead for fast counting schemes
Y
Carry output for N-bit cascading
Y
Load control line
Y
Synchronously programmable
Y
Equivalent
to
MC14160B
MC14161B
MC14162B
MC14163B
Y
Equivalent to MM74C160
MM74C161
MM74C162
MM74C163
Connection Diagram
Dual-In-Line Package
TL F 5986 1
Top View
Order Number CD40160B CD40161B
CD40162B or CD40163B
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
DC Supply Voltage (V
DD
)
b
0 5 to
a
18 V
DC
Input Voltage (V
IN
)
b
0 5 to V
DD
a
0 5 V
DC
Storage Temperature Range (T
S
)
b
65 C to
a
150 C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature
(Soldering 10 seconds)
260 C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
3V to 15 V
DC
Input Voltage (V
IN
)
0V to V
DD
V
DC
Operating Temperature Range (T
A
)
CD40XXXBM
b
55 C to
a
125 C
CD40XXXBC
b
40 C to
a
85 C
DC Electrical Characteristics
CD40160BM CD40161BM CD40162BM CD40163BM (Note 2)
Limits
Symbol
Parameter
Conditions
b
55 C
a
25 C
a
125 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
e
5V
5
5
150
m
A
Current
V
DD
e
10V
10
10
300
m
A
V
DD
e
15V
20
20
600
m
A
V
OL
Low Level Output
l
I
O
l
k
1 mA
Voltage
V
DD
e
5V
0 05
0 05
0 05
V
V
DD
e
10V
0 05
0 05
0 05
V
V
DD
e
15V
0 05
0 05
0 05
V
V
OH
High Level Output
l
I
O
l
k
1 mA
Voltage
V
DD
e
5V
4 95
4 95
5
4 95
V
V
DD
e
10V
9 95
9 95
10
9 95
V
V
DD
e
15V
14 95
14 95
15
14 95
V
V
IL
Low Level Input
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
1 5
1 5
V
Voltage
V
DD
e
10V V
O
e
1V or 9V
3 0
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
4 0
4 0
4 0
V
V
IH
High Level Input
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
3 5
V
Voltage
V
DD
e
10V V
O
e
1V or 9V
7 0
7 0
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
11 0
11 0
11 0
V
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
0 64
0 51
0 88
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
0 5V
1 6
1 3
2 25
0 9
mA
V
DD
e
15V V
O
e
1 5V
4 2
3 4
8 8
2 4
mA
I
OH
High Level Output
V
DD
e
5V V
O
e
4 6V
b
0 64
b
0 51
b
0 88
b
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
9 5V
b
1 6
b
1 3
b
2 25
b
0 9
mA
V
DD
e
15V V
O
e
13 5V
b
4 2
b
3 4
b
8 8
b
2 4
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 10
b
10
b
5
b
0 10
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 10
10
b
5
0 10
1 0
m
A
DC Electrical Characteristics
CD40160BC CD40161BC CD40162BC CD40163BC (Note 2)
Limits
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device Current
V
DD
e
5V
20
20
150
m
A
V
DD
e
10V
40
40
300
m
A
V
DD
e
15V
80
80
600
m
A
V
OL
Low Level Output
l
I
O
l
k
1 mA
Voltage
V
DD
e
5V
0 05
0 05
0 05
V
V
DD
e
10V
0 05
0 05
0 05
V
V
DD
e
15V
0 05
0 05
0 05
V
V
OH
High Level Output
l
I
O
l
k
1 mA
Voltage
V
DD
e
5V
4 95
4 95
5
4 95
V
V
DD
e
10V
9 95
9 95
10
0 95
V
V
DD
e
15V
14 95
14 95
15
14 95
V
V
IL
Low Level Input
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
1 5
1 5
V
Voltage
V
DD
e
10V V
O
e
1V or 9V
3 0
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
4 0
4 0
4 0
V
2
DC Electrical Characteristics
CD40160BC CD40161BC CD40162BC CD40163BC (Note 2) (Continued)
Limits
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
V
IH
High Level Input
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
3 5
V
Voltage
V
DD
e
10V V
O
e
1V or 9V
7 0
7 0
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
11 0
11 0
11 0
V
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
0 52
0 44
0 88
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
0 5V
1 3
1 1
2 25
0 9
mA
V
DD
e
15V V
O
e
1 5V
3 6
3 0
8 8
2 4
mA
I
OH
High Level Output
V
DD
e
5V V
O
e
4 6V
b
0 52
b
0 44
b
0 88
b
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
9 5V
b
1 3
b
1 1
b
2 25
b
0 9
mA
V
DD
e
15V V
O
e
13 5V
b
3 6
b
3 0
b
8 8
b
2 4
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 30
b
10
b
5
b
0 30
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 30
10
b
5
0 30
1 0
m
A
AC Electrical Characteristics
T
A
e
25 C C
L
e
50 pF R
L
e
200k unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHL
or t
PLH
Propagation Delay Time from
V
DD
e
5V
250
400
ns
Clock to Q
V
DD
e
10V
100
160
ns
V
DD
e
15V
80
130
ns
t
PHL
or t
PLH
Propagation Delay Time from
V
DD
e
5V
290
450
ns
Clock to Carry Out
V
DD
e
10V
120
190
ns
V
DD
e
15V
100
160
ns
t
PHL
or t
PLH
Propagation Delay Time from T
V
DD
e
5V
180
290
ns
Enable to Carry Out
V
DD
e
10V
70
130
ns
V
DD
e
15V
60
110
ns
t
PHL
Propagation Time from Clear to Q
V
DD
e
5V
190
300
ns
(CD40160B CD40161B Only)
V
DD
e
10V
80
150
ns
V
DD
e
15V
70
120
ns
t
SU
Minimum Time Prior to Clock that
V
DD
e
5V
120
ns
Data or Load must be Present
V
DD
e
10V
30
ns
V
DD
e
15V
25
ns
t
SU
Minimum Time Prior to Clock that
V
DD
e
5V
170
280
ns
Enable P or T must be Present
V
DD
e
10V
70
120
ns
V
DD
e
15V
60
100
ns
t
SU
Minimum Time Prior to Clock that
V
DD
e
5V
120
190
ns
Clear must be Present (CD40162B
V
DD
e
10V
50
80
ns
CD40163B Only)
V
DD
e
15V
40
70
ns
t
WL
or t
WH
Maximum Clock Pulse Width
V
DD
e
5V
125
250
ns
V
DD
e
10V
45
90
ns
V
DD
e
15V
35
70
ns
t
RCL
or t
FCL
Maximum Clock Rise or Fall Time
V
DD
e
5V
15
m
s
V
DD
e
10V
5 0
m
s
V
DD
e
15V
5 0
m
s
f
CL
Maximum Clock Frequency
V
DD
e
5V
2
4
MHz
V
DD
e
10V
5 5
11
MHz
V
DD
e
15V
7
14
MHz
t
THL
or t
TLH
Transition Time
All Outputs
V
DD
e
5V
100
200
ns
V
DD
e
10V
50
100
ns
V
DD
e
15V
40
80
ns
C
IN
Average Input Capacitance
Any Input
5 0
7 5
pF
C
PD
Power Dissipation Capacity
(Note 4)
95
pF
AC Parameters are guaranteed by DC correlated testing
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices
should be operated at these limits The table of ``Recommended Operating Conditions'' and ``Electrical Characteristics'' provides conditions for actual device
operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OH
and I
OL
are tested one output at a time
Note 4
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note
AN-90
3
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