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Электронный компонент: CD4512

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TL F 5993
CD4512BMCD4512BC
8-Channel
Buffered
Data
Selector
February 1988
CD4512BM CD4512BC 8-Channel Buffered Data Selector
General Description
The CD4512BM CD4512BC buffered 8-channel data selec-
tor is a complementary MOS (CMOS) circuit constructed
with N- and P-channel enhancement mode transistors This
data selector is primarily used as a digital signal multiplexer
selecting 1 of 8 inputs and routing the signal to a TRI-
STATE
output A high level at the Inhibit input forces a low
level at the output A high level at the Output Enable (OE)
input forces the output into the TRI-STATE condition Low
levels at both the Inhibit and (OE) inputs allow normal oper-
ation
Features
Y
Wide supply voltage range
3 0V to 15V
Y
High noise immunity
0 45 V
DD
(typ )
Y
TRI-STATE output
Y
Low quiescent power dissipation
0 25 mW package
(typ )
V
CC
e
5 0V
Y
Plug-in replacement for Motorola MC14512
Connection Diagram and Truth Table
Dual-In-Line Package
TL F 5993 1
Top View
Order Number CD4512B
Address Inputs
Control Inputs
Output
C
B
A
Inhibit
OE
Z
0
0
0
0
0
X0
0
0
1
0
0
X1
0
1
0
0
0
X2
0
1
1
0
0
X3
1
0
0
0
0
X4
1
0
1
0
0
X5
1
1
0
0
0
X6
1
1
1
0
0
X7
j
j
j
1
0
0
j
j
j
j
1
Hi-Z
j e
Don't care
Hi-Z
e
TRI-STATE condition
Xn
e
Data at input n
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1
2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
DD
)
b
0 5 to
a
18 V
DC
Input Voltage (V
IN
)
b
0 5 to V
DD
a
0 5 V
DC
Storage Temperature Range (T
S
)
b
65 C to
a
150 C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260 C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
3 0 to 15 V
DC
Input Voltage (V
IN
)
0 to V
DD
V
DC
Operating Temperature Range (T
A
)
CD4512BM
b
55 C to
a
125 C
CD4512BC
b
40 C to
a
85 C
DC Electrical Characteristics
CD4512BM (Note 2)
Symbol
Parameter
Conditions
b
55 C
a
25 C
a
125 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
e
5V V
IN
e
V
DD
or V
SS
5 0
0 005
5 0
150
m
A
Current
V
DD
e
10V V
IN
e
V
DD
or V
SS
10
0 010
10
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
20
0 015
20
600
m
A
V
OL
Low Level
V
DD
e
5V
0 05
0
0 05
0 05
V
Output Voltage
V
DD
e
10V
l
I
OL
l
k
1 mA
0 05
0
0 05
0 05
V
V
DD
e
15V
(
0 05
0
0 05
0 05
V
V
OH
High Level
V
DD
e
5V
4 95
4 95
5 0
4 95
V
Output Voltage
V
DD
e
10V
l
I
OH
l
k
1 mA
9 95
9 95
10 0
9 95
V
V
DD
e
15V
(
14 95
14 95
15 0
14 95
V
V
IL
Low Level
V
DD
e
5V V
O
e
0 5V
1 5
2 25
1 5
1 5
V
Input Voltage
V
DD
e
10V V
O
e
1 0V
3 0
4 50
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V
4 0
6 75
4 0
4 0
V
V
IH
High Level
V
DD
e
5V V
O
e
4 5V
3 5
3 5
2 75
3 5
V
Input Voltage
V
DD
e
10V V
O
e
9 0V
7 0
7 0
5 50
7 0
V
V
DD
e
15V V
O
e
13 5V
11 0
11 0
8 25
11 0
V
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
0 64
0 51
0 78
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
0 5V
1 6
1 3
2 0
0 9
mA
V
DD
e
15V V
O
e
1 5V
4 2
3 4
7 8
2 4
mA
I
OH
High Level Output
V
DD
e
5V V
O
e
4 6V
b
0 25
b
0 2
b
0 14
mA
Current (Note 3)
V
DD
e
10V V
O
e
9 5V
b
0 62
b
0 5
b
0 35
mA
V
DD
e
15V V
O
e
13 5V
b
1 8
b
1 5
b
1 1
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 1
b
10
b
5
b
0 1
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 1
10
b
5
0 1
1 0
m
A
I
OZ
TRI-STATE
V
DD
e
15V V
O
e
0V
g
0 1
b
10
b
5
g
0 1
g
3 0
m
A
Output Current
V
DD
e
15V V
O
e
15V
DC Electrical Characteristics
CD4512BC (Note 2)
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
e
5V V
IN
e
V
DD
or V
SS
20
0 005
20
150
m
A
Current
V
DD
e
10V V
IN
e
V
DD
or V
SS
40
0 010
40
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
80
0 015
80
600
m
A
V
OL
Low Level
V
DD
e
5V
0 05
0
0 05
0 05
V
Output Voltage
V
DD
e
10V
l
I
OL
l
k
1 mA
0 05
0
0 05
0 05
V
V
DD
e
15V
(
0 05
0
0 05
0 05
V
V
OH
High Level
V
DD
e
5V
4 95
4 95
5 0
4 95
V
Output Voltage
V
DD
e
10V
l
I
OH
l
k
1 mA
9 95
9 95
10 0
9 95
V
V
DD
e
15V
(
14 95
14 95
15 0
14 95
V
V
IL
Low Level
V
DD
e
5V V
O
e
0 5V
1 5
2 25
1 5
1 5
V
Input Voltage
V
DD
e
10V V
O
e
1 0V
3 0
4 50
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V
4 0
6 75
4 0
4 0
V
2
DC Electrical Characteristics
CD4512BC (Note 2) (Continued)
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
V
IH
High Level
V
DD
e
5V V
O
e
4 5V
3 5
3 5
2 75
3 5
V
Input Voltage
V
DD
e
10V V
O
e
9 0V
7 0
7 0
5 50
7 0
V
V
DD
e
15V V
O
e
13 5V
11 0
11 0
8 25
11 0
V
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
0 52
0 44
0 78
0 36
mA
Current
V
DD
e
10V V
O
e
0 5V
1 3
1 1
2 0
0 9
mA
(Note 3)
V
DD
e
15V V
O
e
1 5V
3 6
3 4
7 8
2 4
mA
I
OH
High Level Output
V
DD
e
5V V
O
e
4 6V
b
0 2
b
0 16
b
0 12
mA
Current
V
DD
e
10V V
O
e
9 5
b
0 5
b
0 4
b
0 3
mA
(Note 3)
V
DD
e
15V V
O
e
13 5V
b
1 4
b
1 2
b
1 0
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 3
b
10
b
5
b
0 3
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 3
10
b
5
0 3
1 0
m
A
I
OZ
TRI-STATE
V
DD
e
15V V
O
e
0V
g
1 0
g
10
b
5
g
1 0
g
7 5
m
A
Output Current
V
DD
e
15V V
O
e
15V
AC Electrical Characteristics
T
A
e
25 C t
r
e
t
f
e
20 ns C
L
e
50 pF
Symbol
Parameter
Conditions
CD4512BM
CD4512BC
Units
Min
Typ
Max
Min
Typ
Max
t
PHL
Propagation Delay
V
DD
e
5V
225
500
225
750
ns
High-to-Low Level
V
DD
e
10V
75
175
75
200
ns
V
DD
e
15V
57
130
57
150
ns
t
PLH
Propagation Delay
V
DD
e
5V
225
500
225
750
ns
Low-to-High Level
V
DD
e
10V
75
175
75
200
ns
V
DD
e
15V
57
130
57
150
ns
t
THL
t
TLH
Transition Time
V
DD
e
5V
70
200
70
200
ns
V
DD
e
10V
35
100
35
100
ns
V
DD
e
15V
25
80
25
80
ns
t
PHZ
t
PLZ
Propagation Delay into
V
DD
e
5V
50
125
50
125
ns
TRI-STATE from Logic Level
V
DD
e
10V
25
75
25
75
ns
V
DD
e
15V
19
60
19
60
ns
t
PZH
t
PZL
Propagation Delay to Logic
V
DD
e
5V
50
125
50
125
ns
Level from TRI-STATE
V
DD
e
10V
25
75
25
75
ns
V
DD
e
15V
19
60
19
60
ns
C
IN
Input Capacitance
(Note 4)
7 5
15
7 5
15
pF
C
OUT
TRI-STATE Output
(Note 4)
7 5
15
7 5
15
pF
Capacitance
C
PD
Power Dissipation Capacity
(Note 5)
150
150
pF
AC Parameters are guaranteed by DC correlated testing
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the devices
should be operated at these limits The tables of ``Recommended Operating Conditions'' and ``Electrical Characteristics'' provide conditions for actual device
operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OH
and I
OL
are tested one output at a time
Note 4
Capacitance guaranteed by periodic testing
Note 5
C
PD
determines the no load AC power of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90
3
Logic Diagram
TL F 5993 2
Typical Application
Serial Data Routing Interface
TL F 5993 3
4
AC Test Circuit and Switching Time Waveforms
TL F 5993 4
TL F 5993 5
Input Connections for t
r
t
f
t
PLH
t
PHL
Test
Inhibit
A
X0
1
PG
GND
V
DD
2
GND
PG
V
DD
3
GND
GND
PG
TRI-STATE AC Test Circuit and Switching Time Waveforms
TL F 5993 6
TL F 5993 7
Switch Positions for TRI-STATE Test
Test
S1
S2
S3
S4
t
PHZ
Open
Closed Closed
Open
t
PLZ
Closed
Open
Open
Closed
t
PZL
Closed
Open
Open
Closed
t
PZH
Open
Closed Closed
Open
5