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TL F 5994
CD4514BMCD4514BC
CD4515BMCD4515BC
4-Bit
Latched4-to-16
Line
Decoders
February 1988
CD4514BM CD4514BC CD4515BM CD4515BC
4-Bit Latched 4-to-16 Line Decoders
General Description
The CD4514B and CD4515B are 4-to-16 line decoders with
latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel en-
hancement mode transistors These circuits are primarily
used in decoding applications where low power dissipation
and or high noise immunity is required
The CD4514B (output active high option) presents a logical
``1'' at the selected output whereas the CD4515B presents
a logical ``0'' at the selected output The input latches are
R S type flip-flops which hold the last input data presented
prior to the strobe transition from ``1'' to ``0'' This input data
is decoded and the corresponding output is activated An
output inhibit line is also available
Features
Y
Wide supply voltage range
3 0V to 15V
Y
High noise immunity
0 45 V
DD
(typ )
Y
Low power TTL
fan out of 2
compatibility
driving 74L
Y
Low quiescent power dissipation
0 025 mW package
5 0 V
DC
Y
Single supply operation
Y
Input impedance
e
10
12
X
typically
Y
Plug-in replacement for MC14514 MC14515
Logic and Connection Diagrams
TL F 5994 1
Dual-In-Line Package
TL F 5994 2
Top View
Order Number CD4514B or CD4515B
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Notes 1 and 2)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
DC Supply Voltage (V
DD
)
b
0 5V to
a
18V
Input Voltage (V
IN
)
b
0 5V to V
DD
a
0 5V
Storage Temperature Range (T
S
)
b
65 C to
a
150 C
Power Dissipation (P
D
)
Dual-In-Line
700 mW
Small Outline
500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds)
260 C
Recommended Operating
Conditions
(Note 2)
DC Supply Voltage (V
DD
)
3V to 15V
Input Voltage (V
IN
)
0V to V
DD
Operating Temperature Range (T
A
)
CD4514BM CD4515BM
b
55 C to
a
125 C
CD4514BC CD4515BC
b
40 C to
a
85 C
DC Electrical Characteristics
CD4514BM CD4515BM (Note 2)
Symbol
Parameter
Conditions
b
55 C
a
25 C
a
125 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
e
5V V
IN
e
V
DD
or V
SS
5
0 005
5
150
m
A
Current
V
DD
e
10V V
IN
e
V
DD
or V
SS
10
0 010
10
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
20
0 015
20
600
m
A
V
OL
Low Level
V
IH
e
V
DD
l
I
O
l
k
1 mA
Output Voltage
V
DD
e
5V V
IL
e
0V
0 05
0
0 05
0 05
V
V
DD
e
10V
0 05
0
0 05
0 05
V
V
DD
e
15V
0 05
0
0 05
0 05
V
V
OH
High Level
V
IH
e
V
DD
l
I
O
l
k
1 mA
Output Voltage
V
DD
e
5V V
IL
e
0V
4 95
4 95
5
4 95
V
V
DD
e
10V
9 95
9 95
10
9 95
V
V
DD
e
15V
14 95
14 95
15
14 95
V
V
IL
Low Level
V
O
e
0 5V or 4 5V
Input Voltage
V
DD
e
5V
l
I
O
l
k
1 mA
1 5
2 25
1 5
1 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
3 0
4 50
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
4 0
6 75
4 0
4 0
V
V
IH
High Level
V
O
e
0 5V or 4 5V
Input Voltage
V
DD
e
5V
l
I
O
l
k
1 mA
3 5
3 5
2 75
3 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
7 0
7 0
5 50
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
11 0
11 0
8 25
11 0
V
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
0 64
0 51
0 88
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
0 5V
1 6
1 3
2 25
0 90
mA
V
DD
e
15V V
O
e
1 5V
4 2
3 4
8 80
2 40
mA
I
OH
High Level Output
V
DD
e
5V V
O
e
4 6V
b
0 64
b
0 51
b
0 88
b
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
9 5V
b
1 6
b
1 3
b
2 25
b
0 90
mA
V
DD
e
15V V
O
e
13 5V
b
4 2
b
3 4
b
8 80
b
2 40
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 1
b
10
b
5
b
0 1
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 1
10
b
5
0 1
1 0
m
A
DC Electrical Characteristics
CD4514BC CD4515BC (Note 2)
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
I
DD
Quiescent Device
V
DD
e
5V V
IN
e
V
DD
or V
SS
20
0 005
20
150
m
A
Current
V
DD
e
10V V
IN
e
V
DD
or V
SS
40
0 010
40
300
m
A
V
DD
e
15V V
IN
e
V
DD
or V
SS
80
0 015
80
600
m
A
V
OL
Low Level
V
IL
e
0V V
IH
e
V
DD
Output Voltage
l
I
O
l
k
1 mA
V
DD
e
5V
0 05
0
0 05
0 05
V
V
DD
e
10V
0 05
0
0 05
0 05
V
V
DD
e
15V
0 05
0
0 05
0 05
V
V
OH
High Level
V
IL
e
0V V
IH
e
V
DD
Output Voltage
l
I
O
l
k
1 mA
V
DD
e
5V
4 95
4 95
5 0
4 95
V
V
DD
e
10V
9 95
9 95
10 0
9 95
V
V
DD
e
15V
14 95
14 95
15 0
14 95
V
2
DC Electrical Characteristics
CD4514BC CD4515BC (Note 2) (Continued)
Symbol
Parameter
Conditions
b
40 C
a
25 C
a
85 C
Units
Min
Max
Min
Typ
Max
Min
Max
V
IL
Low Level
l
I
O
l
k
1 mA
Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
1 5
2 25
1 5
1 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
3 0
4 50
3 0
3 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
4 0
6 75
4 0
4 0
V
V
IH
High Level
l
I
O
l
k
1 mA
Input Voltage
V
DD
e
5V V
O
e
0 5V or 4 5V
3 5
3 5
2 75
3 5
V
V
DD
e
10V V
O
e
1 0V or 9 0V
7 0
7 0
5 50
7 0
V
V
DD
e
15V V
O
e
1 5V or 13 5V
11 0
11 0
8 25
11 0
V
I
OL
Low Level Output
V
DD
e
5V V
O
e
0 4V
0 52
0 44
0 88
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
0 5V
1 3
1 1
2 25
0 90
mA
V
DD
e
15V V
O
e
1 5V
3 6
3 0
8 8
2 4
mA
I
OH
High Level Output
V
DD
e
5V V
O
e
4 6V
b
0 52
b
0 44
b
0 88
b
0 36
mA
Current (Note 3)
V
DD
e
10V V
O
e
9 5V
b
1 3
b
1 1
b
2 25
b
0 90
mA
V
DD
e
15V V
O
e
13 5V
b
3 6
b
3 0
b
8 8
b
2 4
mA
I
IN
Input Current
V
DD
e
15V V
IN
e
0V
b
0 3
b
10
b
5
b
0 3
b
1 0
m
A
V
DD
e
15V V
IN
e
15V
0 3
10
b
5
0 3
1 0
m
A
AC Electrical Characteristics
All types C
L
e
50 pF T
A
e
25 C t
r
e
t
f
e
20 ns unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
THL
t
TLH
Transition Times
V
DD
e
5V
100
200
ns
V
DD
e
10V
50
100
ns
V
DD
e
15V
40
80
ns
t
PLH
t
PHL
Propagation Delay Times
V
DD
e
5V
550
1100
ns
V
DD
e
10V
225
450
ns
V
DD
e
15V
150
300
ns
t
PLH
t
PHL
Inhibit Propagation
V
DD
e
5V
400
800
ns
Delay Times
V
DD
e
10V
150
300
ns
V
DD
e
15V
100
200
ns
t
SU
Setup Time
V
DD
e
5V
125
250
ns
V
DD
e
10V
50
100
ns
V
DD
e
15V
38
75
ns
t
WH
Strobe Pulse Width
V
DD
e
5V
175
350
ns
V
DD
e
10V
50
100
ns
V
DD
e
15V
38
75
ns
C
PD
Power Dissipation Capacitance
Per Package (Note 5)
150
pF
C
IN
Input Capacitance
Any Input (Note 4)
5
7 5
pF
AC Parameters are guaranteed by DC correlated testing
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The tables of ``Recommended Operating Conditions'' and ``Electrical Characteris-
tics'' provide conditions for actual device operation
Note 2
V
SS
e
0V unless otherwise specified
Note 3
I
OH
and I
OL
are tested one output at a time
Note 4
Capacitance is guaranteed by periodic testing
Note 5
C
PD
determines the no load AC power consumption of any CMOS device For complete explanation see 54C and 74C Family Characteristics application
note AN-90
3
Truth Table
Decode Truth Table (Strobe
e
1)
Data Inputs
Selected Output
Inhibit
D
C
B
A
CD4514
e
Logic ``1''
CD4515
e
Logic ``0''
0
0
0
0
0
S0
0
0
0
0
1
S1
0
0
0
1
0
S2
0
0
0
1
1
S3
0
0
1
0
0
S4
0
0
1
0
1
S5
0
0
1
1
0
S6
0
0
1
1
1
S7
0
1
0
0
0
S8
0
1
0
0
1
S9
0
1
0
1
0
S10
0
1
0
1
1
S11
0
1
1
0
0
S12
0
1
1
0
1
S13
0
1
1
1
0
S14
0
1
1
1
1
S15
1
X
X
X
X
All Outputs
e
0 CD4514
All Outputs
e
1 CD4515
X
e
Don't Care
AC Test Circuit and Switching Time Waveforms
TL F 5994 3
TL F 5994 4
FIGURE 1
4
Applications
Two CD4512 8-channel data selectors are used here with
the CD4514B 4-bit latch decoder to effect a complex data
routing system A total of 16 inputs from data registers are
selected and transferred via a TRI-STATE
data bus to a
data distributor for rearrangement and entry into 16 output
registers In this way sequential data can be re-routed or
intermixed according to patterns determined by data select
and distribution inputs
Data is placed into the routing scheme via the 8 inputs on
both CD4512 data selectors One register is assigned to
each input The signals on A0 A1 and A2 choose 1-of-8
inputs for transfer out to the TRI-STATE data bus A fourth
signal labelled Dis disables one of the CD4512 selectors
assuring transfer of data from only one register
In addition to a choice of input registers 1 16 the rate of
transfer of the sequential information can also be varied
That is if the CD4512 were addressed at a rate that is
8 times faster than the shift frequency of the input registers
the most significant bit (MSB) from each register could be
selected for transfer to the data bus Therefore all of the
most significant bits from all of the registers can be trans-
ferred to the data bus before the next most significant bit is
presented for transfer by the input registers
Information from the TRI-STATE bus is redistributed by the
CD4514B 4-bit latch decoder Using the 4-bit address
INA IND the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers A P This distribution of data bits to the output
registers can be made in many complex patterns For exam-
ple all of the most significant bits from the input registers
can be routed into output register A all of the next most
significant bits into register B etc In this way horizontal
vertical or other methods of data slicing can be implement-
ed
TL F 5994 5
5
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