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Электронный компонент: CLC426

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CLC426
Wideband, Low-Noise, Voltage Feedback Op Amp
General Description
The CLC426 combines an enhanced voltage-feedback architecture
with an advanced complementary bipolar process to provide a
high-speed op amp with very low noise (1.6nV/
Hz & 2.0pA/
Hz) and
distortion (-62/-68dBc 2
nd
/3
rd
harmonics at 1V
pp
and 10MHz).
Providing a wide 230MHz gain-bandwidth product, a fast 400V/
s
slew rate and very quick 16ns settling time to 0.05% , the CLC426 is
the ideal choice for high speed applications requiring a very wide-
dynamic range such as an input buffer for high-resolution analog-to-
digital converters.
The CLC426 is internally compensated for gains
2V/V and can
easily be externally compensated for unity-gain stability in applications
such as wideband low-noise integrators. The CLC426 is also equipped
with external supply current adjustment which allows the user to
optimize power, bandwidth, noise and distortion performance for each
application.
The CLC426's combination of speed, low noise and distortion and low
dc errors will allow high-speed signal conditioning applications to
achieve the highest signal-to-noise performance. To reduce design
times and assist board layout, the CLC426 is supported by an
evaluation board and SPICE simulation model available from National.
For even higher gain-bandwidth voltage-feedback op amps see the
1.9GHz CLC425 (A
v
10V/V) or the 5.0GHz CLC422 (A
v
30V/V).
June 1999
CLC426
Wideband,
Lo
w-Noise
,

V
olta
g
e
Feedbac
k Op Amp
Features
s
Wide gain-bandwidth product: 230MHz
s
Ultra-low input voltage noise: 1.6nV/
Hz
s
Very low harmonic distortion: -62/-68dBc
s
Fast slew rate: 400V/
s
s
Adjustable supply current
s
Dual 2.5 to 5V or single 5 to 12V supplies
s
Externally compensatable
Applications
s
Active filters & integrators
s
Ultrasound
s
Low-power portable video
s
ADC/DAC buffer
s
Wide dynamic range amp
s
Differential amps
s
Pulse/RF amp
Wide Dynamic Range
Sallen-Key Band Pass Filter
2nd-Order
(20MHz, Q=10, G=2)
1
2
3
4
NC
V
inv
V
non-inv
-V
cc
R
p (optional)
+V
cc
V
out
Ext. Comp.
(optional)
8
7
6
5
-
+
Pinout
DIP & SOIC
Typical Application
1999 National Semiconductor
Corporation
http://www.national.com
Printed in the U.S.A.
CLC426 Electrical Characteristics
CLC426 Electrical Characteristics
CLC426 Electrical Characteristics
CLC426 Electrical Characteristics
CLC426 Electrical Characteristics
(V
(V
(V
(V
(V
CC
CC
CC
CC
CC
=
=
=
=
=


5V; A
5V; A
5V; A
5V; A
5V; A
V
V
V
V
V
= +2V/V; R
= +2V/V; R
= +2V/V; R
= +2V/V; R
= +2V/V; R
f
f
f
f
f
=100
=100
=100
=100
=100
; R
; R
; R
; R
; R
L
L
L
L
L
= 100
= 100
= 100
= 100
= 100
;
;
;
;
;
unless noted
unless noted
unless noted
unless noted
unless noted
))
))
)
A)J-level: spec is 100% tested at +25C.
1) Minimum stable gain with out external compensation is +2 or
-1V/V, the CLC426 is unity-gain stable with external
compensation.
2) Output is short circuit protected to ground, however maximum
reliability is obtained if output current does not exceed 160mA.
3) See text for compensation techniques.
http://www.national.com
2
supply voltage
7V
short circuit current
(note 2)
common-mode input voltage
V
cc
differential input voltage
10V
maximum junction temperature
+150C
storage temperature
-65C to+150C
lead temperature (soldering 10 sec)
+300C
ESD rating
2000V
Absolute Maximum Ratings
Notes
PARAMETERS
PARAMETERS
PARAMETERS
PARAMETERS
PARAMETERS
CONDITIONS
CONDITIONS
CONDITIONS
CONDITIONS
CONDITIONS




TYP
TYP
TYP
TYP
TYP
MIN/MAX RATINGS
MIN/MAX RATINGS
MIN/MAX RATINGS
MIN/MAX RATINGS
MIN/MAX RATINGS
UNITS
UNITS
UNITS
UNITS
UNITS
NOTES
NOTES
NOTES
NOTES
NOTES
Ambient Temperature
CLC426
+25C
+25C
0 to +70C -40 to +85C
FREQUENCY DOMAIN RESPONSE
gain bandwidth product
V
out
< 0.5V
pp
230
170
120
100
MHz
-3dB bandwidth, A
v
=+2
V
out
< 0.5V
pp
130
90
70
55
MHz
1
V
out
< 5.0V
pp
50
25
22
20
MHz
gain flatness
V
out
< 0.5V
pp
peaking
DC to 200MHz
0.6
1.5
2.2
2.5
dB
rolloff
DC to 30MHz
0.0
0.6
1.0
1.0
dB
linear phase deviation
DC to 30MHz
0.2
1.0
1.5
1.5
TIME DOMAIN RESPONSE
rise and fall time
1V step
2.3
3.5
5.0
6.5
ns
settling time
2V step to 0.05%
16
20
24
24
ns
overshoot
1V step
5
15
15
18
%
slew rate
5V step
400
300
275
250
V/
s
DISTORTION AND NOISE RESPONSE
2
nd
harmonic distortion
1V
pp
,10MHz
- 62
- 52
- 47
- 45
dBc
3
rd
harmonic distortion
1V
pp
,10MHz
- 68
- 58
- 54
- 54
dBc
equivalent input noise
op amp only
voltage
1MHz to 100MHz
1.6
2.0
2.3
2.6
nV/
Hz
current
1MHz to 100MHz
2.0
3.0
3.6
4.6
pA/
Hz
STATIC DC PERFORMANCE
open-loop gain
DC
64
60
54
54
dB
input offset voltage
1.0
2.0
2.8
2.8
mV
A
average drift
3
---
10
10
V/
C
input bias current
5
25
40
65
A
A
average drift
90
---
600
700
nA/
C
input offset current
0.3
3
5
5
A
A
average drift
5
---
25
50
nA/
C
power-supply rejection ratio
DC
73
65
60
60
dB
common-mode rejection ratio
DC
70
62
57
57
dB
supply current
pin #8 open, R
L
=
11
12
13
15
mA
A
MISCELLANEOUS PERFORMANCE
input resistance
common-mode
500
250
125
125
k
differential-mode
750
200
50
25
k
input capacitance
common-mode
2.0
3.0
3.0
3.0
pF
differential-mode
2.0
3.0
3.0
3.0
pF
output resistance
closed loop
0.07
0.1
0.2
0.2
output voltage range
R
L
=
3.8
3.5
3.3
3.3
V
R
L
=100
3.5
3.2
2.6
1.3
V
input voltage range
common mode
3.7
3.5
3.3
3.3
V
output current
70
50
40
+ 35, -20
mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Model
Temperature Range
Description
CLC426AJP
-40C to +85C
8-pin PDIP
CLC426AJE
-40C to +85C
8-pin SOIC
CLC426A8B
-55C to +125C
8-pin CerDIP, MIL-STD-883
Ordering Information
Package


JC


JA
Plastic (AJP)
70C/W
125C/W
Surface Mount (AJE)
60C/W
140C/W
CerDIP
40C/W
130C/W
Package Thermal Resistance
Transistor Count
52
Reliability Information
3
http://www.national.com
Introduction
The CLC426 is a wide bandwidth voltage-feedback opera-
tional amplifier that is optimized for applications requiring
wide dynamic range. The CLC426 features adjustable
supply current and external compensation for the added
flexibility of tuning its performance for demanding applica-
tions. The Typical Performance section illustrates many
of the performance trade-offs. Although designed to oper-
ate from 5Volt power supplies, the CLC426 is equally
impressive operating from a single +5V supply. The
following discussion will enable the proper selection of
external components for optimum device performance in
a variety of applications.
External Compensation
The CLC426 is stable for noise gains
2V/V. For unity-gain
operation, the CLC426 requires an external compensation
capacitor (from pin 5 to ground). The plot located in the
Typical Performance section labeled "Frequency Re-
sponse vs Compensation Cap." illustrates the CLC426's
typical AC response for different values of compensation
capacitor. From the plot it is seen that a value of 15pF
produces the optimal response of the CLC426 at unity
gain. The plot labeled "Open-Loop Gain vs. Compensation
Cap." illustrates the CLC426's open-loop behavior for
various values of compensation capacitor. This plot also
illustrates one technique of bandlimiting the device by
reducing the open-loop gain resulting in lower closed-loop
bandwidth. Fig. 1 shows the effect of external compensa-
tion on the CLC426's pulse response.
Application Discussion
Fig. 1
http://www.national.com
4
Supply Current Adjustment
The CLC426's supply current can be externally adjusted
downward from its nominal value to less than 2mA by
adding an optional resistor (R
p
) between pin 8 and the
negative supply as shown in fig 2. The plot labeled "Open-
Loop Gain vs. Supply Current" illustrates the influence
that supply current has over the CLC426's open-loop
response. From the plot it is seen that the CLC426 can be
compensated for unity-gain stability by simply lowering
its supply current. Therefore lowering the CLC426's sup-
ply current effectively reduces its open-loop gain to the
point that there is adequate phase margin at unity gain
crossover. The plot labeled "Supply Current vs. R
p
"
provides the means for selecting the value of R
p
that
produces the desired supply current. The curve in the plot
represents nominal processing but a 12% deviation over
process can be expected. The two plots labeled "Voltage
Noise vs. Supply Current" and "Current Noise vs. Supply
Current" illustrate the CLC426 supply current's effect over
its input-referred noise characteristics.
Driving Capacitive Loads
The CLC426 is designed to drive capacitive loads with the
addition of a small series resistor placed between the
output and the load as seen in fig. 3. Two plots located in
the Typical Performance section illustrate this technique
for both frequency domain and time domain applications.
The plot labeled "Frequency Response vs. Capacitive
Load" shows the CLC426's resulting AC response to
various capacitive loads. The values of R
s
in this plot
were chosen to maximize the CLC426's AC response
(limited to
1dB peaking).
The second plot labeled "Settling Time vs. Capacitive
Load" provides the means for the selection of the value of
R
s
which minimizes the CLC426's settling time. As seen
from the plot, for a given capacitive load R
s
is chosen from
the curve labeled "R
s
". The resulting settling time to
0.05% can then be estimated from the curve labeled "T
s
to 0.05%". The plot of fig. 4 shows the CLC426's pulse
response for various capacitive loads where R
s
has been
chosen from the plot labeled "Settling Time vs. Capaci-
tive Load".
Faster Settling
The circuit of fig. 5 shows an alternative method for driving
capacitive loads that results in quicker settling times. The
small series-resistor, R
s
, is used to decouple the CLC426's
open-loop output resistance, R
out
, from the load capaci-
tance. The small feedback-capacitance, C
f
, is used to
provide a high-frequency bypass between the output and
inverting input. The phase lead introduced by C
f
compen-
sates for the phase lag due to C
L
and therefore restores
stability. The following equations provide values of R
s
and
C
f
for a given load capacitance and closed-loop amplifier
gain.
Eq. 1
Eq. 2
The plot in
fig. 6 shows
the result of the two methods of capacitive load driving
mentioned above while driving a 100pF||1k
load.
Fig. 2
Fig. 4
Fig. 5
Fig. 3
R
R
R
R
where R
C
R
R
C
R
R
s
out
f
g
out
f
g
L
out
g
=


= +




;
6
1
1
2
Fig. 6
5
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