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Электронный компонент: CLC430

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CLC430
General Purpose 100MHz Op Amp with Disable
General Description
The CLC430 is a low-cost, wideband monolithic amplifier for general
purpose applications. The CLC430 utilizes National's patented
current feedback circuit topology to provide an op amp with a slew rate
of 2000V/
s, 100MHz unity-gain bandwidth and fast output disable
function. Like all current feedback op amps, the CLC430 allows the
frequency response to be optimized (or adjusted) by the selection of
the feedback resistor. For demanding video applications, the 0.1dB
bandwidth to 20MHz and differential gain/phase of 0.03%/0.05 make
the CLC430 the preferred component for broadcast quality NTSC and
PAL video systems.
The large voltage swing (28V
pp
), continuous output current (85mA)
and slew rate (2000V/
s) provide high-fidelity signal conditioning for
applications such as CCDs, transmission lines and low impedance
circuits. Even driving loads of 100
, the CLC430 provides very low
2nd and 3rd harmonic distortion at 1MHz (-76/-82dBc).
Video distribution, multimedia and general purpose applications will
benefit from the CLC430's wide bandwidth and disable feature. Power
is reduced and the output becomes a high impedance when disabled.
The wide gain range of the CLC430 makes this general purpose op
amp an improved solution for circuits such as active filters, differen-
tial-to-single-ended drivers, DAC transimpedance amplifiers and
MOSFET drivers.
June 1999
Features
s
0.1dB gain flatness to 20MHz (A
v
=+2)
s
100MHz bandwidth (A
v
=+1)
s
2000V/
s slew rate
s
0.03%/0.05 differential gain/phase
s
5V, 15V or single supplies
s
100ns disable to high-impedance output
s
Wide gain range
s
Low cost
Applications
s
Video distribution
s
CCD clock driver
s
Multimedia systems
s
DAC output buffers
s
Imaging systems
CLC430
General Purpose 100MHz Op Amp with Disable
Pinout
DIP & SOIC
Typical Application
CCD Clock Driver
1999 National Semiconductor
Corporation
http://www.national.com
Printed in the U.S.A.
CLC430 Electrical Characteristics
(V
CC
= 15V; A
V
= +2V/V; R
f
=604
; R
L
= 100
;
unless noted
)
PARAMETERS
CONDITIONS
V
cc
TYP
MIN/MAX RATINGS
UNITS
NOTES
Ambient Temperature
CLC430
25C
25C
0 to 70C -40 to 85C
FREQUENCY DOMAIN RESPONSE
unity-gain bandwidth
V
out
< 1.0V
pp
15
100
MHz
small-signal bandwidth
V
out
< 1.0V
pp
15
75
50
45
42
MHz
V
out
< 1.0V
pp
5
55
35
MHz
0.1dB bandwidth
V
out
< 1.0V
pp
15
20
7
MHz
V
out
< 1.0V
pp
5
16
MHz
large-signal bandwidth
V
out
= 10V
pp
30
22
20
19
MHz
gain flatness
V
out
< 1.0V
pp
peaking
DC to 10MHz
0.0
0.1
0.2
0.2
dB
rolloff
DC to 20MHz
0.1
0.7
1.0
1.2
dB
linear phase deviation
DC to 20MHz
0.5
1.8
2.0
2.1
differential gain
4.43MHz, R
L
=150
15
0.03
0.05
0.06
0.06
%
4.43MHz, R
L
=150
5
0.03
0.05
%
differential phase
4.43MHz, R
L
=150
15
0.05
0.09
0.12
0.13
4.43MHz, R
L
=150
5
0.09
0.19
TIME DOMAIN RESPONSE
rise and fall time
2V step
5
7
7
7
ns
10V step
10
14
14
14
ns
settling time to 0.05%
2V step
35
50
55
55
ns
overshoot
2V step
5
15
15
15
%
slew rate
20V step
2000
1500
1450
1450
V/
s
DISTORTION AND NOISE RESPONSE
2
nd
harmonic distortion
1V
pp
,1MHz, R
L
=500
-89
dBc
3
rd
harmonic distortion
1V
pp
,1MHz, R
L
=500
-92
dBc
input voltage noise
>1MHz
3.0
3.5
3.7
3.8
nV/
Hz
non-inverting input current noise >1MHz
3.2
6.0
6.3
6.8
pA/
Hz
inverting input current noise
>1MHz
15
18
20
21
pA/
Hz
DC PERFORMANCE
input offset voltage
15
1.0
7.5
9.0
10.0
mV
A
average drift
25
---
50
50
V/ C
input bias current
non-inverting
15,5
3
14
16
20
A
A
average drift
10
---
100
100
nA/C
input bias current
inverting
15,5
3
14
15
17
A
A
average drift
10
---
60
90
nA/C
power-supply rejection ratio
DC
62
56
54
53
dB
common-mode rejection ratio DC
62
54
53
52
dB
supply current
R
L
=
15,5
11, 8.5
12
13
14.5
mA
A
disabled
R
L
=
15,5
1.5
2.0
2.2
2.4
mA
A
SWITCHING PERFORMANCE
turn on time
200
300
320
340
ns
turn off time
(Note 2)
100
200
200
200
ns
off isolation
10MHz
59
56
56
56
dB
high input voltage
V
IH
15
11.8
12.5
12.7
V
5
1.8
2.5
2.7
V
low input voltage
V
IL
15
10.8
10.5
10.0
V
5
0.8
0.6
0.1
V
MISCELLANEOUS PERFORMANCE
Non-inverting input resistance
8.0
3.0
2.5
1.7
M
Non-inverting input capacitance
0.5
1.0
1.0
1.0
pF
input voltage range
common mode
15
12.5
12.3
12.1
11.8
V
common mode
5
2.5
2.3
2.2
1.9
V
output voltage range
R
L
=
15
14
13.7
13.7
13.6
V
R
L
=
5
4.0
3.9
3.8
3.7
V
output current
85
60
50
45
mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels
are determined from tested parameters.
http://www.national.com
2
Absolute Maximum Ratings
supply voltage
16.5V
short circuit current
(note 1)
common-mode input voltage
V
cc
maximum junction temperature
+150C
storage temperature
-65C to+150C
lead temperature (soldering 10 sec)
+300C
ESD rating (human body model)
4000V
Notes
A)J-level: spec is 100% tested at +25C.
1) Output is short circuit protected to ground, however
maximum reliability is obtained if output current does not
exceed 125mA.
2) To>50dB attenuation @ 10MHz.
3
http://www.national.com
http://www.national.com
4
Model
Temperature Range
Description
CLC430AJP
-40C to +85C
8-pin PDIP
CLC430AJE
-40C to +85C
8-pin SOIC
CLC430A8B
-55C to +125C
8-pin CERDIP, MIL-STD-883
DESC SMD number: 5962-92030.
Ordering Information
Reliability Information
Transistor count
38
Package Thermal Resistance
Package




JC




JA
AJP
60C/W
115C/W
AJE
55C/W
135C/W
A8B
30C/W
120C/W
General Design Considerations
The CLC430 is a general purpose current-feedback ampli-
fier for use in a variety of small- and large-signal applica-
tions. Use the feedback resistor to fine tune the gain
flatness and -3dB bandwidth for any gain setting. Com-
linear provides information for the performance at a gain of
+2 for small and large signal bandwidths. The plots show
feedback resistor values for selected gains.
Gain
Use the following equations to set the CLC430's non-
inverting or inverting gain:
Non -Inverting Gain = 1+
R
R
f
g
Inverting Gain = -
R
R
f
g
Choose the resistor values for non-inverting or inverting
gain by the following steps.
V
in
V
out
R
f
R
g
R
s
R
in
CLC430
+
-
Fig. 0 Component Identification
1)
Select the recommended feedback resistor R
f
(refer
to plot in the plot section entitled
R
f
vs Gain).
2)
Choose the value of R
g
to set gain.
3)
Select R
s
to set the circuit output impedance.
4)
Select R
in
for input impedance and input bias.
High Gains
Current feedback closed-loop bandwidth is independent of
gain-bandwidth-product for small gain changes. For larger
gain changes the optimum feedback register R
f
is derived
by the following:
As gain is increased, the feedback resistor allows bandwidth
to be held constant over a wide gain range. For a more
complete explanation refer to application note OA-25 Stabil-
ity Analysis of Current-Feedback Amplifiers.
Resistors have varying parasitics that affect circuit perfor-
mance in high-speed design. For best results, use leaded
metal-film resistors or surface mount resistors. A SPICE
model for the CLC430 is available to simulate overall
circuit performance.
Enable / Disable Function
The CLC430 amplifier features an enable/disable function
that changes the output and inverting input from low to high
impedance. The pin 8 enable/disable logic levels are as
follows:
V
cc
15V
5V
Enable
>12.7V
>2.7V
Disable
<10.0V
<0.8V
The amplifier is enabled with pin 8 left open due to the 2k
pull-up resistor, shown in Fig. 1.
To CLC430
Bias network
2k
+V
cc
Pin 8 DISABLE
8k
-V
cc
Fig. 1 Pin 8 Equivalent Disable Circuit
Open-collector or CMOS interfaces are recommended to
drive pin 8. The turn-on and off time depends on the speed
of the digital interface.
The equivalent output impedance when disabled is shown
in Fig. 2. With R
g
connected to ground, the sum of R
f
and
R
g
dominates and reduces the disabled output imped-
ance. To raise the output impedance in the disabled state,
connect the CLC430 as a unity-gain voltage follower by
removing R
g
. Current-feedback op-amps need the recom-
mended R
f
in a unity-gain follower circuit. For high density
circuit layouts consider using the dual CLC431 (with
disable) or the dual CLC432 (without disable).
Equivalent Impedance
in Disable
R
f
V
out
R
g
V
in
300k
8pF
+
-
Fig. 2 Equivalent Disabled Output Impedance
2
nd
and 3
rd
Harmonic Distortion
To meet low distortion requirements, recognize the effect
of the feedback resistor. Increasing the feedback resistor
will decrease the loop gain and increase distortion. De-
creasing the load impedance increases 3
rd
harmonic
distortion more than 2
nd
.
Differential Gain and Differential Phase
The CLC430 has low DG and DP errors for video applica-
tions. Add an external pulldown resistor to the CLC430's
output to improve DG and DP as seen in Fig.3. A 604
R
P
will improve DG and DP to 0.01% and 0.02.
5
http://www.national.com
R
A
f
v
=
-
( )
724
60