Features
s
0.1dB gain flatness to 20MHz (A
v
= +2)
s
90MHz bandwidth (A
v
= +1)
s
Large signal BW 25MHz
s
1800V/
s slew rate
s
0.05%/0.05 differential gain/phase
s
5V, 15V or single supplies
s
200ns disable to high-impedance output
s
Wide gain range
s
-89/-92dBc HD2/HD3 (R
L
= 500
)
s
Low cost
Applications
s
xDSL driver
s
Twisted pair driver
s
Cable driver
s
Video distribution
s
CCD clock driver
s
Multimedia systems
s
DAC output buffers
s
Imaging systems
1
2
3
4
NC
V
V
-V
inv
non-inv
cc
DIS
+V
V
NC
cc
out
8
7
6
5
-
+
+
-
CLC5665
-
+
R
f1
604
R
g
1.2k
CLC5665
+
-
R
o
R
o
R
f2
604
R
L
1:n
V
in
(V
pp
)
V
o
= 2V
in
nV
o
Note: Supply and Bypassing not shown.
DIS
DIS
Typical Application
Differential Line Driver for xDSL
Pinout
DIP & SOIC
General Description
The CLC5665 is a low-cost, wideband amplifier that provides very
low 2nd and 3rd harmonic distortion at 1MHz (-89/-92dBc). The
great slew rate of 1800V/
s, bandwidth of 90MHz (A
v
= +1) and
fast disable make it an excellent choice for many high speed
multiplexing applications. Like all current feedback op amps, the
CLC5665 allows the frequency response to be optimized
(or adjusted) by the selection of the feedback resistor. For
demanding video applications, the 0.1dB bandwidth to 20MHz
and differential gain/phase of 0.05%/0.05 make the CLC5665
the preferred component for broadcast quality NTSC and PAL
video systems.
The large voltage swing (28V
pp
), continuous output current
(85mA) and slew rate (1800V/
s) provide high-fidelity signal
conditioning for applications such as CCDs, transmission lines
and low impedance circuits.
xDSL, video distribution, multimedia and general purpose
applications will benefit from the CLC5665's wide bandwidth and
disable feature. Power is reduced and the output becomes a high
impedance when disabled. The wide gain range of the CLC5665
makes this general purpose op amp an improved solution for
circuits such as active filters, single-to-differential-ended drivers,
DAC transimpedance amplifiers and MOSFET drivers.
Non-Inverting Frequency Response
Magnitude (1dB/div)
Frequency (MHz)
1
10
100
Gain
Phase (deg)
-90
0
-180
-45
-135
Phase
A
v
= 2
R
f
= 604
A
v
= 1
R
f
= 698
A
v
= 10
R
f
= 100
A
v
= 50
R
f
= 500
A
v
= 1
A
v
= 2
A
v
= 10
A
v
= 50
CLC5665
Low Distortion Amplifier with Disable
N
June 1999
CLC5665
Lo
w Distor
tion Amplifier with Disab
le
1999 National Semiconductor Corporation
http://www.national.com
Printed in the U.S.A.
http://www.national.com
2
PARAMETERS
CONDITIONS
V
cc
TYP
MIN/MAX RATINGS
UNITS NOTES
Ambient Temperature
CLC5665
+25C
+25C
0 to 70C -40 to 85C
FREQUENCY DOMAIN RESPONSE
small-signal bandwidth (A
v
= +1) V
out
< 1.0V
pp
15
90
MHz
small-signal bandwidth
V
out
< 1.0V
pp
15
70
MHz
V
out
< 1.0V
pp
5
50
MHz
0.1dB bandwidth
V
out
< 1.0V
pp
15
20
MHz
V
out
< 1.0V
pp
5
15
MHz
large-signal bandwidth
V
out
= 10V
pp
25
MHz
gain flatness
V
out
< 1.0V
pp
peaking
DC to 10MHz
0.03
dB
rolloff
DC to 20MHz
0.1
dB
linear phase deviation
DC to 20MHz
0.7
deg
differential gain
4.43MHz, R
L
= 150
15
0.05
%
4.43MHz, R
L
= 150
5
0.05
%
differential phase
4.43MHz, R
L
= 150
15
0.05
deg
4.43MHz, R
L
= 150
5
0.1
deg
TIME DOMAIN RESPONSE
rise and fall time
2V step
5
ns
10V step
10
ns
settling time to 0.05%
2V step
35
ns
overshoot
2V step
5
%
slew rate
20V step
1800
V/
s
DISTORTION AND NOISE RESPONSE
2nd harmonic distortion
1V
pp
,1MHz, R
L
= 500
-89
dBc
3rd harmonic distortion
1V
pp
,1MHz, R
L
= 500
-92
dBc
input voltage noise
>1MHz
3.0
nV/
Hz
non-inverting input current noise >1MHz
3.2
pA/
Hz
inverting input current noise
>1MHz
15
pA/
Hz
DC PERFORMANCE
input offset voltage
15
1.0
7.5
9.0
10.0
mV
A
average drift
25
V/C
input bias current
non-inverting
15, 5
3
20
20
20
A
A
average drift
10
nA/C
input bias current
inverting
15, 5
3
20
20
20
A
A
average drift
10
nA/C
power-supply rejection ratio
DC
60
55
50
50
dB
common-mode rejection ratio
DC
60
55
50
50
dB
supply current
R
L
=
15, 5
11, 8.5
12
14
15
mA
A
disabled
R
L
=
15, 5
1.5
2.5
2.5
2.5
mA
A
SWITCHING PERFORMANCE
turn on time
400
500
550
550
ns
turn off time
(Note 2)
200
800
800
800
ns
off isolation
10MHz
59
56
56
56
dB
high input voltage
V
IH
15
11.8
12.5
12.7
V
5
1.8
2.5
2.7
V
low input voltage
V
IL
15
10.8
10.5
10.0
V
5
0.8
0.6
0.1
V
MISCELLANEOUS PERFORMANCE
non-inverting input resistance
8.0
3.0
2.5
1.7
M
non-inverting input capacitance
0.5
1.0
1.0
1.0
pF
input voltage range
common mode
15
12.5
12.3
12.1
11.8
V
common mode
5
2.5
2.3
2.2
1.9
V
output voltage range
R
L
=
15
14
13.7
13.7
13.6
V
R
L
=
5
4.0
3.9
3.8
3.7
V
output current
85
60
50
45
mA
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
CLC5665 Electrical Characteristics
(V
CC
= 15V, A
v
= +2V/V; R
f
= 604
, R
L
= 100
; unless specified)
Absolute Maximum Ratings
supply voltage
16V
short circuit current
(see note 1)
common-mode input voltage
V
CC
maximum junction temperature
+150C
storage temperature range
-65C to +150C
lead temperature (soldering 10 sec)
+300C
Notes
A) J-level: spec is 100% tested at +25C.
1) Output is short circuit protected to ground, however
maximum reliability is obtained if output current does not
exceed 125mA.
2) To >50dB attenuation @ 10MHz.
3
http://www.national.com
CLC5665 Typical Performance
(V
CC
= 15V, A
v
= +2V/V; R
f
= 604
, R
L
= 100
; unless specified)
Non-Inverting Frequency Response
Magnitude (1dB/div)
Frequency (MHz)
1
10
100
Gain
Phase (deg)
-90
0
-180
-45
-135
Phase
A
v
= 2
R
f
= 604
A
v
= 1
R
f
= 698
A
v
= 10
R
f
= 100
A
v
= 50
R
f
= 500
A
v
= 1
A
v
= 2
A
v
= 10
A
v
= 50
Inverting Frequency Response
Magnitude (1dB/div)
Frequency (MHz)
1
10
100
Gain
Phase (deg)
-90
0
-180
-45
-135
Phase
A
v
= -2
R
f
= 500
A
v
= -1
R
f
= 500
A
v
= -10
R
f
= 500
A
v
= -50
R
f
= 2.5k
A
v
= -10
A
v
= -2
A
v
= -1
A
v
= -50
Frequency Response vs. Load
Magnitude (1dB/div)
Frequency (MHz)
1
10
100
Gain
Phase (deg)
-90
0
-180
-45
-135
Phase
R
L
= 1k
R
L
= 100
R
L
= 50
R
L
= 1k
R
L
= 100
R
L
= 50
Open-Loop Transimpedance Gain (Zs)
Gain (20 log)
Frequency (MHz)
0.0001
0.001
0.01
1
10
0.1
100
Gain
Phase (deg)
120
160
100
140
40
80
20
60
0
60
40
30
70
50
100
80
110
90
120
130
Phase
Flatness Gain and Linear Phase
Magnitude (0.1dB/div)
Frequency (MHz)
0
4
8
12
16
20
Gain
Phase (0.2
/div)
Phase
Equivalent Input Noise
Noise Voltage (nV/
Hz)
Frequency (MHz)
0.1k
1k
10k
100k
1M
100M
Inverting Current 14.8pA/
Hz
Noise Current (pA/
Hz)
Non-Inverting Current 3.2pA/
Hz
Voltage 3.0nV/
Hz
10M
1
10
100
Signal Pulse Response
Large Signal Output (2V/div)
Time (20ns/div)
Large Signal
Small Signal Output (0.5V/div)
Small Signal
PSRR, CMRR and Closed Loop R
o
PSRR/CMRR (dB)
Frequency (MHz)
0.01
0.10
1
10
100
CMRR
20 log R
o
20
10
0
30
50
40
60
70
-20
-30
-40
-10
10
0
20
30
PSRR
20 log R
o
Differential Gain and Phase (3.58MHz)
Gain (%)
Number of 150
Loads
1
2
3
4
Gain Negative Sync
Phase (deg)
0.04
0.02
0
0.06
0.08
1
0.12
0.06
0.03
0.18
0.24
0.30
Gain Positive Sync
Phase Negative Sync
Phase
Positive Sync
Short Term Settling Time
Settling Error (%)
Time (10ns/div)
2V output step
Short Term
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
I
BI
, I
BN
. V
OS
vs. Temperature
V
OS
(mV)
Temperature (
C)
-60
-20
20
60
100
140
I
BI
I
BI
, I
BN
(
A)
1.5
0.5
2.0
1.0
3.5
2.5
4.0
3.0
4.5
0
-2.0
-3.0
1.0
-1.0
4.0
2.0
5.0
3.0
6.0
7.0
I
BN
V
OS
0
5.0
2-Tone, 3rd Order Intermodulation Intercept
Intercept (+dBm)
Frequency (MHz)
10
6
10
7
10
30
20
50
40
60
50
750
750
50
P
out
-1dBm Compression to Load
Compression Point (dBm)
Frequency (MHz)
0
5
10
15
20
25
30
35
40
45
50
6
14
10
22
18
26
8
16
12
24
20
V
in
698
50
50
Load
698
Harmonic Distortion vs. Frequency
Distortion Level (dBc)
Frequency (MHz)
1
10
100
-100
-60
-80
-20
-40
0
-90
-50
-70
-10
-30
R
L
= 100
V
out
= 2V
pp
2nd
V
CC
=
5V
2nd
V
CC
=
15V
3rd
V
CC
=
15V
3rd
V
CC
=
5V
Harmonic Distortion vs. Frequency
Distortion Level (dBc)
Frequency (MHz)
1
10
100
-100
-60
-80
-20
-40
0
-90
-50
-70
-10
-30
R
L
= 500
V
out
= 2V
pp
2nd
V
CC
=
5V
2nd
V
CC
=
15V
3rd
V
CC
=
15V
3rd
V
CC
=
5V
http://www.national.com
4
The CLC5665 is a general purpose current-feedback
amplifier for use in a variety of small- and large-signal
applications. Use the feedback resistor to fine tune the
gain flatness and -3dB bandwidth for any gain setting.
National provides information for the performance at a
gain of +2 for small and large signal bandwidths. The
plots show feedback resistor values for selected gains.
Gain
Use the following equations to set the CLC5665's non-
inverting or inverting gain:
Choose the resistor values for non-inverting or inverting
gain by the following steps.
Figure 1: Component Identification
1) Select the recommended feedback resistor R
f
.
2) Choose the value of R
g
to set gain.
3) Select R
s
to set the circuit output impedance.
4) Select R
in
for input impedance and input bias.
High Gains
Current feedback closed-loop bandwidth is independent
of gain-bandwidth-product for small gain changes. For
larger gain changes the optimum feedback register R
f
is
derived by the following:
R
f
= 724
60
(A
v
)
As gain is increased, the feedback resistor allows band-
width to be held constant over a wide gain range. For a
more complete explanation refer to application note OA-25:
Stability Analysis of Current-Feedback Amplifiers.
Resistors have varying parasitics that affect circuit
performance in high-speed design. For best results, use
leaded metal-film resistors or surface mount resistors. A
SPICE model for the CLC5665 is available to simulate
overall circuit performance.
Enable/Disable Function
The CLC5665 amplifier features an enable/disable
function that changes the output and inverting input from
low to high impedance. The pin 8 enable/disable logic
levels are as follows:
V
CC
15V
5V
Enable
>12.7V
>2.7V
Disable
<10.0V
<0.8V
The amplifier is enabled with pin 8 left open due to the
2k
pull-up resistor, shown in Figure 2.
Figure 2: Pin 8 Equivalent Disable Circuit
Open-collector or CMOS interfaces are recommended to
drive pin 8. The turn-on and off time depends on the
speed of the digital interface.
The equivalent output impedance when disabled is
shown in Figure 3. With R
g
connected to ground, the sum
of R
f
and R
g
dominates and reduces the disabled output
impedance. To raise the output impedance in the dis-
abled state, connect the CLC5665 as a unity-gain
voltage follower by removing R
g
. Current-feedback
op-amps need the recommended R
f
in a unity-gain
follower circuit. For high density circuit layouts consider
using the dual CLC431 (with disable) or the dual CLC432
(without disable).
Figure 3: Equivalent Disabled Output Impedance
Non Inverting Gain
1
R
R
Inverting Gain
-R
R
f
g
f
g
-
=
+
=
R
in
R
g
R
f
CLC5665
+
-
V
in
V
o
R
s
To CLC5665
Bias network
2k
+V
cc
Pin 8 DISABLE
8k
-V
cc
Equivalent Impedance
in Disable
R
f
V
out
R
g
V
in
300k
8pF
+
-
Z
out
(
)
Frequency (MHz)
1
10
100
1
10
100
1k
10k
100k
1M
CLC5665 Design Considerations
2nd and 3rd Harmonic Distortion
To meet low distortion requirements, recognize the effect
of the feedback resistor.
Increasing the feedback
resistor will decrease the loop gain and increase
distortion. Decreasing the load impedance increases 3rd
harmonic distortion more than 2nd.
Differential Gain and Differential Phase
The CLC5665 has low DG and DP errors for video
applications. Add an external pulldown resistor to the
CLC5665's output to improve DG and DP as seen in
Figure 4. A 604
R
p
will improve DG and DP to 0.01%
and 0.02.
Figure 4: Improved DG and DP Video Amplifier
Printed Circuit Layout
To get the best amplifier performance careful placement
of the amplifier, components and printed circuit traces
must be observed. Place the 0.1
F ceramic decoupling
capacitors less than 0.1" (3mm) from the power supply
pins.
Place the 6.8
F tantalum capacitors less than
0.75" (20mm) from the power supply pins. Shorten traces
between the inverting pin and components to less
than 0.25" (6mm). Clear ground plane 0.1" (3mm) away
from pads and traces that connect to the inverting, non-
inverting and output pins. Do not place ground or power
plane beneath the op-amp package. National provides
literature and evaluation boards CLC730013 DIP or
CLC730027 SOIC illustrating the recommended op-amp
layout.
Level Shifting
The circuit shown in Figure 5 implements level shifting by
AC coupling the input signal and summing a DC voltage.
The resistor R
in
and the capacitor C set the high-pass
break frequency. The amplifier closed-loop bandwidth is
fixed by the selection of R
f
. The DC and AC gains for
circuit of Figure 5 are different. The AC gain is set by the
ratio of R
f
and R
g
. And the DC gain is set by the parallel
combination of R
g
and R
2
.
Figure 5: Level Shifting Circuit
Multiplexing
Multiple signal switching is easily handled with the dis-
able function of the CLC5665. Board trace capacitance
at the output pin will affect the frequency response and
switching transients. To lessen the effects of output
capacitance place a resistor (R
o
) within the feedback
loop to isolate the outputs as shown in Figure 6. To match
the mux output impedance to a transmission line, add a
resistor (R
s
) in series with the output.
Figure 6: Output Connection for
Multiplexing Circuits
Differential Line Driver With Load
Impedance Conversion
The circuit shown in Figure 7, operates as a differential
line driver. The transformer converts the load impedance
to a value that best matches the CLC5665's output
capabilities. The single-ended input signal is converted
to a differential signal by the CLC5665. The line's
characteristic impedance is matched at both the input
and the output. The schematic shows Unshielded Twisted
Pair for the transmission line; other types of lines can also
be driven.
Figure 7: Differential Line Driver with
Load Impedance Conversion
5
http://www.national.com
V
in
-V
cc
V
out
Add R to
improve
DG and DP
p
R
p
R
f
R
g
R
s
R
in
CLC5665
+
-
Applications Circuits
V
V
R
R
R
V
R
R
out
in
f
g
in
f
ac
DC
=
+
-
1
2
2
C
V
in
DC
V
in
AC
V
out
R
f
R
g
R
2
R
in
+
-
CLC5665
R
f
R
f
R
s
R
o
R
o
R
in
R
in
R
L
R
g
R
g
V
out
V
in1
V
in2
DIS1
DIS2
CLC5665
CLC5665
-
+
+
-
+
-
CLC5665
R
g2
+
V
o
-
-
+
R
t2
R
f2
R
f1
R
g1
CLC5665
V
in
R
t1
R
m/2
R
m/2
R
L
Z
o
UTP
I
o
R
eq
1:n
V
d/2
-V
d/2
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