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Электронный компонент: DP84244J

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TL F 5219
DP84240DP84244
Octal
TRI-STATE
MOS
Drivers
March 1986
DP84240 DP84244 Octal TRI-STATE
MOS Drivers
General Description
The DP84240 and DP84244 are octal TRI-STATE drivers
which are designed for heavy capacitive load applications
such as fast data buffers or as memory address drivers The
DP84240 is an inverting driver which is pin-compatible with
both the 74S240 and AM2965 The DP84244 is a non-in-
verting driver which is pin-compatible with the 74S244 and
AM2966 These parts are fabricated using an oxide isolation
process for much faster speeds and are specified for
250 pF and 500 pF load capacitances
TRI-STATE
is a registered trademark of National Semiconductor Corp
Features
Y
t
pd
specified with 250 pF and 500 pF loads
Y
Output specified from 0 8V to 2 7V
Y
Designed for symmetric rise and fall times at 500 pF
Y
Outputs glitch free at power up and power down
Y
PNP inputs reduce DC loading on bus lines
Y
Low static and dynamic input capacitance
Y
Low skew times between edges and pins
Y
AC parameters specified with all outputs switching
simultaneously
Connection Diagram
Truth Table
DP84240
TL F 5219 1
Top View
Order Number DP84240J or DP84240N
See NS Package Numbers J20A or N20A
Inputs
Outputs
G
A
Y
H
X
Z
L
L
H
L
H
L
H
e
High Level
L
e
Low Level
X
e
Don't Care
Z
e
High Impedance
DP84244
TL F 5219 2
Top View
Order Number DP84244J or DP84244N
See NS Package Numbers J20A or N20A
Inputs
Outputs
G
A
Y
H
X
Z
L
L
L
L
H
H
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage V
CC
7 0V
Logical ``1'' Input Voltage
7 0V
Logical ``0'' Input Voltage
b
1 5V
Storage Temperature Range
b
65 C to
a
150 C
Power Dissipation
Cavity Package
1150 mW
Molded Package
1300 mW
Lead Temperature (soldering 10 sec )
300 C
Operating Conditions
Min
Max
Units
V
CC
Supply Voltage
4 5
5 5
V
T
A
Ambient Temperature
0
a
70
C
Electrical Characteristics
V
CC
e
5V
g
10% 0
s
T
A
s
70 C (Notes 2 and 3 )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IN(1)
Logical ``1'' Input Voltage
2 0
V
V
IN(0)
Logical ``0'' Input Voltage
0 8
V
I
IN(1)
Logical ``1'' Input Current
V
IN
e
2 7V
0 1
20
m
A
V
IN
e
7 0V
100
m
A
I
IN(0)
Logical ``0'' Input Current
0
s
V
IN
s
0 4V
b
50
b
200
m
A
V
CLAMP
Input Clamp Voltage
I
IN
e b
18 mA
b
1
b
1 2
V
V
OH
Logical ``1'' Output Voltage
I
OH
e b
100 mA
V
CC
1 15
4 3
V
I
OH
e b
1 mA
V
CC
b
1 5
3 9
V
OL
Logical ``0'' Output Voltage
I
OL
e
10 mA
0 2
0 4
V
I
OL
e
12 mA
0 3
0 5
I
1D
Logical ``1'' Drive Current
V
OUT
e
1 5V
b
75
b
250
mA
I
0D
Logical ``0'' Drive Current
V
OUT
e
1 5V
a
100
a
150
mA
Hi-Z
TRI-STATE Output Current
0 4V
s
V
OUT
s
2 7V
b
100
a
100
m
A
I
CC
Supply Current
All Outputs Open
DP84240
All Outputs High
16
50
All Outputs Low
74
125
All Outputs Hi-Z
80
125
DP84244
All Outputs High
40
75
mA
All Outputs Low
100
130
All Outputs Hi-Z
115
150
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
Note 2
All currents into device pins shown as positive all currents out of device pins shown as negative all voltages referenced to ground unless otherwise noted
All values shown as max or min are on an absolute value basis
Note 3
Typical characteristics are taken at V
CC
e
5 0V and T
A
e
25 C
Note 4
The output-to-output skew is primarily a function of the number of outputs switching and the capacitive loading on those outputs See
Figures 5 and 6 for
the switching time variations
2
Switching Characteristics
V
CC
e
5V
g
10% 0
s
T
A
s
70 C all outputs loaded with specified load capaci-
tance and all eight outputs switching simultaneously (Note 3 )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PLH
Propagation Delay from
Figures 1
3
CL
e
250 pF
9
16
27
ns
LOW-to-HIGH Output
C
L
e
500 pF
10
20
33
t
PHL
Propagation Delay from
C
L
e
250 pF
9
16
25
ns
HIGH-to-LOW Output
C
L
e
500 pF
12
20
31
t
PLZ
Output Disable Time from LOW
Figures 2
4 S
e
1 C
L
e
50 pF
11
24
ns
t
PHZ
Output Disable Time from HIGH
Figures 2
4 S
e
2 C
L
e
50 pF
12
24
ns
t
PZL
Output Enable Time to LOW
Figures 2
4 S
e
1 C
L
e
500 pF
30
45
ns
t
PZH
Output Enable Time to HIGH
Figures 2
4 S
e
2 C
L
e
500 pF
23
35
ns
t
SKEW
Output-to-Output Skew (Note 4)
Figures 1
3 C
L
e
500 pF
3
ns
Capacitance
T
A
e
25 C f
e
1 MHz V
CC
e
5V
g
10% (Note 3 )
Parameter
Conditions
Typ
Units
C
IN
All Other Inputs Tied Low
6
pF
C
OUT
Output in TRI-STATE Mode
20
pF
Note 1
``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed Except for ``Operating Temperature Range''
they are not meant to imply that the devices should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device
operation
Note 2
All currents into device pins shown as positive all currents out of device pins shown as negative all voltages referenced to ground unless otherwise noted
All values shown as max or min are on an absolute value basis
Note 3
Typical characteristics are taken at V
CC
e
5 0V and T
A
e
25 C
Note 4
The output-to-output skew is primarily a function of the number of outputs switching and the capacitive loading on those outputs See
Figures 5 and 6 for
the switching time variations
3
Switching Test Circuits
TL F 5219 3
C
L
INCLUDES PROBE AND JIG CAPACITANCES
FIGURE 1 Capacitive Load Switching
TL F 5219 4
FIGURE 2 TRI-STATE Enable Disable
Typical Switching Characteristics
Voltage Waveforms
TL F 5219 5
FIGURE 3 Output Drive Levels
TL F 5219 6
FIGURE 4 TRI-STATE Control Levels
TL F 5219 7
FIGURE 5 t
PLH
Measured to 2 7V on Output vs C
L
TL F 5219 8
FIGURE 6 t
PHL
Measured to 0 8V on Output vs C
L
4
Typical Switching Characteristics
(Continued)
TL F 5219 9
FIGURE 7 Typical Power Dissipation for DP84240 at
V
CC
e
5 5V (All 8 drivers switching simultaneously)
TL F 5219 10
FIGURE 8 Typical Power Dissipation for DP84244 at
V
CC
e
5 5V (All 8 drivers switching simultaneously)
Typical Application
DP84244 used as a buffer in a large memory array (greater than 88 dynamic RAMs)
TL F 5219 11
5