DS90LV011A
3V LVDS Single High Speed Differential Driver
General Description
The DS90LV011A is a single LVDS driver device optimized
for high data rate and low power applications. The
DS90LV011A is a current mode driver allowing power dissi-
pation to remain low even at high frequency. In addition, the
short circuit fault current is also minimized. The device is
designed to support data rates in excess of 400Mbps
(200MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The device is in both a 5-lead small outline transistor pack-
age and a new LLP-8 package with a 3mm x 3mm body size.
The LVDS outputs have been arranged for easy PCB layout.
The differential driver outputs provide low EMI with its typical
low output swing of 350 mV. The DS90LV011A can be paired
with its companion single line receiver, the DS90LV012A, or
with any of National's LVDS receivers, to provide a high-
speed LVDS interface.
Features
n
Conforms to TIA/EIA-644-A Standard
n
>
400Mbps (200MHz) switching rates
n
700 ps (100 ps typical) maximum differential skew
n
1.5 ns maximum propagation delay
n
Single 3.3V power supply
n
350 mV differential signaling
n
Power Off Protection (outputs in TRI-STATE)
n
Pinout simplifies PCB layout
n
Low power dissipation (23 mW
@
3.3V typical)
n
SOT-23 5-lead package
n
Leadless LLP-8 package (3x3 mm body size)
n
SOT-23 version pin compatible with SN65LVDS1
n
Fabricated with advanced CMOS process technology
n
Industrial temperature operating range
(-40C to +85C)
Connection Diagrams
20014922
(Top View)
Order Number DS90LV011ATMF
See NS Package Number MF05A
20014923
(Top View)
Order Number DS90LV011ATLD
See NS Package Number LDA08A
Functional Diagram
20014902
May 2002
DS90L
V01
1A
3V
L
VDS
Single
High
Speed
Differential
Driver
2002 National Semiconductor Corporation
DS200149
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
DD
)
-0.3V to +4V
LVCMOS input voltage (TTL IN)
-0.3V to +3.6V
LVDS output voltage (OUT
)
-0.3V to +3.9V
LVDS output short circuit current
24mA
Maximum Package Power Dissipation
@
+25C
LDA Package
2.26 W
Derate LDA Package
18.1 mW/C above +25C
Thermal resistance (
JA
)
55.3C/Watt
MF Package
902 mW
Derate MF Package
7.22 mW/C above +25C
Thermal resistance (
JA
)
138.5C/Watt
Storage Temperature
-65C to +150C
Lead Temperature Range Soldering
(4 sec.)
+260C
Maximum Junction
Temperature
+150C
ESD Ratings
HBM (1.5 k
, 100 pF)
9kV
EIAJ (0
, 200 pF)
900V
CDM (0
, 0 pF)
2000V
IEC direct (330
, 150 pF)
4kV
Recommended Operating
Conditions
Min
Typ
Max
Units
Supply Voltage (V
DD
)
3.0
3.3
3.6
V
Temperature (T
A
)
-40
+25
+85
C
Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3, 8)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
|V
OD
|
Output Differential Voltage
R
L
= 100
(Figure 1 and Figure 2)
OUT+,
OUT-
250
350
450
mV
V
OD
V
OD
Magnitude Change
3
35
mV
V
OS
Offset Voltage
R
L
= 100
(Figure 1)
1.125
1.22
1.375
V
V
OS
Offset Magnitude Change
0
1
25
mV
I
OFF
Power-off Leakage
V
OUT
= 3.6V or GND, V
DD
= 0V
1
10
A
I
OS
Output Short Circuit Current
(Note 4)
V
OUT+
and V
OUT-
= 0V
-6
-24
mA
I
OSD
Differential Output Short Circuit
Current (Note 4)
V
OD
= 0V
-5
-12
mA
C
OUT
Output Capacitance
3
pF
V
IH
Input High Voltage
TTL IN
2.0
V
DD
V
V
IL
Input Low Voltage
GND
0.8
V
I
IH
Input High Current
V
IN
= 3.3V or 2.4V
2
10
A
I
IL
Input Low Current
V
IN
= GND or 0.5V
1
10
A
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-1.5
-0.6
V
C
IN
Input Capacitance
3
pF
I
DD
Power Supply Current
No Load
V
IN
= V
DD
or GND
V
DD
5
8
mA
R
L
= 100
7
10
mA
Switching Characteristics
Over Supply Voltage and Operating Temperature Ranges, unless otherwise specified. (Notes 3, 5, 6, 7)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHLD
Differential Propagation Delay High to Low
R
L
= 100
, C
L
= 15 pF
0.3
1.0
1.5
ns
t
PLHD
Differential Propagation Delay Low to High
(Figure 3 and Figure 4)
0.3
1.1
1.5
ns
t
SKD1
Differential Pulse Skew |t
PHLD
- t
PLHD
| (Note 9)
0
0.1
0.7
ns
t
SKD3
Differential Part to Part Skew (Note 10)
0
0.2
1.0
ns
t
SKD4
Differential Part to Part Skew (Note 11)
0
0.4
1.2
ns
t
TLH
Transition Low to High Time
0.2
0.5
1.0
ns
t
THL
Transition High to Low Time
0.2
0.5
1.0
ns
f
MAX
Maximum Operating Frequency (Note 12)
200
250
MHz
DS90L
V01
1A
www.national.com
2
Switching Characteristics
(Continued)
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V
OD
.
Note 3: All typicals are given for: V
DD
= +3.3V and T
A
= +25C.
Note 4: Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
Note 5: These parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage,
temperature) ranges.
Note 6: C
L
includes probe and fixture capacitance.
Note 7: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50
, t
r
1 ns, t
f
1 ns (10%-90%).
Note 8: The DS90LV011A is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers outputs.
Note 9: t
SKD1
, |t
PHLD
- t
PLHD
|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel.
Note 10: t
SKD3
, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same V
DD
and within 5C of each other within the operating temperature range.
Note 11: t
SKD4
, part to part skew, is the differential channel to channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max - Min| differential propagation delay.
Note 12: f
MAX
generator input conditions: t
r
= t
f
<
1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output criteria: duty cycle = 45%/55%, V
OD
>
250mV. The
parameter is guaranteed by design. The limit is based on the statistical analysis of the device over the PVT range by the transitions times (t
TLH
and t
THL
).
Parameter Measurement Information
20014903
FIGURE 1. Differential Driver DC Test Circuit
20014924
FIGURE 2. Differential Driver Full Load DC Test Circuit
20014904
FIGURE 3. Differential Driver Propagation Delay and Transition Time Test Circuit
DS90L
V01
1A
www.national.com
3
Parameter Measurement Information
(Continued)
Application Information
TABLE 1. Device Pin Descriptions
Package Pin Number
Pin Name
Description
SOT23
LLP
5
8
TTL IN
LVTTL/LVCMOS driver input pins
4
1
OUT+
Non-inverting driver output pin
3
3
OUT-
Inverting driver output pin
2
7
GND
Ground pin
1
6
V
DD
Power supply pin, +3.3V
0.3V
2, 4, 5
NC
No connect
PC Board Considerations:
For PC board considerations for the LLP package, please
refer to application note AN-1187 "Leadless Leadframe
Package." It is important to note that to optimize signal
integrity (minimize jitter and noise coupling), the LLP thermal
land pad, which is a metal (normally copper) rectangular
region located under the package, should be attached to
ground and match the dimensions of the exposed pad on the
PCB (1:1 ratio).
20014905
FIGURE 4. Differential Driver Propagation Delay and Transition Time Waveforms
DS90L
V01
1A
www.national.com
4
Physical Dimensions
inches (millimeters)
unless otherwise noted
5-Lead SOT23, JEDEC MO-178, 1.6mm
Order Number DS90LV011ATMF
NS Package Number MF05A
DS90L
V01
1A
www.national.com
5
PDF 
ZIP