DS90LV047A
3V LVDS Quad CMOS Differential Line Driver
General Description
The DS90LV047A is a quad CMOS flow-through differential
line driver designed for applications requiring ultra low power
dissipation and high data rates. The device is designed to
support data rates in excess of 400 Mbps (200 MHz) utilizing
Low Voltage Differential Signaling (LVDS) technology.
The DS90LV047A accepts low voltage TTL/CMOS input lev-
els and translates them to low voltage (350 mV) differential
output signals. In addition, the driver supports a TRI-STATE
function that may be used to disable the output stage, dis-
abling the load current, and thus dropping the device to an
ultra low idle power state of 13 mW typical. The
DS90LV047A has a flow-through pinout for easy PCB layout.
The EN and EN* inputs are ANDed together and control the
TRI-STATE outputs. The enables are common to all four
drivers. The DS90LV047A and companion line receiver
(DS90LV048A) provide a new alternative to high power
psuedo-ECL devices for high speed point-to-point interface
applications.
Features
n
>
400 Mbps (200 MHz) switching rates
n
Flow-through pinout simplifies PCB layout
n
300 ps typical differential skew
n
400 ps maximum differential skew
n
1.7 ns maximum propagation delay
n
3.3V power supply design
n
350 mV differential signaling
n
Low power dissipation (13mW at 3.3V static)
n
Interoperable with existing 5V LVDS receivers
n
High impedance on LVDS outputs on power down
n
Conforms to TIA/EIA-644 LVDS Standard
n
Industrial operating temperature range (-40C to +85C)
n
Available in surface mount (SOIC) and low profile
TSSOP package
Connection Diagram
Functional Diagram
Truth Table
ENABLES
INPUT
OUTPUTS
EN
EN
*
D
IN
D
OUT+
D
OUT-
H
L or Open
L
L
H
H
H
L
All other combinations of ENABLE inputs
X
Z
Z
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
Dual-In-Line
DS100887-1
Order Number DS90LV047ATM, DS90LV047ATMTC
See NS Package Number M16A, MTC16
DS100887-2
July 1999
DS90L
V047A
3V
L
VDS
Quad
CMOS
Differential
Line
Driver
1999 National Semiconductor Corporation
DS100887
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.3V to +4V
Input Voltage (D
IN
)
-0.3V to (V
CC
+ 0.3V)
Enable Input Voltage (EN, EN
*
)
-0.3V to (V
CC
+ 0.3V)
Output Voltage (D
OUT+
, D
OUT-
)
-0.3V to +3.9V
Short Circuit Duration
(D
OUT+
, D
OUT-
)
Continuous
Maximum Package Power Dissipation
@
+25C
M Package
1088 mW
MTC Package
866 mW
Derate M Package
8.5 mW/C above +25C
Derate MTC Package
6.9 mW/C above +25C
Storage Temperature Range
-65C to +150C
Lead Temperature Range
Soldering (4 sec.)
+260C
Maximum Junction Temperature
+150C
ESD Rating (Note 10)
(HBM, 1.5 k
, 100 pF)
10 kV
(EIAJ, 0
, 200 pF)
1200 V
Recommended Operating
Conditions
Min
Typ
Max
Units
Supply Voltage (V
CC
)
+3.0
+3.3
+3.6
V
Operating Free Air
Temperature (T
A
)
-40
+25
+85
C
Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 2, 3, 4)
Symbol
Parameter
Conditions
Pin
Min
Typ
Max
Units
V
OD1
Differential Output Voltage
R
L
= 100
(
Figure 1)
D
OUT-
D
OUT+
250
310
450
mV
V
OD1
Change in Magnitude of V
OD1
for Complementary Output
States
1
35
|mV|
V
OS
Offset Voltage
1.125
1.17
1.375
V
V
OS
Change in Magnitude of V
OS
for
Complementary Output States
1
25
|mV|
V
OH
Output High Voltage
1.33
1.6
V
V
OL
Output Low Voltage
0.90
1.02
V
V
IH
Input High Voltage
D
IN
,
EN,
EN*
2.0
V
CC
V
V
IL
Input Low Voltage
GND
0.8
V
I
IH
Input High Current
V
IN
= V
CC
or 2.5V
-10
2
+10
A
I
IL
Input Low Current
V
IN
= GND or 0.4V
-10
-2
+10
A
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-1.5
-0.8
V
I
OS
Output Short Circuit Current
(Note 11)
ENABLED,
D
IN
= V
CC
, D
OUT+
= 0V or
D
IN
= GND, D
OUT-
= 0V
D
OUT-
D
OUT+
-4.2
-9.0
mA
I
OSD
Differential Output Short Circuit
Current (Note 11)
ENABLED, V
OD
= 0V
-4.2
-9.0
mA
I
OFF
Power-off Leakage
V
OUT
= 0V or 3.6V, V
CC
= 0V
or Open
-20
1
+20
A
I
OZ
Output TRI-STATE Current
EN = 0.8V and EN* = 2.0V
V
OUT
= 0V or V
CC
-10
1
+10
A
I
CC
No Load Supply current Drivers
Enabled
D
IN
= V
CC
or GND
V
CC
4.0
8.0
mA
I
CCL
Loaded Supply Current Drivers
Enabled
R
L
= 100
All Channels, D
IN
=
V
CC
or GND (all inputs)
20
30
mA
I
CCZ
No Load Supply Current Drivers
Disabled
D
IN
= V
CC
or GND, EN =
GND, EN* = V
CC
2.2
6.0
mA
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2
Switching Characteristics
V
CC
= +3.3V
10%, T
A
= -40C to +85C (Notes 3, 9, 12)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
PHLD
Differential Propagation Delay High to Low
R
L
= 100
, C
L
= 15 pF
(
Figure 2 and Figure 3)
0.5
0.9
1.7
ns
t
PLHD
Differential Propagation Delay Low to High
0.5
1.2
1.7
ns
t
SKD1
Differential Pulse Skew |t
PHLD
- t
PLHD
|
(Note 5)
0
0.3
0.4
ns
t
SKD2
Channel-to-Channel Skew (Note 6)
0
0.4
0.5
ns
t
SKD3
Differential Part to Part Skew (Note 7)
0
1.0
ns
t
SKD4
Differential Part to Part Skew (Note 8)
0
1.2
ns
t
TLH
Rise Time
0.5
1.5
ns
t
THL
Fall Time
0.5
1.5
ns
t
PHZ
Disable Time High to Z
R
L
= 100
, C
L
= 15 pF
(
Figure 4 and Figure 5)
2
5
ns
t
PLZ
Disable Time Low to Z
2
5
ns
t
PZH
Enable Time Z to High
3
7
ns
t
PZL
Enable Time Z to Low
3
7
ns
f
MAX
Maximum Operating Frequency (Note 14)
200
250
MHz
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except: V
OD1
and
V
OD1
.
Note 3: All typicals are given for: V
CC
= +3.3V, T
A
= +25C.
Note 4: The DS90LV047A is a current mode device and only functions within datasheet specifications when a resistive load is applied to the driver outputs typical
range is (90
to 110
).
Note 5: t
SKD1
|t
PHLD
- t
PLHD
| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
Note 6: t
SKD2
is the Differential Channel-to-Channel Skew of any event on the same device.
Note 7: t
SKD3
, Differential Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This speci-
fication applies to devices at the same V
CC
and within 5C of each other within the operating temperature range.
Note 8: t
SKD4
, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperature and voltage ranges, and across process distribution. t
SKD4
is defined as |Max - Min| differential propagation delay.
Note 9: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
O
= 50
, t
r
1 ns, and t
f
1 ns.
Note 10: ESD Ratings:
HBM (1.5 k
, 100 pF)
10 kV
EIAJ (0
, 200 pF)
1200 V
Note 11: Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
Note 12: C
L
includes probe and jig capacitance.
Note 13: All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
Note 14: f
MAX
generator input conditions: t
r
= t
f
<
1 ns (0% to 100%), 50% duty cycle, 0V to 3V. Output Criteria: duty cycle = 45%/55%, VOD
>
250mV, all channels
switching.
Parameter Measurement Information
DS100887-3
FIGURE 1. Driver V
OD
and V
OS
Test Circuit
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3
Parameter Measurement Information
(Continued)
DS100887-4
FIGURE 2. Driver Propagation Delay and Transition Time Test Circuit
DS100887-5
FIGURE 3. Driver Propagation Delay and Transition Time Waveforms
DS100887-6
FIGURE 4. Driver TRI-STATE Delay Test Circuit
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4
Parameter Measurement Information
(Continued)
Typical Application
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner's Manual (lit #550062-001), AN808,
AN977, AN971, AN916, AN805, AN903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in
Figure 6. This configuration provides a clean signaling en-
vironment for the fast edge rates of the drivers. The receiver
is connected to the driver through a balanced media which
may be a standard twisted pair cable, a parallel pair cable, or
simply PCB traces. Typically, the characteristic differential
impedance of the media is in the range of 100
. A termina-
tion resistor of 100
(selected to match the media), and is lo-
cated as close to the receiver input pins as possible. The ter-
mination resistor converts the driver output current (current
mode) into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu-
ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.
The DS90LV047A differential line driver is a balanced cur-
rent source design. A current mode driver, generally speak-
ing has a high output impedance and supplies a constant
current for a range of loads (a voltage mode driver on the
other hand supplies a constant voltage for a range of loads).
Current is switched through the load in one direction to pro-
duce a logic state and in the other direction to produce the
other logic state. The output current is typically 3.1 mA, a
minimum of 2.5 mA, and a maximum of 4.5 mA. The current
mode driver requires (as discussed above) that a resistive
termination be employed to terminate the signal and to com-
plete the loop as shown in
Figure 6. AC or unterminated con-
figurations are not allowed. The 3.1 mA loop current will de-
velop a differential voltage of 310mV across the 100
termination resistor which the receiver detects with a 250mV
minimum differential noise margin, (driven signal minus re-
ceiver threshold (250mV 100mV = 150mV)). The signal is
centered around +1.2V (Driver Offset, V
OS
) with respect to
ground as shown in
Figure 7. Note that the steady-state volt-
age (V
SS
) peak-to-peak swing is twice the differential voltage
(V
OD
) and is typically 620mV.
The current mode driver provides substantial benefits over
voltage mode drivers, such as an RS-422 driver. Its quies-
cent current remains relatively flat versus switching fre-
quency. Whereas the RS-422 voltage mode driver increases
exponentially in most case between 20 MHz50 MHz. This
is due to the overlap current that flows between the rails of
the device when the internal gates switch. Whereas the cur-
rent mode driver switches a fixed current between its output
without any substantial overlap current. This is similar to
some ECL and PECL devices, but without the heavy static
I
CC
requirements of the ECL/PECL designs. LVDS requires
>
80% less current than similar PECL devices. AC specifica-
tions for the driver are a tenfold improvement over other ex-
isting RS-422 drivers.
DS100887-7
FIGURE 5. Driver TRI-STATE Delay Waveform
DS100887-8
FIGURE 6. Point-to-Point Application
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