TL DD 9682
HPC3616446164
HPC3610446104
High-Performance
microController
with
AD
January 1993
HPC36164 46164 HPC36104 46104
High-Performance microController with A D
General Description
The HPC46164 and HPC46104 are members of the HPC
TM
family of High Performance microControllers Each member
of the family has the same core CPU with a unique memory
and I O configuration to suit specific applications The
HPC46164 has 16k bytes of on-chip ROM The HPC46104
has no on-chip ROM and is intended for use with external
memory Each part is fabricated in National's advanced
microCMOS technology This process combined with an ad-
vanced architecture provides fast flexible I O control effi-
cient data manipulation and high speed computation
The HPC devices are complete microcomputers on a single
chip All system timing internal logic ROM RAM and I O
are provided on the chip to produce a cost effective solution
for high performance applications On-chip functions such
as UART up to eight 16-bit timers with 4 input capture regis-
ters vectored interrupts WATCHDOG
TM
logic and MICRO-
WIRE PLUS
TM
provide a high level of system integration
The ability to address up to 64k bytes of external memory
enables the HPC to be used in powerful applications typical-
ly performed by microprocessors and expensive peripheral
chips The term ``HPC46164'' is used throughout this data-
sheet to refer to the HPC46164 and HPC46104 devices un-
less otherwise specified
The HPC46164 and HPC46104 have as an on-board pe-
ripheral an 8-channel 8-bit Analog-to-Digital Converter This
A D converter can operate in a single-ended mode where
the analog input voltage is applied across one of the eight
input channels (D0 D7) and AGND The A D converter can
also operate in differential mode where the analog input
voltage is applied across two adjacent input channels The
A D converter will convert up to eight channels in single-
ended mode and up to four channel pairs in differential
mode
The microCMOS process results in very low current drain
and enables the user to select the optimum speed power
product for his system The IDLE and HALT modes provide
further current savings The HPC is available only in an
80-pin PQFP package
Features
Y
HPC family
core features
16-bit architecture both byte and word
16-bit data bus ALU and registers
64k bytes of external direct memory addressing
FAST
200 ns for fastest instruction when using
20 0 MHz clock 134 ns at 30 0 MHz
High code efficiency
most instructions are single
byte
16 x 16 multiply and 32 x 16 divide
Eight vectored interrupt sources
Four 16-bit timer counters with 4 synchronous out-
puts and WATCHDOG logic
MICROWIRE PLUS serial I O interface
CMOS
very low power with two power save modes
IDLE and HALT
Y
A D
8-channel 8-bit analog-to-digital converter with
g
LSB non-linearity
Y
UART
full duplex programmable baud rate
Y
Four additional 16-bit timer counters with pulse width
modulated outputs
Y
Four input capture registers
Y
52 general purpose I O lines (memory mapped)
Y
16k bytes of ROM 512 bytes of RAM on-chip
Y
ROMless version available (HPC46104)
Y
Commercial (0 C to
a
70 C) and industrial (
b
40 C to
a
85 C) temperature ranges
Block Diagram
(HPC46164 with 16k ROM shown)
TL DD 9682 1
Series 32000
and TRI-STATE
are registered trademarks of National Semiconductor Corporation
MOLE
TM
HPC
TM
COPS
TM
microcontrollers WATCHDOG
TM
and MICROWIRE PLUS
TM
are trademarks of National Semiconductor Corporation
PC-AT
is a registered trademark of International Business Machines Corp
SunOS
TM
is a trademark of Sun Microsystems
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Total Allowable Source or Sink Current
100 mA
Storage Temperature Range
b
65 C to
a
150 C
Lead Temperature (Soldering 10 sec )
300 C
V
CC
with Respect to GND
b
0 5V to 7 0V
All Other Pins
(V
CC
a
0 5)V to (GND
b
0 5)V
Note
Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics
V
CC
e
5 0V
g
10% unless otherwise specified T
A
e
0 C to
a
70 C for HPC46164 HPC46104
b
40 C to
a
85 C for
HPC36164 HPC36104
Symbol
Parameter
Test Conditions
Min
Max
Units
I
CC1
Supply Current
V
CC
e
5 5V f
in
e
30 MHz (Note 1)
65
mA
V
CC
e
5 5V f
in
e
20 MHz (Note 1)
47
mA
V
CC
e
5 5V f
in
e
2 0 MHz (Note 1)
10
mA
I
CC2
IDLE Mode Current
V
CC
e
5 5V f
in
e
30 MHz (Note 1)
5
mA
V
CC
e
5 5V f
in
e
20 MHz (Note 1)
3
mA
V
CC
e
5 5V f
in
e
2 0 MHz (Note 1)
1
mA
I
CC3
HALT Mode Current
V
CC
e
5 5V f
in
e
0 kHz (Note 1)
300
m
A
V
CC
e
2 5V f
in
e
0 kHz (Note 1)
100
m
A
INPUT VOLTAGE LEVELS FOR SCHMITT TRIGGERED INPUTS RESET NMI WO AND ALSO CKI
V
IH1
Logic High
0 9 V
CC
V
V
IL1
Logic Low
0 1 V
CC
V
ALL OTHER INPUTS
V
IH2
Logic High (except Port D)
0 7 V
CC
V
V
IL2
Logic Low (except Port D)
0 2 V
CC
V
V
IH3
Logic High (Port D Only)
(Note 9 in AC Characteristics)
0 7 V
CC
V
V
IL3
Logic Low (Port D Only)
(Note 9 in AC Characteristics)
0 2 V
CC
V
I
LI1
Input Leakage Current
V
IN
e
0 and V
IN
e
V
CC
g
2
m
A
I
LI2
Input Leakage Current RDY HLD EXUI
V
IN
e
0
b
3
b
50
m
A
I
LI3
Input Leakage Current B12
RESET
e
0 V
IN
e
V
CC
0 5
7
m
A
C
I
Input Capacitance
(Note 2)
10
pF
C
IO
I O Capacitance
(Note 2)
20
pF
OUTPUT VOLTAGE LEVELS
V
OH1
Logic High (CMOS)
I
OH
e b
10 mA (Note 2)
V
CC
b
0 1
V
V
OL1
Logic Low (CMOS)
I
OH
e
10 mA (Note 2)
0 1
V
V
OH2
Port A B Drive CK2
I
OH
e b
7 mA
2 4
V
V
OL2
(A
0
A
15
B
10
B
11
B
12
B
15
)
I
OL
e
3 mA
0 4
V
V
OH3
Other Port Pin Drive WO (open
I
OH
e b
1 6 mA (except WO)
2 4
V
V
OL3
drain) (B
0
B
9
B
13
B
14
P
0
P
3
)
I
OL
e
0 5 mA
0 4
V
V
OH4
ST1 and ST2 Drive
I
OH
e b
6 mA
2 4
V
V
OL4
I
OL
e
1 6 mA
0 4
V
V
OH5
Port A B Drive (A
0
A
15
B
10
B
11
B
12
B
15
) When
I
OH
e b
1 mA
2 4
V
Used as External Address Data Bus
V
OL5
I
OL
e
3 mA
0 4
V
V
RAM
RAM Keep-Alive Voltage
(Note 3)
2 5
V
CC
V
I
OZ
TRI-STATE Leakage Current
V
IN
e
0 and V
IN
e
V
CC
g
5
m
A
Note 1
I
CC1
I
CC2
I
CC3
measured with no external drive (I
OH
and I
OL
e
0 I
IH
and I
IL
e
0) I
CC1
is measured with RESET
e
GND I
CC3
is measured with NMI
e
V
CC
and A D inactive CKI driven to V
IH1
and V
IL1
with rise and fall times less than 10 ns V
REF
e
AGND
e
GND
Note 2
This is guaranteed by design and not tested
Note 3
Test duration is 100 ms
2
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 through Figure 5 ) V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for HPC46164 and
b
40 C to
a
85 C for HPC36164
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
C
CKI Operating Frequency
2
20
MHz
t
C1
e
1 f
C
CKI Clock Period
50
500
ns
t
CKIH
CKI High Time
22 5
ns
t
CKIL
CKI Low Time
22 5
ns
t
C
e
2 f
C
CPU Timing Cycle
100
ns
t
WAIT
e
t
C
CPU Wait State Period
100
ns
t
DC1C2R
Delay of CK2 Rising Edge after CKI Falling Edge
0
55
ns
(Note 2)
t
DC1C2F
Delay of CK2 Falling Edge after CKI Falling Edge
0
55
ns
(Note 2)
f
U
e
f
C
8
External UART Clock Input Frequency
2 5
MHz
f
MW
External MICROWIRE PLUS Clock Input Frequency
1 25
MHz
f
XIN
e
f
C
22
External Timer Input Frequency
0 91
MHz
t
XIN
e
t
C
Pulse Width for Timer Inputs
100
ns
t
UWS
MICROWIRE Setup Time
Master
100
ns
Slave
20
t
UWH
MICROWIRE Hold Time
Master
20
ns
Slave
50
t
UWV
MICROWIRE Output Valid Time
Master
50
ns
Slave
150
t
SALE
e
t
C
a
40
HLD Falling Edge before ALE Rising Edge
115
ns
t
HWP
e
t
C
a
10
HLD Pulse Width
110
ns
t
HAE
e
t
C
a
100
HLDA Falling Edge after HLD Falling Edge
200
ns
(Note 3)
t
HAD
e
t
C
a
85
HLDA Rising Edge after HLD Rising Edge
160
ns
t
BF
e
t
C
a
66
Bus Float after HLDA Falling Edge
116
ns
(Note 5)
t
BE
e
t
C
a
66
Bus Enable after HLDA Rising Edge
116
ns
(Note 5)
t
UAS
Address Setup Time to Falling Edge of URD
10
ns
t
UAH
Address Hold Time from Rising Edge of URD
10
ns
t
RPW
URD Pulse Width
100
ns
t
OE
URD Falling Edge to Output Data Valid
0
60
ns
t
OD
Rising Edge of URD to Output Data Invalid
5
35
ns
(Note 6)
t
DRDY
RDRDY Delay from Rising Edge of URD
70
ns
t
WDW
UWR Pulse Width
40
ns
t
UDS
Input Data Valid before Rising Edge of UWR
10
ns
t
UDH
Input Data Hold after Rising Edge of UWR
20
ns
t
A
WRRDY Delay from Rising Edge of UWR
70
ns
Clocks
Timers
MICROWIREPLUS
External
Hold
UPI
Timing
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock
3
20 MHz
(Continued)
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 through Figure 5 ) V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for HPC46164 and
b
40 C to
a
85 C for HPC36164
Symbol and Formula
Parameter
Min
Max
Units
Notes
t
DC1ALER
Delay from CKI Rising Edge to
0
35
ns
(Notes 1 2)
ALE Rising Edge
t
DC1ALEF
Delay from CKI Rising Edge to
0
35
ns
(Notes 1 2)
ALE Falling Edge
t
DC2ALER
e
t
C
a
20
Delay from CK2 Rising Edge to
45
ns
(Note 2)
ALE Rising Edge
t
DC2ALEF
e
t
C
a
20
Delay from CK2 Falling Edge to
45
ns
(Note 2)
ALE Falling Edge
t
LL
e
t
C
b
9
ALE Pulse Width
41
ns
t
ST
e
t
C
b
7
Setup of Address Valid before
18
ns
ALE Falling Edge
t
VP
e
t
C
b
5
Hold of Address Valid after
20
ns
ALE Falling Edge
t
ARR
e
t
C
b
5
ALE Falling Edge to RD Falling Edge
20
ns
t
ACC
e
t
C
a
WS
b
55
Data Input Valid after Address Output Valid
145
ns
(Note 6)
t
RD
e
t
C
a
WS
b
65
Data Input Valid after RD Falling Edge
85
ns
t
RW
e
t
C
a
WS
b
10
RD Pulse Width
140
ns
t
DR
e
t
C
b
15
Hold of Data Input Valid after
0
60
ns
RD Rising Edge
t
RDA
e
t
C
b
15
Bus Enable after RD Rising Edge
85
ns
t
ARW
e
t
C
b
5
ALE Falling Edge to WR Falling Edge
45
ns
t
WW
e
t
C
a
WS
b
15
WR Pulse Width
160
ns
t
V
e
t
C
a
WS
b
5
Data Output Valid before WR Rising Edge
145
ns
t
HW
e
t
C
b
5
Hold of Data Valid after WR Rising Edge
20
ns
t
DAR
e
t
C
a
WS
b
50
Falling Edge of ALE to
75
ns
Falling Edge of RDY
t
RWP
e
t
C
RDY Pulse Width
100
ns
Address
Cycles
Read
Cycles
Write
Cycles
Ready
Input
Note
C
L
e
40 pF
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
CKIR
and t
CKIL
) on CKI input less than 2 5 ns
Note 2
Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
t
HAE
is spec'd for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
edge occurs later t
HAE
may be as long as (3 t
C
a
4WS
a
72 t
C
a
100) may occur depending on the following CPU instruction cycles its wait states and ready
input
Note 4
WS (t
WAIT
)
c
(number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency t
C
e
20 MHz with
one wait state programmed
Note 5
Due to emulation restrictions
actual limits will be better
Note 6
This is guaranteed by design and not tested
4
A D Converter Specifications
V
CC
e
5V
g
10% (V
SS
b
0 05V)
s
Any Input
s
(V
CC
a
0 05V) f
C
e
20 MHz and Prescalar
e
f
C
12
Parameter
Conditions
Min
Typ
Max
Units
Resolution
8
Bits
Reference Voltage Input
AGND
e
0V
3
V
CC
V
Absolute Accuracy
V
CC
e
5 5V V
REF
e
5V
V
CC
e
5V V
REF
e
5V and
g
2
LSB
V
CC
e
4 5V V
REF
e
4 5V
Non-Linearity
V
CC
e
5 5V V
REF
e
5V
V
CC
e
5V V
REF
e
5V and
g
LSB
V
CC
e
4 5V V
REF
e
4 5V
Differential Non-Linearity
V
CC
e
5 5V V
REF
e
5V
V
CC
e
5V V
REF
e
5V and
g
LSB
V
CC
e
4 5V V
REF
e
4 5V
Input Reference Resistance
1 6
4 8
kX
Common Mode Input Range (Note 9)
AGND
V
REF
V
DC Common Mode Error
g
LSB
Off Channel Leakage Current
g
2
m
A
On Channel Leakage Current
g
2
m
A
A D Clock Frequency (Note 8)
0 1
1 67
MHz
Conversion Time (Note 7)
12 5
A D Clock Cycles
Note 7
Conversion Time includes sample and hold time See following diagrams
Note 8
See Prescalar description
Note 9
For V
IN(
b
)
l
V
IN(
a
)
the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input The diodes will forward conduct for analog
input voltages below ground or above the V
CC
supply Be careful during testing at low V
CC
levels (4 5V) as high level analog inputs (5 0V) can cause this input
diode to conduct
especially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This
means that as long as the analog V
IN
does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 V
DC
to
5 0V
DC
input voltage range will therefore require a minimum supply voltage of 4 950 V
DC
over temperature variations initial tolerance and loading
Timing Diagram
TL DD 9682 11
Note
The trigger condition generated by the start conversion method selected by the SC bits requires one CK2 to propagate through before the trigger condition is
known Once the trigger condition is known the sample and hold will start at the next rising edge of ADCLK The figure shows worst case
5
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 through Figure 5 ) V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for HPC46164 HPC46104
b
55 C
to
a
125 C for HPC16164 HPC16104
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
C
CKI Operating Frequency
2
30
MHz
t
C1
e
1 f
C
CKI Clock Period
33
500
ns
t
CKIH
CKI High Time
15
ns
t
CKIL
CKI Low Time
16 6
ns
t
C
e
2 f
C
CPU Timing Cycle
66
ns
t
WAIT
e
t
C
CPU Wait State Period
66
ns
t
DC1C2R
Delay of CK2 Rising Edge after CKI Falling Edge
0
55
ns
(Note 2)
t
DC1C2F
Delay of CK2 Falling Edge after CKI Falling Edge
0
55
ns
(Note 2)
f
U
e
f
C
8
External UART Clock Input Frequency
3 75
MHz
f
MW
External MICROWIRE PLUS Clock Input Frequency
1 875
MHz
f
XIN
e
f
C
22
External Timer Input Frequency
1 36
MHz
t
XIN
e
t
C
Pulse Width for Timer Inputs
66
ns
t
UWS
MICROWIRE Setup Time
Master
100
ns
Slave
20
t
UWH
MICROWIRE Hold Time
Master
20
ns
Slave
50
t
UWV
MICROWIRE Output Valid Time
Master
50
ns
Slave
150
t
SALE
e
t
C
a
40
HLD Falling Edge before ALE Rising Edge
90
ns
t
HWP
e
t
C
a
10
HLD Pulse Width
76
ns
t
HAE
e
t
C
a
85
HLDA Falling Edge after HLD Falling Edge
151
ns
(Note 3)
t
HAD
e
t
C
a
85
HLDA Rising Edge after HLD Rising Edge
135
ns
t
BF
e
t
C
a
66
Bus Float after HLDA Falling Edge
99
ns
(Note 5)
t
BE
e
t
C
a
66
Bus Enable after HLDA Rising Edge
99
ns
(Note 5)
t
UAS
Address Setup Time to Falling Edge of URD
10
ns
t
UAH
Address Hold Time from Rising Edge of URD
10
ns
t
RPW
URD Pulse Width
100
ns
t
OE
URD Falling Edge to Output Data Valid
0
60
ns
t
OD
Rising Edge of URD to Output Data Invalid
5
35
ns
(Note 6)
t
DRDY
RDRDY Delay from Rising Edge of URD
70
ns
t
WDW
UWR Pulse Width
40
ns
t
UDS
Input Data Valid before Rising Edge of UWR
10
ns
t
UDH
Input Data Hold after Rising Edge of UWR
20
ns
t
A
WRRDY Delay from Rising Edge of UWR
70
ns
Clocks
Timers
MICROWIREPLUS
External
Hold
UPI
Timing
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock
6
30 MHz
(Continued)
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 through Figure 5 ) V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for HPC46164 HPC46104
b
55 C
to
a
125 C for HPC16164 HPC16104
Symbol and Formula
Parameter
Min
Max
Units
Notes
t
DC1ALER
Delay from CKI Rising Edge to
0
35
ns
(Notes 1 2)
ALE Rising Edge
t
DC1ALEF
Delay from CKI Rising Edge to
0
35
ns
(Notes 1 2)
ALE Falling Edge
t
DC2ALER
e
t
C
a
20
Delay from CK2 Rising Edge to
37
ns
(Note 2)
ALE Rising Edge
t
DC2ALEF
e
t
C
a
20
Delay from CK2 Falling Edge to
37
ns
(Note 2)
ALE Falling Edge
t
LL
e
t
C
b
9
ALE Pulse Width
24
ns
t
ST
e
t
C
b
7
Setup of Address Valid before
9
ns
ALE Falling Edge
t
VP
e
t
C
b
5
Hold of Address Valid after
11
ns
ALE Falling Edge
t
ARR
e
t
C
b
5
ALE Falling Edge to RD Falling Edge
11
ns
t
ACC
e
t
C
a
WS
b
32
Data Input Valid after Address Output Valid
100
ns
(Note 6)
t
RD
e
t
C
a
WS
b
39
Data Input Valid after RD Falling Edge
60
ns
t
RW
e
t
C
a
WS
b
14
RD Pulse Width
85
ns
t
DR
e
t
C
b
15
Hold of Data Input Valid after
0
35
ns
RD Rising Edge
t
RDA
e
t
C
b
15
Bus Enable after RD Rising Edge
51
ns
t
ARW
e
t
C
b
5
ALE Falling Edge to WR Falling Edge
28
ns
t
WW
e
t
C
a
WS
b
15
WR Pulse Width
101
ns
t
V
e
t
C
a
WS
b
5
Data Output Valid before WR Rising Edge
94
ns
t
HW
e
t
C
b
10
Hold of Data Valid after WR Rising Edge
7
ns
t
DAR
e
t
C
a
WS
b
50
Falling Edge of ALE to
33
ns
Falling Edge of RDY
t
RWP
e
t
C
RDY Pulse Width
66
ns
Address
Cycles
Read
Cycles
Write
Cycles
Ready
Input
Note
C
L
e
40 pF
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
CKIR
and t
CKIL
) on CKI input less than 2 5 ns
Note 2
Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
t
HAE
is specified for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
edge occurs later t
HAE
may be as long as (3 t
C
a
4WS
a
72 t
C
a
100) may occur depending on the following CPU instruction cycles its wait states and ready
input
Note 4
WS (t
WAIT
)
c
(number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency t
C
e
30 MHz with
one wait state programmed
Note 5
Due to emulation restrictions
actual limits will be better
Note 6
This is guaranteed by design and not tested
7
CKI Input Signal Characteristics
Rise Fall Time
TL DD 9682 34
Duty Cycle
TL DD 9682 35
FIGURE 1 CKI Input Signal
TL DD 9682 40
Note
AC testing inputs are driven at V
IH
for a logic ``1'' and V
IL
for a logic ``0'' Output timing measurements are made at 2 0V for a logic ``1'' and 0 8V for a logic
``0''
FIGURE 2 Input and Output for AC Tests
8
Timing Waveforms
TL DD 9682 2
FIGURE 3 CKI CK2 ALE Timing Diagram
TL DD 9682 3
FIGURE 4 Write Cycle
TL DD 9682 4
FIGURE 5 Read Cycle
9
Timing Waveforms
(Continued)
TL DD 9682 5
FIGURE 6 Ready Mode Timing
TL DD 9682 6
FIGURE 7 Hold Mode Timing
TL DD 9682 39
FIGURE 8 MICROWIRE Setup Hold Timing
10
Timing Waveforms
(Continued)
TL DD 9682 9
FIGURE 9 UPI Read Timing
TL DD 9682 10
FIGURE 10 UPI Write Timing
11
Pin Descriptions
The HPC46164 is available only in an 80-pin PQFP pack-
age
I O PORTS
Port A is a 16-bit bidirectional I O port with a data direction
register to enable each separate pin to be individually de-
fined as an input or output When accessing external memo-
ry port A is used as the multiplexed address data bus
Port B is a 16-bit port with 12 bits of bidirectional I O similar
in structure to Port A Pins B10 B11 B12 and B15 are gen-
eral purpose outputs only in this mode Port B may also be
configured via a 16-bit function register BFUN to individually
allow each pin to have an alternate function
B0
TDX
UART Data Output
B1
B2
CKX
UART Clock (Input or Output)
B3
T2IO
Timer2 I O Pin
B4
T3IO
Timer3 I O Pin
B5
SO
MICROWIRE PLUS Output
B6
SK
MICROWIRE PLUS Clock (Input or Output)
B7
HLDA
Hold Acknowledge Output
B8
TS0
Timer Synchronous Output
B9
TS1
Timer Synchronous Output
B10
UA0
Address 0 Input for UPI Mode
B11
WRRDY Write Ready Output for UPI Mode
B12
B13
TS2
Timer Synchronous Output
B14
TS3
Timer Synchronous Output
B15
RDRDY
Read Ready Output for UPI Mode
When accessing external memory four bits of port B are
used as follows
B10
ALE
Address Latch Enable Output
B11
WR
Write Output
B12
HBE
High Byte Enable Output Input
(sampled at reset)
B15
RD
Read Output
Port I is an 8-bit input port that can be read as general
purpose inputs and is also used for the following functions
I0
I1
NMI
Nonmaskable Interrupt Input
I2
INT2
Maskable Interrupt Input Capture URD
I3
INT3
Maskable Interrupt Input Capture UWR
I4
INT4
Maskable Interrupt Input Capture
I5
SI
MICROWIRE PLUS Data Input
I6
RDX
UART Data Input
I7
External Start A D Conversion
Port D is an 8-bit input port that can be used as general
purpose digital inputs or as analog channel inputs for the
A D converter These functions of Port D are mutually ex-
clusive and under the control of software
Port P is a 4-bit output port that can be used as general
purpose data or selected to be controlled by timers 4
through 7 in order to generate frequency duty cycle and
pulse width modulated outputs
POWER SUPPLY PINS
V
CC1
and
Positive Power Supply
V
CC2
GND
Ground for On-Chip Logic
DGND
Ground for Output Buffers
Note
There are two electrically connected V
CC
pins on the chip GND and
DGND are electrically isolated Both V
CC
pins and both ground pins
must be used
CLOCK PINS
CKI
The Chip System Clock Input
CKO
The Chip System Clock Output (inversion of
CKI)
Pins CKI and CKO are usually connected across an external
crystal
CK2
Clock Output (CKI divided by 2)
OTHER PINS
WO
This is an active low open drain output that
signals an illegal situation has been detected
by the WATCHDOG logic
ST1
Bus Cycle Status Output indicates first op-
code fetch
ST2
Bus Cycle Status Output indicates machine
states (skip interrupt and first instruction cy-
cle)
RESET
Active low input that forces the chip to restart
and sets the ports in a TRI-STATE mode
RDY HLD
Selected by a software bit
It's either a
READY input to extend the bus cycle for slow-
er memories or a HOLD request input to put
the bus in a high impedance state for DMA
purposes
V
REF
A D converter reference voltage input
EXM
External memory enable (active high) disables
internal ROM and maps it to external memory
EI
External
interrupt
with
vector
address
FFF1 FFF0 (Rising falling edge or high low
level sensitive) Alternately can be configured
as 4th input capture
EXUI
External active low interrupt which is internally
OR'ed with the UART interrupt with vector ad-
dress FFF3 FFF2
12
Connection Diagram
TL DD 9682 45
Top View
Order Number HPC46064XXX F20 HPC46064XXX F30
HPC46004VF20 or HPC46004VF30
See NS Package Number VF80B
Ports A
B
The highly flexible A and B ports are similarly structured
The Port A (see
Figure 11 ) consists of a data register and a
direction register Port B (see
Figures 12 13 and 14 ) has an
alternate function register in addition to the data and direc-
tion registers All the control registers are read write regis-
ters
The associated direction registers allow the port pins to be
individually programmed as inputs or outputs Port pins se-
lected as inputs are placed in a TRI-STATE mode by reset-
ting corresponding bits in the direction register
A write operation to a port pin configured as an input causes
the value to be written into the data register a read opera-
tion returns the value of the pin Writing to port pins config-
ured as outputs causes the pins to have the same value
reading the pins returns the value of the data register
Primary and secondary functions are multiplexed onto Port
B through the alternate function register (BFUN) The sec-
ondary functions are enabled by setting the corresponding
bits in the BFUN register
13
Ports A
B
(Continued)
TL DD 9682 13
FIGURE 11 Port A I O Structure
TL DD 9682 14
FIGURE 12 Structure of Port B Pins B0 B1 B2 B5 B6 and B7 (Typical Pins)
14
Ports A
B
(Continued)
TL DD 9682 15
FIGURE 13 Structure of Port B Pins B3 B4 B8 B9 B13 and B14 (Timer Synchronous Pins)
15
Ports A
B
(Continued)
TL DD 9682 16
FIGURE 14 Structure of Port B Pins B10 B11 B12 and B15 (Pins with Bus Control Roles)
Operating Modes
To offer the user a variety of I O and expanded memory
options the HPC46164 and HPC46104 have four operating
modes The ROMless HPC46104 has one mode of opera-
tion The various modes of operation are determined by the
state of both the EXM pin and the EA bit in the PSW regis-
ter The state of the EXM pin determines whether on-chip
ROM will be accessed or external memory will be accessed
within the address range of the on-chip ROM The on-chip
ROM range of the HPC46164 is C000 to FFFF (16k bytes)
The HPC46104 has no on-chip ROM and is intended for use
with external memory for program storage A logic ``0'' state
on the EXM pin will cause the HPC device to address on-
chip ROM when the Program Counter (PC) contains ad-
dresses within the on-chip ROM address range A logic ``1''
state on the EXM pin will cause the HPC device to address
memory that is external to the HPC when the PC contains
on-chip ROM addresses The EXM pin should always be
pulled high (logic ``1'') on the HPC46104 because no on-
chip ROM is available The function of the EA bit is to deter-
mine the legal addressing range of the HPC device A logic
``0'' state in the EA bit of the PSW register does two
things
addresses are limited to the on-chip ROM range
and on-chip RAM and Register range and the ``illegal ad-
dress detection'' feature of the WATCHDOG logic is en-
gaged A logic ``1'' in the EA bit enables accesses to be
made anywhere within the 64k byte address range and the
``illegal address detection'' feature of the WATCHDOG logic
is disabled The EA bit should be set to ``1'' by software
when using the HPC46104 to disable the ``illegal address
detection'' feature of WATCHDOG
All HPC devices can be used with external memory Exter-
nal memory may be any combination of RAM and ROM
Both 8-bit and 16-bit external data bus modes are available
Upon entering an operating mode in which external memory
is used port A becomes the Address Data bus Four pins of
port B become the control lines ALE RD WR and HBE The
High Byte Enable pin (HBE) is used in 16-bit mode to select
high order memory bytes The RD and WR signals are only
generated if the selected address is off-chip The 8-bit mode
is selected by pulling HBE high at reset If HBE is left float-
ing or connected to a memory device chip select at reset
the 16-bit mode is entered The following sections describe
the operating modes of the HPC46164 and HPC46104
Note
The HPC devices use 16-bit words for stack memory Therefore
when using the 8-bit mode User's Stack must be in internal RAM
16
HPC46164 Operating Modes
SINGLE CHIP NORMAL MODE
In this mode the HPC46164 functions as a self-contained
microcomputer (see
Figure 15 ) with all memory (RAM and
ROM) on-chip It can address internal memory only consist-
ing of 16k bytes of ROM (C000 to FFFF) and 512 bytes of
on-chip RAM and Registers (0000 to 02FF) The ``illegal
address detection'' feature of the WATCHDOG is enabled
in the Single-Chip Normal mode and a WATCHDOG Output
(WO) will occur if an attempt is made to access addresses
that are outside of the on-chip ROM and RAM range of the
device Ports A and B are used for I O functions and not for
addressing external memory The EXM pin and the EA bit of
the PSW register must both be logic ``0'' to enter the Single-
Chip Normal mode
TL DD 9682 17
FIGURE 15 Single-Chip Mode
EXPANDED NORMAL MODE
The Expanded Normal mode of operation enables the
HPC46164 to address external memory in addition to the
on-chip ROM and RAM (see Table I) WATCHDOG illegal
address detection is disabled and memory accesses may
be made anywhere in the 64k byte address range without
triggering an illegal address condition The Expanded Nor-
mal mode is entered with the EXM pin pulled low (logic ``0'')
and setting the EA bit in the PSW register to ``1''
SINGLE-CHIP ROMLESS MODE
In this mode the on-chip mask programmed ROM of the
HPC46164 is not used The address space corresponding
to the on-chip ROM is mapped into external memory so 16k
of external memory may be used with the HPC46164 (see
Table I) The WATCHDOG circuitry detects illegal address-
es (addresses not within the on-chip ROM and RAM range)
The Single-Chip ROMless mode is entered when the EXM
pin is pulled high (logic ``1'') and the EA bit is logic ``0''
TABLE I HPC46164 Operating Modes
Operating
EXM
EA
Memory
Mode
Pin
Bit
Configuration
Single-Chip Normal
0
0
C000 FFFF on-chip
Expanded Normal
0
1
C000 FFFF on-chip
0300 BFFF off-chip
Single-Chip ROMless
1
0
C000 FFFF off-chip
Expanded ROMless
1
1
0300 FFFF off-chip
Note
In all operating modes the on-chip RAM and Registers (0000 02FF)
may be accessed
EXPANDED ROMLESS MODE
This mode of operation is similar to Single-Chip ROMless
mode in that no on-chip ROM is used however a full 64k
bytes of external memory may be used The ``illegal address
detection'' feature of WATCHDOG is disabled The EXM pin
must be pulled high (logic ``1'') and the EA bit in the PSW
register set to ``1'' to enter this mode
TL DD 9682 18
FIGURE 16 8-Bit External Memory
17
HPC46164 Operating Modes
(Continued)
TL DD 9682 19
FIGURE 17 16-Bit External Memory
HPC46104 Operating Modes
EXPANDED ROMLESS MODE
Because the HPC46104 has no on-chip ROM it has only
one mode of operation the Expanded ROMless Mode The
EXM pin must be pulled high (logic ``1'') on power up the
EA bit in the PSW register should be set to a ``1'' The
HPC46104 is a ROMless device and is intended for use with
external memory The external memory may be any combi-
nation of ROM and RAM Up to 64k bytes of external mem-
ory may be accessed It is necessary to vector on reset to
an address between C000 and FFFF therefore the user
should have external memory at these addresses The EA
bit in the PSW register must immediately be set to ``1'' at the
beginning of the user's program to disable illegal address
detection in the WATCHDOG logic
TABLE II HPC46104 Operating Modes
Operating
EXM
EA
Memory
Mode
Pin
Bit
Configuration
Expanded ROMless
1
1
0300 FFFF off-chip
Note
The on-chip RAM and Registers (0000 02FF) of the HPC46104 may
be accessed at all times
Wait States
The internal ROM can be accessed at the maximum operat-
ing frequency with one wait state With 0 wait states internal
ROM accesses are limited to
f
C
max The HPC46164
provides four software selectable Wait States that allow ac-
cess to slower memories The Wait States are selected by
the state of two bits in the PSW register Additionally the
RDY input may be used to extend the instruction cycle al-
lowing the user to interface with slow memories and periph-
erals
Power Save Modes
Two power saving modes are available on the HPC46164
HALT and IDLE In the HALT mode all processor activities
are stopped In the IDLE mode the on-board oscillator and
timer T0 are active but all other processor activities are
stopped In either mode all on-board RAM registers and
I O are unaffected
HALT MODE
The HPC46164 is placed in the HALT mode under software
control by setting bits in the PSW All processor activities
including the clock and timers are stopped In the HALT
mode power requirements for the HPC46164 are minimal
and the applied voltage (V
CC
) may be decreased without
altering the state of the machine There are two ways of
exiting the HALT mode via the RESET or the NMI The
RESET input reinitializes the processor Use of the NMI in-
put will generate a vectored interrupt and resume operation
from that point with no initialization The HALT mode can be
enabled or disabled by means of a control register HALT
enable To prevent accidental use of the HALT mode the
HALT enable register can be modified only once
IDLE MODE
The HPC46164 is placed in the IDLE mode through the
PSW In this mode all processor activity except the on-
board oscillator and Timer T0 is stopped As with the HALT
mode the processor is returned to full operation by the
RESET or NMI inputs but without waiting for oscillator stabi-
lization A timer T0 overflow will also cause the HPC46164
to resume normal operation
18
HPC46164 Interrupts
Complex interrupt handling is easily accomplished by the
HPC46164's vectored interrupt scheme There are eight
possible interrupt sources as shown in Table III
TABLE III Interrupts
Vector
Interrupt
Arbitration
Address
Source
Ranking
FFFF FFFE
RESET
0
FFFD FFFC
Nonmaskable external on
1
rising edge of I1 pin
FFFB FFFA
External interrupt on I2 pin
2
FFF9 FFF8
External interrupt on I3 pin
3
FFF7 FFF6
External interrupt on I4 pin
4
FFF5 FFF4
Overflow on internal timers
5
FFF3 FFF2
Internal on the UART
transmit receive complete
6
or external on EXUI
or A D converter
FFF1 FFF0
External interrupt on EI pin
7
Interrupt Arbitration
The HPC46164 contains arbitration logic to determine which
interrupt will be serviced first if two or more interrupts occur
simultaneously The arbitration ranking is given in Table III
The interrupt on Reset has the highest rank and is serviced
first
Interrupt Processing
Interrupts are serviced after the current instruction is com-
pleted except for the RESET which is serviced immediately
RESET and EXUI are level-LOW-sensitive interrupts and EI
is programmable for edge-(RISING or FALLING) or level-
(HIGH or LOW) sensitivity All other interrupts are edge-sen-
sitive NMI is positive-edge sensitive The external interrupts
on I2 I3 and I4 can be software selected to be rising or
falling edge External interrupt (EXUI) is shared with the on-
board UART The EXUI interrupt is level-LOW-sensitive To
select this interrupt disable the ERI and ETI UART inter-
rupts by resetting these enable bits in the ENUI register To
select the on-board UART interrupt leave this pin floating
Interrupt Control Registers
The HPC46164 allows the various interrupt sources and
conditions to be programmed This is done through the vari-
ous control registers A brief description of the different con-
trol registers is given below
INTERRUPT ENABLE REGISTER (ENIR)
RESET and the External Interrupt on I1 are non-maskable
interrupts The other interrupts can be individually enabled
or disabled Additionally a Global Interrupt Enable Bit in the
ENIR Register allows the Maskable interrupts to be collec-
tively enabled or disabled Thus in order for a particular
interrupt to request service both the individual enable bit
and the Global Interrupt bit (GIE) have to be set
INTERRUPT PENDING REGISTER (IRPD)
The IRPD register contains a bit allocated for each interrupt
vector The occurrence of specified interrupt trigger condi-
tions causes the appropriate bit to be set There is no indi-
cation of the order in which the interrupts have been re-
ceived The bits are set independently of the fact that the
interrupts may be disabled IRPD is a Read Write register
The bits corresponding to the maskable external interrupts
are normally cleared by the HPC46164 after servicing the
interrupts
For the interrupts from the on-board peripherals the user
has the responsibility of resetting the interrupt pending flags
through software
The NMI bit is read only and I2 I3 and I4 are designed as to
only allow a zero to be written to the pending bit (writing a
one has no affect) A LOAD IMMEDIATE instruction is to be
the only instruction used to clear a bit or bits in the IRPD
register This allows a mask to be used thus ensuring that
the other pending bits are not affected
INTERRUPT CONDITION REGISTER (IRCD)
Three bits of the register select the input polarity of the
external interrupt on I2 I3 and I4
Servicing the Interrupts
The Interrupt once acknowledged pushes the program
counter (PC) onto the stack thus incrementing the stack
pointer (SP) twice The Global Interrupt Enable bit (GIE) is
copied into the CGIE bit of the PSW register it is then reset
thus disabling further interrupts The program counter is
loaded with the contents of the memory at the vector ad-
dress and the processor resumes operation at this point At
the end of the interrupt service routine the user does a
RETI instruction to pop the stack and re-enable interrupts if
the CGIE bit is set or RET to just pop the stack if the CGIE
bit is clear and then returns to the main program The GIE
bit can be set in the interrupt service routine to nest inter-
rupts if desired
Figure 18 shows the Interrupt Enable Logic
Reset
The RESET input initializes the processor and sets ports A
and B in the TRI-STATE condition and Port P in the LOW
state RESET is an active-low Schmitt trigger input The
processor vectors to FFFF FFFE and resumes operation at
the address contained at that memory location (which must
correspond to an on board location) The Reset vector ad-
dress must be between C000 and FFFF when using the
HPC46104
19
Servicing the Interrupts
(Continued)
TLDD9682
2
0
FIGURE
18
Block
Diagram
of
Interrupt
Logic
20
Timer Overview
The HPC46164 contains a powerful set of flexible timers
enabling the HPC46164 to perform extensive timer func-
tions not usually associated with microcontrollers
The
HPC46164 contains nine 16-bit timers Timer T0 is a free-
running timer counting up at a fixed CKI 16 (Clock Input
16) rate It is used for WATCHDOG logic high speed event
capture and to exit from the IDLE mode Consequently it
cannot be stopped or written to under software control Tim-
er T0 permits precise measurements by means of the cap-
ture registers I2CR I3CR and I4CR A control bit in the
register TMMODE configures timer T1 and its associated
register R1 as capture registers I3CR and I2CR The cap-
ture registers I2CR I3CR and I4CR respectively record the
value of timer T0 when specific events occur on the inter-
rupt pins I2 I3 and I4 The control register IRCD programs
the capture registers to trigger on either a rising edge or a
falling edge of its respective input The specified edge can
also be programmed to generate an interrupt (see
Figure
19 )
TL DD 9682 21
FIGURE 19 Timers T0 T1 and T8 with
Four Input Capture Registers
The HPC46164 provides an additional 16-bit free running
timer T8 with associated input capture register EICR (Ex-
ternal Interrupt Capture Register) and Configuration Regis-
ter EICON EICON is used to select the mode and edge of
the EI pin EICR is a 16-bit capture register which records
the value of T8 (which is identical to T0) when a specific
event occurs on the EI pin
The timers T2 and T3 have selectable clock rates The
clock input to these two timers may be selected from the
following two sources an external pin or derived internally
by dividing the clock input Timer T2 has additional capabili-
ty of being clocked by the timer T3 underflow This allows
the user to cascade timers T3 and T2 into a 32-bit timer
counter The control register DIVBY programs the clock in-
put to timers T2 and T3 (see
Figure 20 )
The timers T1 through T7 in conjunction with their registers
form Timer-Register pairs The registers hold the pulse du-
ration values All the Timer-Register pairs can be read from
or written to Each timer can be started or stopped under
software control Once enabled the timers count down and
upon underflow the contents of its associated register are
automatically loaded into the timer
SYNCHRONOUS OUTPUTS
The flexible timer structure of the HPC46164 simplifies
pulse generation and measurement There are four syn-
chronous timer outputs (TS0 through TS3) that work in con-
junction with the timer T2 The synchronous timer outputs
can be used either as regular outputs or individually pro-
grammed to toggle on timer T2 underflows (see
Figure 20 )
TL DD 9682 22
FIGURE 20 Timers T2 T3 Block
21
Timer Overview
(Continued)
Timer register pairs 4 7 form four identical units which can
generate synchronous outputs on port P (see
Figure 21 )
Maximum output frequency for any timer output can be ob-
tained by setting timer register pair to zero This then will
produce an output frequency equal to
the frequency of
the source used for clocking the timer
TL DD 9682 23
FIGURE 21 Timers T4 T7 Block
Timer Registers
There are four control registers that program the timers The
divide by (DIVBY) register programs the clock input to tim-
ers T2 and T3 The timer mode register (TMMODE) contains
control bits to start and stop timers T1 through T3 It also
contains bits to latch acknowledge and enable interrupts
from timers T0 through T3 The control register PWMODE
similarly programs the pulse width timers T4 through T7 by
allowing them to be started stopped and to latch and en-
able interrupts on underflows The PORTP register contains
bits to preset the outputs and enable the synchronous timer
output functions
Timer Applications
The use of Pulse Width Timers for the generation of various
waveforms is easily accomplished by the HPC46164
Frequencies can be generated by using the timer register
pairs A square wave is generated when the register value is
a constant The duty cycle can be controlled simply by
changing the register value
TL DD 9682 24
FIGURE 22 Square Wave Frequency Generation
Synchronous outputs based on Timer T2 can be generated
on the 4 outputs TS0 TS3 Each output can be individually
programmed to toggle on T2 underflow Register R2 con-
tains the time delay between events
Figure 23 is an exam-
ple of synchronous pulse train generation
TL DD 9682 25
FIGURE 23 Synchronous Pulse Generation
WATCHDOG Logic
The WATCHDOG Logic monitors the operations taking
place and signals upon the occurrence of any illegal activity
The illegal conditions that trigger the WATCHDOG logic are
potentially infinite loops and illegal addresses Should the
WATCHDOG register not be written to before Timer T0
overflows twice or more often than once every 4096
counts an infinite loop condition is assumed to have oc-
curred An illegal condition also occurs when the processor
generates an illegal address when in the Single-Chip
modes
Any illegal condition forces the WATCHDOG Out-
put (WO) pin low The WO pin is an open drain output and
can be connected to the RESET or NMI inputs or to the
users external logic
Note See Operating Modes for details
MICROWIRE PLUS
MICROWIRE PLUS is used for synchronous serial data
communications (see
Figure 24 ) MICROWIRE PLUS has
an 8-bit parallel-loaded serial shift register using SI as the
input and SO as the output SK is the clock for the serial
shift register (SIO) The SK clock signal can be provided by
an internal or external source The internal clock rate is pro-
grammable by the DIVBY register A DONE flag indicates
when the data shift is completed
The MICROWIRE PLUS capability enables it to interface
with any of National Semiconductor's MICROWIRE periph-
erals (i e A D converters display drivers EEPROMs)
22
MICROWIRE PLUS
(Continued)
TL DD 9682 26
FIGURE 24 MICROWIRE PLUS
MICROWIRE PLUS Operation
The HPC46164 can enter the MICROWIRE PLUS mode as
the master or a slave A control bit in the IRCD register
determines whether the HPC46164 is the master or slave
The shift clock is generated when the HPC46164 is config-
ured as a master An externally generated shift clock on the
SK pin is used when the HPC46164 is configured as a slave
When the HPC46164 is a master the DIVBY register pro-
grams the frequency of the SK clock The DIVBY register
allows the SK clock frequency to be programmed in 14 se-
lectable binary steps or T3 underflow from 153 Hz to
1 25 MHz with CKI at 20 0 MHz
The contents of the SIO register may be accessed through
any of the memory access instructions Data waiting to be
transmitted in the SIO register is clocked out on the falling
edge of the SK clock Serial data on the SI pin is clocked in
on the rising edge of the SK clock
MICROWIRE PLUS Application
Figure 25 illustrates a MICROWIRE PLUS arrangement for
an automotive application The microcontroller-based sys-
tem could be used to interface to an instrument cluster and
various parts of the automobile The diagram shows two
HPC46164 microcontrollers interconnected to other MI-
CROWIRE peripherals HPC46164
1 is set up as the mas-
ter and initiates all data transfers HPC46164
2 is set up
as a slave answering to the master
The master microcontroller interfaces the operator with the
system and could also manage the instrument cluster in an
automotive application Information is visually presented to
the operator by means of an LCD display controlled by the
COP472 display driver The data to be displayed is sent
serially to the COP472 over the MICROWIRE PLUS link
Data such as accumulated mileage could be stored and re-
trieved from the EEPROM COP494 The slave HPC46164
could be used as a fuel injection processor and generate
timing signals required to operate the fuel valves The mas-
ter processor could be used to periodically send updated
values to the slave via the MICROWIRE PLUS link To
speed up the response chip select logic is implemented by
connecting an output from the master to the external inter-
rupt input on the slave
23
MICROWIRE PLUS Application
(Continued)
TL DD 9682 27
FIGURE 25 MICROWIRE PLUS Application
24
HPC46164 UART
The HPC46164 contains a software programmable UART
The UART (see
Figure 26 ) consists of a transmit shift regis-
ter a receiver shift register and five addressable registers
as follows a transmit buffer register (TBUF) a receiver buff-
er register (RBUF) a UART control and status register
(ENU) a UART receive control and status register (ENUR)
and a UART interrupt and clock source register (ENUI) The
ENU register contains flags for transmit and receive func-
tions this register also determines the length of the data
frame (8 or 9 bits) and the value of the ninth bit in transmis-
sion The ENUR register flags framing and data overrun er-
rors while the UART is receiving Other functions of the
ENUR register include saving the ninth bit received in the
data frame and enabling or disabling the UART's Wake-up
Mode of operation The determination of an internal or ex-
ternal clock source is done by the ENUI register as well as
selecting the number of stop bits and enabling or disabling
transmit and receive interrupts
The baud rate clock for the Receiver and Transmitter can
be selected for either an internal or external source using
two bits in the ENUI register The internal baud rate is pro-
grammed by the DIVBY register The baud rate may be se-
lected from a range of 8 Hz to 128 kHz in binary steps or T3
underflow By selecting a 9 83 MHz crystal all standard
baud rates from 75 baud to 38 4 kBaud can be generated
The external baud clock source comes from the CKX pin
The Transmitter and Receiver can be run at different rates
by selecting one to operate from the internal clock and the
other from an external source
The HPC46164 UART supports two data formats The first
format for data transmission consists of one start bit eight
data bits and one or two stop bits The second data format
for transmission consists of one start bit nine data bits and
one or two stop bits Receiving formats differ from transmis-
sion only in that the Receiver always requires only one stop
bit in a data frame
UART Wake-up Mode
The HPC46164 UART features a Wake-up Mode of opera-
tion This mode of operation enables the HPC46164 to be
networked with other processors Typically in such environ-
ments the messages consist of addresses and actual data
Addresses are specified by having the ninth bit in the data
frame set to 1 Data in the message is specified by having
the ninth bit in the data frame reset to 0
The UART monitors the communication stream looking for
addresses When the data word with the ninth bit set is
received the UART signals the HPC46164 with an interrupt
The processor then examines the content of the receiver
buffer to decide whether it has been addressed and whether
to accept subsequent data
TL DD 9682 28
FIGURE 26 UART Block Diagram
25
A D Converter
The HPC46164 has an on-board eight-channel 8-bit Analog
to Digital converter Conversion is peformed using a succes-
sive approximation technique The A D converter cell can
operate in single-ended mode where the input voltage is
applied across one of the eight input channels (D0 D7) and
AGND or in differential mode where the input voltage is ap-
plied across two adjacent input channels The A D convert-
er will convert up to eight channels in single-ended mode
and up to four channel-pairs in differential mode
OPERATING MODES
The operating modes of the converter are selected by 4 bits
called ADMODE (CR2 4 7) see Table IV Associated with
the eight input channels in single-ended mode are eight re-
sult registers one for each channel The A D converter can
be programmed by software to convert on any specific
channel storing the result in the result register associated
with that channel It can also be programmed to stop after
one conversion or to convert continuously If a brief history
of the signal on any specific input channel is required the
converter can be programmed to convert on that channel
and store the consecutive results in each of the result regis-
ters before stopping As a final configuration in single-ended
mode the converter can be programmed to convert the sig-
nal on each input channel and store the result in its associ-
ated result register continuously
Associated with each even-odd pair of input channels in
differential mode of operation are four result register-pairs
The A D converter performs two conversions on the select-
ed pair of input channels One conversion is performed as-
suming the positive connection is made to the even channel
and the negative connection is made to the following odd
channel This result is stored in the result register associat-
ed with the even channel Another conversion is performed
assuming the positive connection is made to the odd chan-
nel and the negative connection is made to the preceding
even channel This result is stored in the result register as-
sociated with the odd channel This technique does not re-
quire that the programmer know the polarity of the input
signal If the even channel result register is nonzero (mean-
ing the odd channel result register is zero) then the input
signal is positive with respect to the odd channel If the odd
channel result register is non-zero (meaning the even chan-
nel result register is zero) then the input signal is positive
with respect to the even channel
The same operating modes for single-ended operation also
apply when the inputs are taken from channel-pairs in differ-
ential mode The programmer can configure the A D to con-
vert on any selected channel-pair and store the result in its
associated result register-pair then stop The A D can also
be programmed to do this continuously Conversion can
also be done on any channel-pair storing the result into four
result register-pairs for a history of the differential input Fi-
nally all input channel-pairs can be converted continuously
The final mode of operation suppresses the external ad-
dress data bus activity during the single conversion modes
These quiet modes of operation utilize the RDY function of
the HPC Core to insert wait states in the instruction being
executed in order to limit digital noise in the environment
due to external bus activity when addressing external mem-
ory The overall effect is to increase the accuracy of the
A D
CONTROL
The conversion clock supplied to the A D converter can be
selected by three bits in CR1 used as a prescaler on CKI
These bits can be used to ensure that the A D is clocked as
fast as possible when different external crystal frequencies
are used Controlling the starting of conversion cycles in
each of the operating modes can be done by four different
methods The method is selected by two bits called SC
(CR3 0 1) Conversion cycles can be initiated through soft-
ware by resetting a bit in a control register through hard-
ware by an underflow of Timer T2 or externally by a rising or
falling edge of a signal input on I7
INTERRUPTS
The A D converter can interrupt the HPC when it completes
a conversion cycle if one of the noncontinuous modes has
been selected If one of the cycle modes was selected then
the converter will request an interrupt after eight conver-
sions If one of the one-shot modes was selected then the
converter will request an interrupt after every conversion
When this interrupt is generated the HPC vectors to the on-
board peripheral interrupt vector location at address FFF2
The service routine must then determine if the A D convert-
er requested the interrupt by checking the A D done flag
which doubles as the A D interrupt pending flag
Analog Input and Source Resistance Considerations
Figure 27 shows the A D pin model for the HPC46164 in
single ended mode The differential mode has similar A D
pin model The leads to the analog inputs should be kept as
short as possible Both noise and digital clock coupling to
an A D input can cause conversion errors The clock lead
should be kept away from the analog input line to reduce
coupling The A D channel input pins do not have any inter-
nal output driver circuitry connected to them because this
circuitry would load the analog input singals due to output
buffer leakage current
TL DD 9682 12
The analog switch is closed only during the sample time
FIGURE 27 Port D Input Structure
26
A D Converter
(Continued)
TABLE IV A D Operating Modes
Mode 0
Single-ended single channel single result
register one-shot (default value on power-up)
Mode 1
Single-ended single channel single result
register continuous
Mode 2
Single-ended single channel multiple result
registers stop after 8
Mode 3
Single-ended multiple channel multiple result
registers continuous
Mode 4
Differential single channel-pair single result
register-pair one-shot
Mode 5
Differential single channel-pair single result
register-pair continuous
Mode 6
Differential single channel-pair multiple result
register-pairs stop after 4 pairs
Mode 7
Differential multiple channel-pair multiple
result register-pairs continuous
Mode 8
Single-ended single channel single result
register one-shot (default value on power-
up) quiet address data bus
Mode C
Differential single channel-pair single result
register-pair one-shot quiet address data bus
Source impedances greater than 1 kX on the analog input
lines will adversely affect internal RC charging time during
input sampling As shown in
Figure 27 the analog switch to
the capacitor array is closed only during the 2 A D cycle
sample time Large source impedances on the analog in-
puts may result in the capacitor array not being charged to
the correct voltage levels causing scale errors
If large source resistance is necessary the recommended
solution is to slow down the A D clock speed in proportion
to the source resistance The A D converter may be operat-
ed at the maximum speed for R
S
less than 1 kX For R
S
greater than 1 kX A D clock speed needs to be reduced
For example with R
S
e
2 kX the A D converter may be
operated at half the maximum speed A D converter clock
speed may be slowed down by either increasing the A D
prescaler divide-by or decreasing the CKI clock frequency
The A D clock speed may be reduced to its minimum fre-
quency of 100 kHz
Universal Peripheral Interface
The
Universal
Peripheral
Interface
(UPI)
allows
the
HPC46164 to be used as an intelligent peripheral to another
processor The UPI could thus be used to tightly link two
HPC46164's and set up systems with very high data ex-
change rates Another area of application could be where
an HPC46164 is programmed as an intelligent peripheral to
a host system such as the Series 32000
microprocessor
Figure 28 illustrates how an HPC46164 could be used as an
intelligent peripherial for a Series 32000-based application
The interface consists of a Data Bus (port A) a Read Strobe
(URD) a Write Strobe (UWR) a Read Ready Line (RDRDY)
a Write Ready Line (WRRDY) and one Address Input (UA0)
The data bus can be either eight or sixteen bits wide
The URD and UWR inputs may be used to interrupt the
HPC46164 The RDRDY and WRRDY outputs may be used
to interrupt the host processor
The UPI contains an Input Buffer (IBUF) an Output Buffer
(OBUF) and a Control Register (UPIC) In the UPI mode
port A on the HPC46164 is the data bus UPI can only be
used if the HPC46164 is in the Single-Chip mode
TL DD 9682 30
FIGURE 28 HPC46164 as a Peripheral (UPI Interface to Series 32000 Application)
27
Shared Memory Support
Shared memory access provides a rapid technique to ex-
change data It is effective when data is moved from a pe-
ripheral to memory or when data is moved between blocks
of memory A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block The HPC46164
supports shared memory access with two pins The pins are
the RDY HLD input pin and the HLDA output pin The user
can software select either the Hold or Ready function by the
state of a control bit The HLDA output is multiplexed onto
port B
The host uses DMA to interface with the HPC46164 The
host initiates a data transfer by activating the HLD input of
the HPC46164 In response the HPC46164 places its sys-
tem bus in a TRI-STATE Mode freeing it for use by the host
The host waits for the acknowledge signal (HLDA) from the
HPC46164 indicating that the sytem bus is free On receiv-
ing the acknowledge the host can rapidly transfer data into
or out of the shared memory by using a conventional DMA
controller Upon completion of the message transfer the
host removes the HOLD request and the HPC46164 re-
sumes normal operations
To insure proper operation the interface logic shown is rec-
ommended as the means for enabling and disabling the us-
er's bus
Figure 29 illustrates an application of the shared
memory interface between the HPC46164 and a Series
32000 system
TL DD 9682 31
FIGURE 29 Shared Memory Application HPC46164 Interface to Series 32000 System
28
Memory
The HPC46164 has been designed to offer flexibility in
memory usage A total address space of 64 kbytes can be
addressed with 16 kbytes of ROM and 512 bytes of RAM
available on the chip itself The ROM may contain program
instructions constants or data The ROM and RAM share
the same address space allowing instructions to be execut-
ed out of RAM
Program memory addressing is accomplished by the 16-bit
program counter on a byte basis Memory can be addressed
directly by instructions or indirectly through the B X and SP
registers Memory can be addressed as words or bytes
Words are always addressed on even-byte boundaries The
HPC46164 uses memory-mapped organization to support
registers I O and on-chip peripheral functions
The
HPC46164
memory
address
space
extends
to
64 kbytes and registers and I O are mapped as shown in
Table V
TABLE V HPC46164 Memory Map
FFFF FFF0
Interrupt Vectors
FFEF FFD0
JSRP Vectors
FFCF FFCE
On-Chip ROM
C001 C000
(
USER MEMORY
BFFF BFFE
External Expansion
0301 0300
Memory
(
02FF 02FE
On-Chip RAM
USER RAM
01C1 01C0
(
0195 0194
WATCHDOG Address
WATCHDOG Logic
0192
T0CON Register
0191 0190
TMMODE Register
018F 018E
DIVBY Register
018D 018C
T3 Timer
018B 018A
R3 Register
Timer Block T0 T3
0189 0188
T2 Timer
0187 0186
R2 Register
0185 0184
I2CR Register R1
0183 0182
I3CR Register T1
0181 0180
I4CR Register
015E 015F
EICR
015C
EICON
0153 0152
Port P Register
0151 0150
PWMODE Register
014F 014E
R7 Register
014D 014C
T7 Timer
014B 014A
R6 Register
Timer Block T4 T7
0149 0148
T6 Timer
0147 0146
R5 Register
0145 0144
T5 Timer
0143 0142
R4 Register
0141 0140
T4 Timer
0128
ENUR Register
0126
TBUF Register
0124
RBUF Register
UART
0122
ENUI Register
0120
ENU Register
011F 011E
A D Result Register 7
011D 011C
A D Result Register 6
011B 011A
A D Result Register 5
0119 0118
A D Result Register 4
A to D
0117 0116
A D Result Register 3
Registers
0115 0114
A D Result Register 2
0113 0112
A D Result Register 1
0111 0110
A D Result Register 0
0106
A D Control Register 3
0104
Port D Input Register
0102
A D Control Register 2
A to D
0100
A D Control Register 1
Registers
00F5 00F4
BFUN Register
PORTS A
B
00F3 00F2
DIR B Register
CONTROL
00F1 00F0
DIR A Register
IBUF
00E6
UPIC Register
UPI CONTROL
00E3 00E2
Port B
PORTS A
B
00E1 00E0
Port A
OBUF
00DE
Reserved
00DD 00DC
HALT Enable Register
PORT CONTROL
00D8
Port I Input Register
INTERRUPT
00D6
SIO Register
CONTROL
00D4
IRCD Register
REGISTERS
00D2
IRPD Register
00D0
ENIR Register
00CF 00CE
X Register
00CD 00CC
B Register
00CB 00CA
K Register
00C9 00C8
A Register
HPC CORE
00C7 00C6
PC Register
REGISTERS
00C5 00C4
SP Register
00C3 00C2
Reserved
00C0
PSW Register
00BF 00BE
On-Chip
RAM
USER RAM
0001 0000
Note
The HPC46164 On-Chip ROM is on addresses C000 FFFF and the
External Expansion Memory is 0300 BFFF The HPC46104 have no On-Chip
ROM External Memory is 0300 FFFF
29
Design Considerations
Designs using the HPC family of 16-bit high speed CMOS
microcontrollers need to follow some general guidelines on
usage and board layout
Floating inputs are a frequently overlooked problem CMOS
inputs have extremely high impedance and if left open can
float to any voltage You should thus tie unused inputs to
V
CC
or ground either through a resistor or directly Unlike
the inputs unused output should be left floating to allow the
output to switch without drawing any DC current
To reduce voltage transients keep the supply line's parasit-
ic inductances as low as possible by reducing trace lengths
using wide traces ground planes and by decoupling the
supply with bypass capacitors In order to prevent additional
voltage spiking this local bypass capacitor must exhibit low
inductive reactance You should therefore use high frequen-
cy ceramic capacitors and place them very near the IC to
minimize wiring inductance
Keep V
CC
bus routing short When using double sided or
multilayer circuit boards use ground plane techniques
Keep ground lines short and on PC boards make them
as wide as possible even if trace width varies Use sepa-
rate ground traces to supply high current devices such as
relay and transmission line drivers
In systems mixing linear and logic functions and where
supply noise is critical to the analog components' per-
formance provide separate supply buses or even sepa-
rate supplies
If you use local regulators bypass their inputs with a tan-
talum capacitor of at least 1 mF and bypass their outputs
with a 10 mF to 50 mF tantalum or aluminum electrolytic
capacitor
If the system uses a centralized regulated power supply
use a 10 mF to 20 mF tantalum electrolytic capacitor or a
50 mF to 100 mF aluminum electrolytic capacitor to de-
couple the V
CC
bus connected to the circuit board
Provide localized decoupling For random logic a rule of
thumb dictates approximately 10 nF (spaced within
12 cm) per every two to five packages and 100 nF for
every 10 packages You can group these capacitances
but it's more effective to distribute them among the ICs If
the design has a fair amount of synchronous logic with
outputs that tend to switch simultaneously additional de-
coupling might be advisable Octal flip-flop and buffers in
bus-oriented circuits might also require more decoupling
Note that wire-wrapped circuits can require more decou-
pling than ground plane or multilayer PC boards
A recommended crystal oscillator circuit to be used with the
HPC is shown in
Figure 30 See table for recommended
component values The recommended values given in Ta-
ble VI have yielded consistent results and are made to
match a crystal with a 20 pF load capacitance with some
small allowance for layout capacitance
A recommended layout for the oscillator network should be
as close to the processor as physically possible entirely
within ``1'' distance This is to reduce lead inductance from
long PC traces as well as interference from other compo-
nents and reduce trace capacitance The layout contains a
large ground plane either on the top or bottom surface of
the board to provide signal shielding and a convenient loca-
tion to ground both the HPC and the case of the crystal
It is very critical to have an extremely clean power supply for
the HPC crystal oscillator Ideally one would like a V
CC
and
ground plane that provide low inductance power lines to the
chip The power planes in the PC board should be decou-
pled with three decoupling capacitors as close to the chip
as possible A 1 0 mF a 0 1 mF and a 0 001 mF dipped mica
or ceramic cap mounted as close to the HPC as is physically
possible on the board using the shortest leads or surface
mount components This should provide a stable power
supply and noiseless ground plane which will vastly im-
prove the performance of the crystal oscillator network
TABLE VI HPC Oscillator Table
XTAL
Freq
R
1
(X)
(MHz)
s
2
1500
4
1200
6
910
8
750
10
600
12
470
14
390
16
300
18
220
20
180
22
150
24
120
26
100
28
75
30
62
R
F
e
3 3 MX
C
1
e
27 pF
C
2
e
33F
XTAL Specifications The crystal used was an M-TRON Industries MP-1 Se-
ries XTAL ``AT'' cut parallel resonant
C
L
e
18 pF
Series Resistance is
25X
25 MHz
40X
10 MHz
600X
2 MHz
TL DD 9682 41
FIGURE 30 Recommended Crystal Circuit
HPC46164 CPU
The HPC46164 CPU has a 16-bit ALU and six 16-bit regis-
ters
Arithmetic Logic Unit (ALU)
The ALU is 16 bits wide and can do 16-bit add subtract and
shift or logic AND OR and exclusive OR in one timing cycle
The ALU can also output the carry bit to a 1-bit C register
30
HPC46164 CPU
(Continued)
Accumulator (A) Register
The 16-bit A register is the source and destination register
for most I O arithmetic logic and data memory access op-
erations
Address (B and X) Registers
The 16-bit B and X registers can be used for indirect ad-
dressing They can automatically count up or down to se-
quence through data memory
Boundary (K) Register
The 16-bit K register is used to set limits in repetitive loops
of code as register B sequences through data memory
Stack Pointer (SP) Register
The 16-bit SP register is the pointer that addresses the
stack The SP register is incremented by two for each push
or call and decremented by two for each pop or return The
stack can be placed anywhere in user memory and be as
deep as the available memory permits
Program (PC) Register
The 16-bit PC register addresses program memory
Addressing Modes
ADDRESSING MODES
ACCUMULATOR AS
DESTINATION
Register Indirect
This is the ``normal'' mode of addressing for the HPC46164
(instructions are single-byte) The operand is the memory
addressed by the B register (or X register for some instruc-
tions)
Direct
The instruction contains an 8-bit or 16-bit address field that
directly points to the memory for the operand
Indirect
The instruction contains an 8-bit address field The contents
of the WORD addressed points to the memory for the oper-
and
Indexed
The instruction contains an 8-bit address field and an 8- or
16-bit displacement field The contents of the WORD ad-
dressed is added to the displacement to get the address of
the operand
Immediate
The instruction contains an 8-bit or 16-bit immediate field
that is used as the operand
Register Indirect (Auto Increment and Decrement)
The operand is the memory addressed by the X register
This mode automatically increments or decrements the X
register (by 1 for bytes and by 2 for words)
Register Indirect (Auto Increment and Decrement)
with Conditional Skip
The operand is the memory addressed by the B register
This mode automatically increments or decrements the B
register (by 1 for bytes and by 2 for words) The B register is
then compared with the K register A skip condition is gener-
ated if B goes past K
ADDRESSING MODES
DIRECT MEMORY AS
DESTINATION
Direct Memory to Direct Memory
The instruction contains two 8- or 16-bit address fields One
field directly points to the source operand and the other field
directly points to the destination operand
Immediate to Direct Memory
The instruction contains an 8- or 16-bit address field and an
8- or 16-bit immediate field The immediate field is the oper-
and and the direct field is the destination
Double Register Indirect Using the B and X Registers
Used only with Reset Set and IF bit instructions a specific
bit within the 64 kbyte address range is addressed using the
B and X registers The address of a byte of memory is
formed by adding the contents of the B register to the most
significant 13 bits of the X register The specific bit to be
modified or tested within the byte of memory is selected
using the least significant 3 bits of register X
HPC Instruction Set Description
Mnemonic
Description
Action
ARITHMETIC INSTRUCTIONS
ADD
Add
MA
a
MemI
x
MA
carry
x
C
ADC
Add with carry
MA
a
MemI
a
C
x
MA
carry
x
C
ADDS
Add short imm8
A
a
imm8
x
A
carry
x
C
DADC
Decimal add with carry
MA
a
MemI
a
C
x
MA (Decimal)
carry
x
C
SUBC
Subtract with carry
MA
b
MemI
a
C
x
MA
carry
x
C
DSUBC
Decimal subtract w carry
MA
b
MemI
a
C
x
MA (Decimal)
carry
x
C
MULT
Multiply (unsigned)
MA MemI
x
MA
X 0
x
K 0
x
C
DIV
Divide (unsigned)
MA MemI
x
MA rem
x
X 0
x
K 0
x
C
DIVD
Divide Double Word (unsigned)
X
MA MemI
x
MA rem
x
X 0
x
K Carry
x
C
IFEQ
If equal
Compare MA
MemI Do next if equal
IFGT
If greater than
Compare MA
MemI Do next if MA
l
MemI
AND
Logical and
MA and MemI
x
MA
OR
Logical or
MA or MemI
x
MA
XOR
Logical exclusive-or
MA xor MemI
x
MA
MEMORY MODIFY INSTRUCTIONS
INC
Increment
Mem
a
1
x
Mem
DECSZ
Decrement skip if 0
Mem
b
1
x
Mem Skip next if Mem
e
0
31
HPC Instruction Set Description
(Continued)
Mnemonic
Description
Action
BIT INSTRUCTIONS
SBIT
Set bit
1
x
Mem bit
RBIT
Reset bit
0
x
Mem bit
IFBIT
If bit
If Mem bit is true do next instr
MEMORY TRANSFER INSTRUCTIONS
LD
Load
MemI
x
MA
Load incr decr X
Mem(X)
x
A X
g
1 (or 2)
x
X
ST
Store to Memory
A
x
Mem
X
Exchange
A
Mem
Exchange incr decr X
A
Mem(X) X
g
1 (or 2)
x
X
PUSH
Push Memory to Stack
W
x
W(SP) SP
a
2
x
SP
POP
Pop Stack to Memory
SP
b
2
x
SP W(SP)
x
W
LDS
Load A incr decr B
Mem(B)
x
A B
g
1 (or 2)
x
B
Skip on condition
Skip next if B greater less than K
XS
Exchange incr decr B
Mem(B)
A B
g
1 (or 2)
x
B
Skip on condition
Skip next if B greater less than K
REGISTER LOAD IMMEDIATE INSTRUCTIONS
LD B
Load B immediate
imm
x
B
LD K
Load K immediate
imm
x
K
LD X
Load X immediate
imm
x
X
LD BK
Load B and K immediate
imm
x
B imm
x
K
ACCUMULATOR AND C INSTRUCTIONS
CLR A
Clear A
0
x
A
INC A
Increment A
A
a
1
x
A
DEC A
Decrement A
A
b
1
x
A
COMP A
Complement A
1's complement of A
x
A
SWAP A
Swap nibbles of A
A15 12
w
A11 8
w
A7 4
A3 0
RRC A
Rotate A right thru C
C
x
A15
x
x
A0
x
C
RLC A
Rotate A left thru C
C
w
A15
w
w
A0
w
C
SHR A
Shift A right
0
x
A15
x
x
A0
x
C
SHL A
Shift A left
C
w
A15
w
w
A0
w
0
SC
Set C
1
x
C
RC
Reset C
0
x
C
IFC
IF C
Do next if C
e
1
IFNC
IF not C
Do next if C
e
0
TRANSFER OF CONTROL INSTRUCTIONS
JSRP
Jump subroutine from table
PC
x
W(SP) SP
a
2
x
SP
W(table )
x
PC
JSR
Jump subroutine relative
PC
x
W(SP) SP
a
2
x
SP PC
a
x
PC
( is
a
1025 to
b
1023)
JSRL
Jump subroutine long
PC
x
W(SP) SP
a
2
x
SP PC
a
x
PC
JP
Jump relative short
PC
a
x
PC(
is
a
32 to
b
31)
JMP
Jump relative
PC
a
x
PC( is
a
257 to
b
255)
JMPL
Jump relative long
PC
a
x
PC
JID
Jump indirect at PC
a
A
PC
a
A
a
1
x
PC
JIDW
then Mem(PC)
a
PC
x
PC
NOP
No Operation
PC
a
1
x
PC
RET
Return
SP
b
2
x
SP W(SP)
x
PC
RETSK
Return then skip next
SP
b
2
x
SP W(SP)
x
PC
skip
RETI
Return from interrupt
SP
b
2
x
SP W(SP)
x
PC interrupt re-enabled
Note
W is 16-bit word of memory
MA is Accumulator A or direct memory (8- or 16-bit)
Mem is 8-bit byte or 16-bit word of memory
MemI is 8- or 16-bit memory or 8- or 16-bit immediate data
imm is 8-bit or 16-bit immediate data
imm8 is 8-bit immediate data only
32
Memory Usage
Number of Bytes for Each Instruction
(number in parenthesis is 16-Bit field)
Using Accumulator A
To Direct Memory
Reg Indir
Direct
Indir
Index
Immed
Direct
Immed
(B)
(X)
LD
1
1
2(4)
3
4(5)
2(3)
3(5)
5(6)
3(4)
5(6)
X
1
1
2(4)
3
4(5)
ST
1
1
2(4)
3
4(5)
ADC
1
2
3(4)
3
4(5)
4(5)
4(5)
5(6)
4(5)
5(6)
ADDS
2
SBC
1
2
3(4)
3
4(5)
4(5)
4(5)
5(6)
4(5)
5(6)
DADC
1
2
3(4)
3
4(5)
4(5)
4(5)
5(6)
4(5)
5(6)
DSBC
1
2
3(4)
3
4(5)
4(5)
4(5)
5(6)
4(5)
5(6)
ADD
1
2
3(4)
3
4(5)
2(3)
4(5)
5(6)
4(5)
5(6)
MULT
1
2
3(4)
3
4(5)
2(3)
4(5)
5(6)
4(5)
5(6)
DIV
1
2
3(4)
3
4(5)
2(3)
4(5)
5(6)
4(5)
5(6)
DIVD
1
2
3(4)
3
4(5)
4(5)
5(6)
4(5)
5(6)
IFEQ
1
2
3(4)
3
4(5)
2(3)
4(5)
5(6)
4(5)
5(6)
IFGT
1
2
3(4)
3
4(5)
2(3)
4(5)
5(6)
4(5)
5(6)
AND
1
2
3(4)
3
4(5)
2(3)
4(5)
5(6)
4(5)
5(6)
OR
1
2
3(4)
3
4(5)
2(3)
4(5)
5(6)
4(5)
5(6)
XOR
1
2
3(4)
3
4(5)
2(3)
4(5)
5(6)
4(5)
5(6)
8-bit direct address
16-bit direct address
Instructions that Modify Memory Directly
(B)
(X)
Direct
Indir
Index
B X
SBIT
1
2
3(4)
3
4(5)
1
RBIT
1
2
3(4)
3
4(5)
1
IFBIT
1
2
3(4)
3
4(5)
1
DECSZ
3
2
2(4)
3
4(5)
INC
3
2
2(4)
3
4(5)
Immediate Load Instructions
Immed
LD B
2(3)
LD X
2(3)
LD K
2(3)
LD BK
3(5)
Register Indirect Instructions with
Auto Increment and Decrement
Register B With Skip
(B
a
)
(B
b
)
LDS A
1
1
XS A
1
1
Register X
(X
a
)
(X
b
)
LD A
1
1
X A
1
1
Instructions Using A and C
CLR
A
1
INC
A
1
DEC
A
1
COMP
A
1
SWAP
A
1
RRC
A
1
RLC
A
1
SHR
A
1
SHL
A
1
SC
1
RC
1
IFC
1
IFNC
1
Transfer of Control Instructions
JSRP
1
JSR
2
JSRL
3
JP
1
JMP
2
JMPL
3
JID
1
JIDW
1
NOP
1
RET
1
RETSK
1
RETI
1
Stack Reference Instructions
Direct
PUSH
2
POP
2
33
Code Efficiency
One of the most important criteria of a single chip microcon-
troller is code efficiency The more efficient the code the
more features that can be put on a chip The memory size
on a chip is fixed so if code is not efficient features may
have to be sacrificed or the programmer may have to buy a
larger more expensive version of the chip
The HPC46164 has been designed to be extremely code-
efficient The HPC46164 looks very good in all the standard
coding benchmarks however it is not realistic to rely only
on benchmarks Many large jobs have been programmed
onto the HPC46164 and the code savings over other popu-
lar microcontrollers has been considerable
Reasons for this saving of code include the following
SINGLE BYTE INSTRUCTIONS
The majority of instructions on the HPC46164 are single-
byte There are two especially code-saving instructions JP
is a 1-byte jump True it can only jump within a range of plus
or minus 32 but many loops and decisions are often within
a small range of program memory Most other micros need
2-byte instructions for any short jumps
JSRP is a 1-byte call subroutine The user makes a table of
the 16 most frequently called subroutines and these calls
will only take one byte Most other micros require two and
even three bytes to call a subroutine The user does not
have to decide which subroutine addresses to put into this
table the assembler can give this information
EFFICIENT SUBROUTINE CALLS
The 2-byte JSR instructions can call any subroutine within
plus or minus 1k of program memory
MULTIFUNCTION INSTRUCTIONS FOR DATA
MOVEMENT AND PROGRAM LOOPING
The HPC46164 has single-byte instructions that perform
multiple tasks For example the XS instruction will do the
following
1 Exchange A and memory pointed to by the B register
2 Increment or decrement the B register
3 Compare the B register to the K register
4 Generate a conditional skip if B has passed K
The value of this multipurpose instruction becomes evident
when looping through sequential areas of memory and exit-
ing when the loop is finished
BIT MANIPULATION INSTRUCTIONS
Any bit of memory I O or registers can be set reset or
tested by the single byte bit instructions The bits can be
addressed directly or indirectly Since all registers and I O
are mapped into the memory it is very easy to manipulate
specific bits to do efficient control
DECIMAL ADD AND SUBTRACT
This instruction is needed to interface with the decimal user
world
It can handle both 16-bit words and 8-bit bytes
The 16-bit capability saves code since many variables can
be stored as one piece of data and the programmer does
not have to break his data into two bytes Many applications
store most data in 4-digit variables The HPC46164 supplies
8-bit byte capability for 2-digit variables and literal variables
MULTIPLY AND DIVIDE INSTRUCTIONS
The HPC46164 has 16-bit multiply 16-bit by 16-bit divide
and 32-bit by 16-bit divide instructions This saves both
code and time Multiply and divide can use immediate data
or data from memory The ability to multiply and divide by
immediate data saves code since this function is often
needed for scaling base conversion computing indexes of
arrays etc
Development Support
HPC MICROCONTROLLER DEVELOPMENT SYSTEM
The HPC microcontroller development system is an in-sys-
tem emulator (ISE) designed to support the entire family of
HPC Microcontrollers The complete package of hardware
and software tools combined with a host system provides a
powerful system for design development and debug of HPC
based designs Software tools are available for IBM PC-AT
(MS-DOS PC-DOS) and for Unix based multi-user Sun
SparcStation (SunOS
TM
)
The stand alone units comes complete with a power supply
and external emulation POD This unit can be connected to
various host systems through an RS-232 link The software
package includes an ANSI compatible C-Compiler Linker
Assembler and librarian package Source symbolic debug
capability is provided through a user friendly MS-windows
3 0 interface for IBM PC-AT environment and through a line
debugger under Sunview for Sun SparcStations
The ISE provides fully transparent in-system emulation at
speeds up to 20 MHz 1 waitstate A 2k word (48-bit wide)
trace buffer gives trace trigger and non intrusive monitoring
of the system External triggering is also available through
an external logic interface socket on the POD Direct
EPROM programming can be done through the use of ex-
ternally mounted EPROM socket Form-Fit-Function emula-
tor programming is supported by a programming board in-
cluded with the system Comprehensive on-line help and
diagnostics features reduced user's design and debug time
8 hardware breakpoints (Address range) 64 kbytes of user
memory and break on external events are some of the oth-
er features offered
Hewlett Packard model HP64775 Emulator Analyzer pro-
viding in-system emulation for up to 30 MHz 1 waitstate is
also available Contact your local sales office for technical
details and support
34
Development Support
(Continued)
Development Tools Selection Table
Product
Order
Description
Includes
Manual
Part Number
Number
HPC16104
HPC-DEV-ISE4
HPC In-System Emulator
HPC MDS User's Manual
420420184-001
16164
HPC-DEV-ISE-E
HPC In-System Emulator
MDS Comm User's Manual
424420188-001
for Europe and South
HPC Emulator Programmer
420421313-001
East Asia
HPC16104 16164 Manual
HPC-DEV-IBMA
Assembler Linker
HPC Assembler Linker
424410836-001
Library Package
Librarian User's Manual
for IBM PC-AT
HPC-DEV-IBMC
C Compiler Assembler
HPC C Compiler User's Manual
424410883-001
Linker Library
Package for IBM PC-AT
HPC Assembler Linker Library
424410836-001
User's Manual
HPC-DEV-WDBC
Source Symbolic Debugger for
Source Symbolic Debugger
424420189-001
IBM PC-AT
User's Manual
C Compiler Assembler Linker
HPC C Compiler User's Manual
424410883-001
Library Package for IBM PC-AT
HPC Assembler Linker Library
424410836-001
User's Manual
HPC-DEV-SUNC
C Compiler Assembler Linker
HPC Compiler User's Manual
Library Package for Sun
HPC Assembler Linker Library
SparcStation
User's Manual
HPC-DEV-SUNDB
Source Symbolic Debugger for
Source Symbolic Debugger
Sun SparcStation
User's Manual
C Compiler Assembler Linker
HPC C Compiler User's Manual
Library Package
HPC Assembler Linker Library
User's Manual
Complete System
16164
HPC16104
HPC-DEV-SYS4
HPC In-System Emulator with
C Compiler Assembler
Linker Library and Source
Symbolic Debugger
HPC-DEV-SYS4-E
Same for Europe and South
East Asia
How to Order
To order a complete development package select the sec-
tion for the microcontroller to be developed and order the
parts listed
DIAL-A-HELPER
Dial-A-Helper is a service provided by the Microcontroller
Applications group Dial-A-Helper is an Electronic Bulletin
Board Information system and additionally provides the ca-
pability of remotely accessing the development system at a
customer site
INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be ac-
cessed over standard dial-up telephone lines 24 hours a
day The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Micro-
controller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities can be found The minimum require-
ment for accessing Dial-A-Helper is a Hayes compatible mo-
dem
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use
Order P N MDS-DIAL-A-HLP
Information System Package Contains
Dial-A-Helper Users Manual
Public Domain Communications Software
35
FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications support If a user is having difficulty in operating a MDS he can
leave messages on our electronic bulletin board which we will respond to
Voice
(408) 721-5582
Modem (408) 739-1162
Baud
300 or 1200 baud
Set-Up
Length
8-Bit
Parity
None
Stop Bit 1
Operation 24 Hrs 7 Days
DIAL-A-HELPER
TL DD 9682 37
Part Selection
The HPC family includes devices with many different options and configurations to meet various application needs The
number HPC46164 has been generically used throughout this datasheet to represent the whole family of parts The follow-
ing chart explains how to order various options available when ordering HPC family members
Note
All options may not currently be available
TL DD 9682 46
36
37
HPC3616446164
HPC3610446104
High-Performance
microController
with
AD
Physical Dimensions
inches (millimeters)
Plastic Flat Quad Package (VF)
Order Number HPC46064XXX F20 HPC46064XXX F30
HPC46004VF20 or HPC46004VF30
NS Package Number VF80B
LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein
1 Life support devices or systems are devices or
2 A critical component is any component of a life
systems which (a) are intended for surgical implant
support device or system whose failure to perform can
into the body or (b) support or sustain life and whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system or to affect its safety or
with instructions for use provided in the labeling can
effectiveness
be reasonably expected to result in a significant injury
to the user
National Semiconductor
National Semiconductor
National Semiconductor
National Semiconductor
Corporation
Europe
Hong Kong Ltd
Japan Ltd
1111 West Bardin Road
Fax (a49) 0-180-530 85 86
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Tel 81-043-299-2309
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Fax 81-043-299-2408
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Tel (852) 2737-1600
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Fax (852) 2736-9960
National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
This datasheet has been download from:
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