TL DD10422
HPC36400EHPC46400E
High-Performance
Communications
MicroController
PRELIMINARY
November 1992
HPC36400E HPC46400E
High-Performance Communications MicroController
General Description
The HPC46400E is an upgraded HPC16400 Features have
been added to support V 120 the 8-bit mode has been en-
hanced to support all instructions and the UART has been
changed to provide more flexibility and power
The
HPC46400E is fully upward compatible with the HPC16400
The HPC46400E has 4 functional blocks to support a wide
range of communication application-2 HDLC channels 4
channel DMA controller to facilitate data flow for the HDLC
channels programmable serial interface and UART
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-to-
point and multipoint data exchanges The decoder gener-
ates enable signals for the HDLC channels allowing multi-
plexed D and B channel data to be accessed
The HDLC channels manage the link by providing sequenc-
ing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC) Multiple address
recognition modes and both bit and byte modes of opera-
tion are supported
The HPC36400E and HPC46400E are available in 68-pin
PLCC and 80-pin PQFP packages
Features
Y
HPC
TM
family
core features
16-bit data bus ALU and registers
64 kbytes of external memory addressing
FAST
20 0 MHz system clock
Four 16-bit timer counters with WATCHDOG
TM
logic
MICROWIRE PLUS
TM
serial I O interface
CMOS
low power with two power save modes
Y
Two full duplex HDLC channels
Optimized for ISDN X 25 V 120 and LAPD
applications
Programmable frame address recognition
Up to 4 65 Mbps serial data rate
Built in diagnostics
Synchronous bypass mode
Optional CRC generation
Received CRC bytes can be read by the CPU
Y
Four channel DMA controller
Y
8- or 16-bit external data bus
Y
UART
Full duplex
7 8 or 9 data bits
Even odd mark space or no parity
7 8 1 or 2 stop bit generation
Accurate internal baud rate generation up to 625k
baud without penalty of using expensive crystal
Synchronous and asynchronous modes of operation
Y
Serial Decoder
Supports 6 popular time division multiplexing proto-
cols for inter-chip communications
Optional rate adaptation of 64 kbit s data rate to
56 kbit s
Y
Over
Mbyte of extended addressing
Y
Easy interface to National's DASL `U' and `S' trans-
ceivers
TP3400 TP3410 and TP3420
Y
Commercial (0 C to
a
70 C) and industrial (
b
40 C to
a
85 C)
Block Diagram
TL DD 10422 1
TapePak
and TRI-STATE
are registered trademarks of National Semiconductor Corporation
HPC
TM
MICROWIRE PLUS
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation
IBM
PC-AT
are registered trademarks of International Business Machines Corporation
Sun
is a registered trademark of Sun Microsystems
SunOS
TM
is a trademark of Sun Microsystems
UNIX
is a registered trademark of AT T Bell Laboratories
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Total Allowable Source or Sink Current
100 mA
Storage Temperature Range
b
65 C to
a
150 C
Lead Temperature (Soldering 10 sec )
300 C
V
CC
with Respect to GND
b
0 5V to 7 0V
All Other Pins
(V
CC
a
0 5)V to (GND
b
0 5)V
Note
Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics
V
CC
e
5 0V
g
10% unless otherwise specified T
A
e
0 C to
a
70 C for
HPC46400E
b
40 C to
a
85 C for HPC36400E
Symbol
Parameter
Test Conditions
Min
Max
Units
I
CC1
Supply Current
V
CC
e
5 5V f
in
e
20 0 MHz (Note 1)
70
mA
V
CC
e
5 5V f
in
e
2 0 MHz (Note 1)
10
mA
I
CC2
IDLE Mode Current
V
CC
e
5 5V f
in
e
20 0 MHz (Note 1)
10
mA
V
CC
e
5 5V f
in
e
2 0 MHz (Note 1)
2
mA
I
CC3
HALT Mode Current
V
CC
e
5 5V f
in
e
0 kHz (Note 1)
500
m
A
V
CC
e
2 5V f
in
e
0 kHz (Note 1)
150
m
A
INPUT VOLTAGE LEVELS
SCHMITT TRIGGERED RESET WO D0 NMI I2 I3 AND ALSO CKI
V
IH1
Logic High
0 9 V
CC
V
V
IL1
Logic Low
0 1 V
CC
V
INPUT VOLTAGE LEVELS
PORT A
V
IH2
Logic High
2 0
V
V
IL2
Logic Low
0 8
V
INPUT VOLTAGE LEVELS
ALL OTHERS
V
IH3
Logic High
0 7 V
CC
V
V
IL3
Logic Low
0 2 V
CC
V
I
LI
Input Leakage Current
(Note 2)
g
1
m
A
C
I
Input Capacitance
(Note 3)
10
pF
C
IO
I O Capacitance
(Note 3)
20
pF
OUTPUT VOLTAGE LEVELS
V
OH1
Logic High (CMOS)
I
OH
e b
10 mA (Note 3)
V
CC
b
0 1
V
V
OL1
Logic Low (CMOS)
I
OL
e
10 mA (Note 3)
0 1
V
V
OH2
Port A B Drive CK2
I
OH
e b
1 mA
2 4
V
V
OL2
(A
0
A
15
B
10
B
11
B
12
B
15
)
I
OL
e
3 mA
0 4
V
V
OH3
Other Port Pin Drive WO (open drain)
I
OH
e b
1 6 mA (except WO)
2 4
V
V
OL3
(B
0
B
9
B
13
B
14
R
0
R
7
D
5
D
7
)
I
OL
e
0 5 mA
0 4
V
V
OH4
ST1 and ST2 Drive
I
OH
e b
6 mA
2 4
V
V
OL4
I
OL
e
1 6 mA (Note 4)
0 4
V
V
RAM
RAM Keep-Alive Voltage
(Note 5)
2 5
V
I
OZ
TRI-STATE Leakage Current
V
IN
e
0 and V
IN
e
V
CC
g
5
m
A
Note 1
I
CC1
I
CC2
I
CC3
measured with no external drive (I
OH
and I
OL
e
0 I
IH
and I
IL
e
0) I
CC1
is measured with RESET
e
V
SS
I
CC3
is measured with NMI
e
V
CC
CKI driven to V
IH1
and V
IL1
with rise and fall times less than 10 ns
Note 2
RDY HLD and RDY I4 pins have internal pullups and meet this spec only at V
IN
e
V
CC
Note 3
These parameters are guaranteed by design and are not tested
Note 4
ST2 drive will not meet this spec under condition of RESET pin
e
low
Note 5
Test duration is 100 ms
2
AC Electrical Characteristics
(see Notes 1 and 4 and
Figures 1 thru 5 ) V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for HPC46400E
b
40 C to
a
85 C for
HPC36400E
Symbol and Formula
Parameter and Notes
Min
Max
Units
Note
f
C
Operating Frequency
2
20
MHz
t
C1
e
1 f
C
Operating Period
50
500
ns
t
CKIH
CKI Rise Time
22 5
ns
t
CKIL
CKI Fall Time
22 5
ns
t
C
e
2 f
C
CPU or DMA Timing Cycle
100
ns
t
WAIT
e
t
C
CPU or DMA Wait State Period
100
ns
t
DC1C2R
Delay of CK2 Rising Edge after
0
55
ns
(Note 2)
CKI Falling Edge
t
DC1C2F
Delay of CK2 Falling Edge after
0
55
ns
(Note 2)
CKI Falling Edge
f
U
e
f
C
8
External UART Clock Input Frequency
2 5
MHz
f
MW
External MICROWIRE PLUS
1 25
MHz
Clock Input Frequency
t
HCK
e
4t
C1
a
14
HDLC Clock Input Period
214
ns
f
XIN
e
f
C
22
External Timer Input Frequency
0 91
kHz
t
XIN
e
t
C
Pulse Width for Timer Inputs
100
ns
t
UWS
MICROWIRE Setup Time
Master
100
ns
Slave
20
ns
t
UWH
MICROWIRE Hold Time
Master
20
ns
Slave
50
ns
t
UWV
MICROWIRE Output Valid Time
Master
50
ns
Slave
150
ns
t
SALE
e
t
C
a
40
HLD Falling Edge before ALE Rising Edge
115
ns
t
HWP
e
t
C
a
35
HLD Pulse Width
110
ns
t
HAE
e
t
C
a
100
HLDA Falling Edge after HLD Falling Edge
175
ns
(Note 3)
t
HAD
e
t
C
a
85
HLDA Rising Edge after HLD Rising Edge
210
ns
t
BF
Bus Float after HLDA Falling Edge
66
ns
t
BE
e
t
C
b
66
Bus Enable after HLDA Rising Edge
34
ns
Clocks
Timers
MICROWIRE
PLUS
External
Hold
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO Spec'd t
C1R
t
C1F
and CKI duty cycle limits are not tested but are guaranteed functional by design Keep in mind that when SLOW mode is selected f
C
(Operating Frequency) will be
the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics
Note 2
Do not design with this parameter unless CKI is driven with an active signal and SLOW mode is not selected When using a passive crystal circuit its
stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
t
HAE
is spec'd for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU or DMA cycle being executed If HLD
falling edge occurs later t
HAE
as long as (3 t
C
a
4 WS
a
72 t
C
a
100) may occur depending on the following CPU instruction or DMA cycle its wait states and
ready input
Note 4
WS (t
WAIT
)
c
(number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency f
C
e
20 MHz with
one wait state preprogrammed These values are guaranteed with AC loading of 100 pF on Port A 50 pF on CK2 80 pF on other outputs and DC loading of the
pin's DC spec non CMOS I
OL
or I
OH
3
AC Electrical Characteristics
(Continued)
CPU and DMA Timing (see Notes 1 and 4 and
Figures 2 4 6 7 8 and 9 ) V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for
HPC46400E
b
40 C to
a
85 C for HPC36400E
Symbol
Formula
Cycle
Parameter
Min
Max
Units
Note
t
1ALR
CPU
Delay of ALE Rising Edge after CKI Rising Edge
0
35
ns
(Note 2)
DMA
Delay of ALE Rising Edge after CKI Falling Edge
0
35
ns
(Note 2)
t
1ALF
CPU
Delay of ALE Falling Edge after CKI Rising Edge
0
35
ns
(Note 2)
DMA
Delay of ALE Falling Edge after CKI Falling Edge
0
35
ns
(Note 2)
t
2ALR
t
C
a
20
CPU
ALE Rising Edge after CK2 Rising Edge
45
ns
t
2ALF
t
C
a
20
CPU
ALE Falling Edge after CK2 Falling Edge
45
ns
t
LL
t
C
b
9
ALE Pulse Width
41
ns
t
ST
t
C
b
20
Setup of Address Valid before ALE Falling Edge
5
ns
(Note 3)
t
VP
t
C
b
10
CPU
Hold of Address Valid after ALE Falling Edge
15
ns
t
C
b
10
DMA
40
ns
t
ARR
t
C
b
20
ALE Falling Edge to RD Falling Edge
30
ns
t
ACC
t
C
a
WS
b
55
CPU
Data Input Valid after Address Output Valid
145
ns
t
C
a
WS
b
75
DMA
150
ns
t
RD
t
C
a
WS
b
35
CPU
Data Input Valid after RD Falling Edge
90
ns
t
C
a
WS
DMA
115
ns
t
RW
t
C
a
WS
b
15
CPU
RD Pulse Width
110
ns
t
C
a
WS
b
15
DMA
135
ns
t
DR
t
C
b
25
Hold of Data Input Valid after RD Rising Edge
0
50
ns
t
RDA
t
C
b
20
Bus Enable after RD Rising Edge
55
ns
t
ARW
t
C
b
20
ALE Falling Edge to WR Falling Edge
30
ns
t
WW
t
C
a
WS
b
15
CPU
WR Pulse Width
160
ns
t
C
a
WS
b
15
DMA
135
ns
t
V
t
C
a
WS
b
40
CPU
Data Output Valid before WR Rising Edge
110
ns
t
C
a
WS
b
50
DMA
100
ns
t
HW
t
C
b
10
Hold of Data Output Valid after WR Rising Edge
15
ns
(Note 5)
t
RDYS
RDY Falling Edge before CK2 Rising Edge
45
ns
t
RDYH
RDY Rising Edge after CK2 Rising Edge
0
ns
t
RDYV
WS
b
t
C
b
47
CPU
RDY Falling Edge after RD or WR Falling Edge
28
ns
(Note 6)
t
C
b
47
DMA
53
ns
Address
Cycles
Read
Cycles
Write
Cycles
Ready
Input
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO Spec'd t
C1R
t
C1F
and CKI duty cycle limits are not tested but are guaranteed functional by design Keep in mind that when SLOW mode is selected f
C
(Operating Frequency) will be
the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics
Note 2
Do not design with this parameter unless CKI is driven with an active signal meeting T
C1R
and T
C1F
specs When using a passive crystal circuit its stability
is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
Setup of HBE valid before ALE falling edge is 0 ns minimum Setup of BS0 thru BS3 valid before ALE falling edge when in extended addressing mode is
0 ns minimum
Note 4
WS (t
WAIT
)
c
(number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency f
C
e
20 MHz with
one wait state preprogrammed These values are guaranteed with AC loading of 100 pF on Port A 50 pF on CK2 80 pF on other outputs and DC loading of the
pin's DC spec non CMOS I
OL
or I
OH
Note 5
Hold of HBE Output Valid after WR rising edge is 0 ns minimum Hold of BS0 thru BS3 Output Valid after WR rising edge when in extended addressing
mode is 0 ns minimum
Note 6
In HPC in-circuit emulators the t
RDYV
formulas are WS
b
t
C
b
57 and t
C
b
57 yielding minimums of 18 ns and 43 ns for CPU and DMA cycles
respectively
4
Timing Waveforms
Rise Fall Time
TL DD 10422 2
Duty Cycle
TL DD 10422 3
FIGURE 1 CKI Input Signal
TL DD 10422 4
Note
AC testing inputs are driven at V
IH
for a logic ``1'' and V
IL
for a logic ``0'' Output timing measurements are made at 2 0V for a logic ``1'' and at 0 8V for a logic
``0''
FIGURE 2 Input and Output for AC Tests
TL DD 10422 5
FIGURE 3 MICROWIRE Setup Hold Timing
TL DD 10422 6
FIGURE 4 CKI CK2 ALE Timing Diagram
TL DD 10422 7
FIGURE 5 External Hold Timing
5
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