TL DD11372
HPC1606426064360644606416004260043600446004High-Performance
microController
May 1992
HPC16064 26064 36064 46064 16004 26004
36004 46004 High-Performance microController
General Description
The HPC46064 and HPC46004 are members of the HPC
TM
family of High Performance microControllers Each member
of the family has the same core CPU with a unique memory
and I O configuration to suit specific applications The
HPC46064 has 16k bytes of on-chip ROM The HPC46004
has no on-chip ROM and is intended for use with external
memory Each part is fabricated in National's advanced
microCMOS technology This process combined with an ad-
vanced architecture provides fast flexible I O control effi-
cient data manipulation and high speed computation
The HPC devices are complete microcomputers on a single
chip All system timing internal logic ROM RAM and I O
are provided on the chip to produce a cost effective solution
for high performance applications On-chip functions such
as UART up to eight 16-bit timers with 4 input capture regis-
ters vectored interrupts WATCHDOG
TM
logic and MICRO-
WIRE PLUS
TM
provide a high level of system integration
The ability to address up to 64k bytes of external memory
enables the HPC to be used in powerful applications typical-
ly performed by microprocessors and expensive peripheral
chips The term ``HPC46064'' is used throughout this data-
sheet to refer to the HPC46064 and HPC46004 devices un-
less otherwise specified
The microCMOS process results in very low current drain
and enables the user to select the optimum speed power
product for his system The IDLE and HALT modes provide
further current savings The HPC is available in 68-pin
PLCC LDCC PGA and 80-pin PQFP package
Features
Y
HPC family
core features
16-bit architecture both byte and word
16-bit data bus ALU and registers
64k bytes of external direct memory addressing
FAST
200 ns for fastest instruction when using
20 0 MHz clock 134 ns at 30 0 MHz
High code efficiency
most instructions are single
byte
16 x 16 multiply and 32 x 16 divide
Eight vectored interrupt sources
Four 16-bit timer counters with 4 synchronous out-
puts and WATCHDOG logic
MICROWIRE PLUS serial I O interface
CMOS
very low power with two power save modes
IDLE and HALT
Y
UART
full duplex programmable baud rate
Y
Four additional 16-bit timer counters with pulse width
modulated outputs
Y
Four input capture registers
Y
52 general purpose I O lines (memory mapped)
Y
16k bytes of ROM 512 bytes of RAM on-chip
Y
ROMless version available (HPC46004)
Y
Commercial (0 C to
a
70 C)
industrial (
b
40 C to
a
85 C) automotive (
b
40 C to
a
105 C) and military
(
b
55 C to
a
125 C) temperature ranges
Block Diagram
(HPC46064 with 16k ROM shown)
TL DD 11372 1
Series 32000
and TRI-STATE
are registered trademarks of National Semiconductor Corporation
MOLE
TM
HPC
TM
COPS
TM
microcontrollers WATCHDOG
TM
and MICROWIRE PLUS
TM
are trademarks of National Semiconductor Corporation
IBM
and PC-AT
are registered trademarks of International Business Machines Corporation
Sun
is a registered trademark of Sun Microsystems
SunOS
TM
is a trademark of Sun Microsystems
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Total Allowable Source or Sink Current
100 mA
Storage Temperature Range
b
65 C to
a
150 C
Lead Temperature (Soldering 10 sec )
300 C
V
CC
with Respect to GND
b
0 5V to 7 0V
All Other Pins
(V
CC
a
0 5)V to (GND
b
0 5)V
Note
Absolute maximum ratings indicate limits beyond
which damage to the device may occur DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings
DC Electrical Characteristics
V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for HPC46064 46004
b
40 C to
a
85 C for HPC36064 36004
b
40 C to
a
105 C for
HPC26064 26004
b
55 C to
a
125 C for HPC16064 16004
Symbol
Parameter
Test Conditions
Min
Max
Units
I
CC1
Supply Current
V
CC
e
5 5V f
in
e
30 MHz (Note 1)
65
mA
V
CC
e
5 5V f
in
e
20 MHz (Note 1)
47
mA
V
CC
e
5 5V f
in
e
2 0 MHz (Note 1)
10
mA
I
CC2
IDLE Mode Current
V
CC
e
5 5V f
in
e
30 MHz (Note 1)
5
mA
V
CC
e
5 5V f
in
e
20 MHz (Note 1)
3 0
mA
V
CC
e
5 5V f
in
e
2 0 MHz (Note 1)
1
mA
I
CC3
HALT Mode Current
V
CC
e
5 5V f
in
e
0 kHz (Note 1)
300
m
A
V
CC
e
2 5V f
in
e
0 kHz (Note 1)
100
m
A
INPUT VOLTAGE LEVELS FOR SCHMITT TRIGGERED INPUTS RESET NMI AND WO AND ALSO CKI
V
IH1
Logic High
0 9 V
CC
V
V
IL1
Logic Low
0 1 V
CC
V
ALL OTHER INPUTS
V
IH2
Logic High
0 7 V
CC
V
V
IL2
Logic Low
0 2 V
CC
V
I
LI1
Input Leakage Current
V
IN
e
0 and V
IN
e
V
CC
g
2
m
A
I
LI2
Input Leakage Current RDY HLD EXUI
V
IN
e
0
b
3
b
50
m
A
I
LI3
Input Leakage Current B12
RESET
e
0 V
IN
e
V
CC
0 5
7
m
A
C
I
Input Capacitance
(Note 2)
10
pF
C
IO
I O Capacitance
(Note 2)
20
pF
OUTPUT VOLTAGE LEVELS
V
OH1
Logic High (CMOS)
I
OH
e b
10 mA (Note 2)
V
CC
b
0 1
V
V
OL1
Logic Low (CMOS)
I
OH
e
10 mA (Note 2)
0 1
V
V
OH2
Port A B Drive CK2
I
OH
e b
7 mA
2 4
V
V
OL2
(A
0
A
15
B
10
B
11
B
12
B
15
)
I
OL
e
3 mA
0 4
V
V
OH3
Other Port Pin Drive WO (open
I
OH
e b
1 6 mA (except WO)
2 4
V
V
OL3
drain) (B
0
B
9
B
13
B
14
P
0
P
3
)
I
OL
e
0 5 mA
0 4
V
V
OH4
ST1 and ST2 Drive
I
OH
e b
6 mA
2 4
V
V
OL4
I
OL
e
1 6 mA
0 4
V
V
OH5
Port A B Drive (A
0
A
15
B
10
B
11
B
12
B
15
) When
I
OH
e b
1 mA
2 4
V
Used as External Address Data Bus
V
OL5
I
OL
e
3 mA
0 4
V
V
RAM
RAM Keep-Alive Voltage
(Note 3)
2 5
V
CC
V
I
OZ
TRI-STATE Leakage Current
V
IN
e
0 and V
IN
e
V
CC
g
5
m
A
Note 1
I
CC1
I
CC2
I
CC3
measured with no external drive (I
OH
and I
OL
e
0 I
IH
and I
IL
e
0) I
CC1
is measured with RESET
e
V
SS
I
CC3
is measured with NMI
e
V
CC
CKI driven to V
IH1
and V
IL1
with rise and fall times less than 10 ns
Note 2
This is guaranteed by design and not tested
Note 3
Test duration is 100 ms
2
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 through Figure 5 ) V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for HPC46064 46004
b
40 C to
a
85 C for HPC36064 36004
b
40 C to
a
105 C for HPC26064 26004
b
55 C to
a
125 C for HPC16064 16004
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
C
CKI Operating Frequency
2
20
MHz
t
C1
e
1 f
C
CKI Clock Period
50
500
ns
t
CKIH
CKI High Time
22 5
ns
t
CKIL
CKI Low Time
22 5
ns
t
C
e
2 f
C
CPU Timing Cycle
100
ns
t
WAIT
e
t
C
CPU Wait State Period
100
ns
t
DC1C2R
Delay of CK2 Rising Edge 2fter CKI Falling Edge
0
55
ns
(Note 2)
t
DC1C2F
Delay of CK2 Falling Edge after CKI Falling Edge
0
55
ns
(Note 2)
f
U
e
f
C
8
External UART Clock Input Frequency
2 5
MHz
f
MW
External MICROWIRE PLUS Clock Input Frequency
1 25
MHz
f
XIN
e
f
C
22
External Timer Input Frequency
0 91
MHz
t
XIN
e
t
C
Pulse Width for Timer Inputs
100
ns
t
UWS
MICROWIRE Setup Time
Master
100
ns
Slave
20
t
UWH
MICROWIRE Hold Time
Master
20
ns
Slave
50
t
UWV
MICROWIRE Output Valid Time
Master
50
ns
Slave
150
t
SALE
e
t
C
a
40
HLD Falling Edge before ALE Rising Edge
115
ns
t
HWP
e
t
C
a
10
HLD Pulse Width
110
ns
t
HAE
e
t
C
a
100
HLDA Falling Edge after HLD Falling Edge
200
ns
(Note 3)
t
HAD
e
t
C
a
85
HLDA Rising Edge after HLD Rising Edge
160
ns
t
BF
e
t
C
a
66
Bus Float after HLDA Falling Edge
116
ns
(Note 5)
t
BE
e
t
C
a
66
Bus Enable after HLDA Rising Edge
116
ns
(Note 5)
t
UAS
Address Setup Time to Falling Edge of URD
10
ns
t
UAH
Address Hold Time from Rising Edge of URD
10
ns
t
RPW
URD Pulse Width
100
ns
t
OE
URD Falling Edge to Output Data Valid
0
60
ns
t
OD
Rising Edge of URD to Output Data Invalid
5
35
ns
(Note 6)
t
DRDY
RDRDY Delay from Rising Edge of URD
70
ns
t
WDW
UWR Pulse Width
40
ns
t
UDS
Input Data Valid before Rising Edge of UWR
10
ns
t
UDH
Input Data Hold after Rising Edge of UWR
20
ns
t
A
WRRDY Delay from Rising Edge of UWR
70
ns
Clocks
Timers
MICROWIREPLUS
External
Hold
UPI
Timing
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock
3
20 MHz
(Continued)
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 through Figure 5 ) V
CC
e
5V
g
10% T
A
e
0 C to
a
70 C for HPC46064 46004
b
40 C to
a
85 C for HPC36064 36004
b
40 C to
a
105 C for HPC26064 26004
b
55 C to
a
125 C for HPC16064 16004
Symbol and Formula
Parameter
Min
Max
Units
Notes
t
DC1ALER
Delay from CKI Rising Edge to
0
35
ns
(Notes 1 2)
ALE Rising Edge
t
DC1ALEF
Delay from CKI Rising Edge to
0
35
ns
(Notes 1 2)
ALE Falling Edge
t
DC2ALER
e
t
C
a
20
Delay from CK2 Rising Edge to
45
ns
(Note 2)
ALE Rising Edge
t
DC2ALEF
e
t
C
a
20
Delay from CK2 Falling Edge to
45
ns
(Note 2)
ALE Falling Edge
t
LL
e
t
C
b
9
ALE Pulse Width
41
ns
t
ST
e
t
C
b
7
Setup of Address Valid before
18
ns
ALE Falling Edge
t
VP
e
t
C
b
5
Hold of Address Valid after
20
ns
ALE Falling Edge
t
ARR
e
t
C
b
5
ALE Falling Edge to RD Falling Edge
20
ns
t
ACC
e
t
C
a
WS
b
55
Data Input Valid after Address Output Valid
145
ns
(Note 6)
t
RD
e
t
C
a
WS
b
65
Data Input Valid after RD Falling Edge
85
ns
t
RW
e
t
C
a
WS
b
10
RD Pulse Width
140
ns
t
DR
e
t
C
b
15
Hold of Data Input Valid after
0
60
ns
RD Rising Edge
t
RDA
e
t
C
b
15
Bus Enable after RD Rising Edge
85
ns
t
ARW
e
t
C
b
5
ALE Falling Edge to WR Falling Edge
45
ns
t
WW
e
t
C
a
WS
b
15
WR Pulse Width
160
ns
t
V
e
t
C
a
WS
b
5
Data Output Valid before WR Rising Edge
145
ns
t
HW
e
t
C
b
5
Hold of Data Valid after WR Rising Edge
20
ns
t
DAR
e
t
C
a
WS
b
50
Falling Edge of ALE to
75
ns
Falling Edge of RDY
t
RWP
e
t
C
RDY Pulse Width
100
ns
Address
Cycles
Read
Cycles
Write
Cycles
Ready
Input
Note
C
L
e
40 pF
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
CKIR
and t
CKIL
) on CKI input less than 2 5 ns
Note 2
Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
t
HAE
is spec'd for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
edge occurs later t
HAE
may be as long as (3 t
C
a
4WS
a
72 t
C
a
100) may occur depending on the following CPU instruction cycles its wait states and ready
input
Note 4
WS (t
WAIT
)
c
(number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency t
C
e
20 MHz with
one wait state programmed
Note 5
Due to emulation restrictions
actual limits will be better
Note 6
This is guaranteed by design and not tested
4
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 through Figure 5 ) V
CC
e
5V
g
10% unless otherwise specified T
A
e
0 C to
a
70 C for
HPC46064 46004
b
40 C to
a
85 C for HPC36064 36004
b
40 C to
a
105 C for HPC26064 26004
b
55 C to
a
125 C for
HPC16064 16004
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
C
CKI Operating Frequency
2
30
MHz
t
C1
e
1 f
C
CKI Clock Period
33
500
ns
t
CKIH
CKI High Time
15
ns
t
CKIL
CKI Low Time
16 6
ns
t
C
e
2 f
C
CPU Timing Cycle
66
ns
t
WAIT
e
t
C
CPU Wait State Period
66
ns
t
DC1C2R
Delay of CK2 Rising Edge after CKI Falling Edge
0
55
ns
(Note 2)
t
DC1C2F
Delay of CK2 Falling Edge after CKI Falling Edge
0
55
ns
(Note 2)
f
U
e
f
C
8
External UART Clock Input Frequency
3 75
MHz
f
MW
External MICROWIRE PLUS Clock Input Frequency
1 875
MHz
f
XIN
e
f
C
22
External Timer Input Frequency
1 36
MHz
t
XIN
e
t
C
Pulse Width for Timer Inputs
66
ns
t
UWS
MICROWIRE Setup Time
Master
100
ns
Slave
20
t
UWH
MICROWIRE Hold Time
Master
20
ns
Slave
50
t
UWV
MICROWIRE Output Valid Time
Master
50
ns
Slave
150
t
SALE
e
t
C
a
40
HLD Falling Edge before ALE Rising Edge
90
ns
t
HWP
e
t
C
a
10
HLD Pulse Width
76
ns
t
HAE
e
t
C
a
85
HLDA Falling Edge after HLD Falling Edge
151
ns
(Note 3)
t
HAD
e
t
C
a
85
HLDA Rising Edge after HLD Rising Edge
135
ns
t
BF
e
t
C
a
66
Bus Float after HLDA Falling Edge
99
ns
(Note 5)
t
BE
e
t
C
a
66
Bus Enable after HLDA Rising Edge
99
ns
(Note 5)
t
UAS
Address Setup Time to Falling Edge of URD
10
ns
t
UAH
Address Hold Time from Rising Edge of URD
10
ns
t
RPW
URD Pulse Width
100
ns
t
OE
URD Falling Edge to Output Data Valid
0
60
ns
t
OD
Rising Edge of URD to Output Data Invalid
5
35
ns
(Note 6)
t
DRDY
RDRDY Delay from Rising Edge of URD
70
ns
t
WDW
UWR Pulse Width
40
ns
t
UDS
Input Data Valid before Rising Edge of UWR
10
ns
t
UDH
Input Data Hold after Rising Edge of UWR
20
ns
t
A
WRRDY Delay from Rising Edge of UWR
70
ns
Clocks
Timers
MICROWIREPLUS
External
Hold
UPI
Timing
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock
5
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