ADC12H030/ADC12H032/ADC12H034/ADC12H038,
ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D
Converters with MUX and Sample/Hold
General Description
The ADC12030, and ADC12H030 families are 12-bit plus
sign successive approximation A/D converters with serial I/O
and
configurable
input
multiplexers.
The
ADC12032/
ADC12H032,
ADC12034/ADC12H034
and
ADC12038/
ADC12H038 have 2, 4 and 8 channel multiplexers, respec-
tively. The differential multiplexer outputs and A/D inputs are
available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2
pins. The ADC12030/ADC12H030 has a two channel multi-
plexer with the multiplexer outputs and A/D inputs internally
connected. The ADC12030 family is tested with a 5 MHz
clock, while the ADC12H030 family is tested with an 8 MHz
clock. On request, these A/Ds go through a self calibration
process that adjusts linearity, zero and full-scale errors to
less than
1 LSB each.
The analog inputs can be configured to operate in various
combinations
of
single-ended,
differential,
or
pseudo-differential modes. A fully differential unipolar analog
input range (0V to +5V) can be accommodated with a single
+5V supply. In the differential modes, valid outputs are ob-
tained even when the negative inputs are greater than the
positive because of the 12-bit plus sign output data format.
The
serial
I/O
is
configured
to
comply
with
the
NSC MICROWIRE
TM
. For voltage references see the
LM4040 or LM4041.
Features
n
Serial I/O (MICROWIRE Compatible)
n
2, 4, or 8 channel differential or single-ended multiplexer
n
Analog input sample/hold function
n
Power down mode
n
Variable resolution and conversion rate
n
Programmable acquisition time
n
Variable digital output word length and format
n
No zero or full scale adjustment required
n
Fully tested and guaranteed with a 4.096V reference
n
0V to 5V analog input range with single 5V power
supply
n
No Missing Codes over temperature
Key Specifications
n
Resolution
12-bit plus sign
n
12-bit plus sign conversion time
-- ADC12H030 family
5.5 s (max)
-- ADC12030 family
8.8 s (max)
n
12-bit plus sign throughput time
-- ADC12H030 family
8.6 s (max)
-- ADC12030 family
14 s (max)
n
Integral linearity error
1 LSB (max)
n
Single supply
5V
10%
n
Power dissipation
33 mW (max)
-- Power down
100 W (typ)
Applications
n
Medical instruments
n
Process control systems
n
Test equipment
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
COPS
TM
microcontrollers, HPC
TM
and MICROWIRE
TM
are trademarks of National Semiconductor Corporation.
July 1999
ADC12H030/ADC12H032/ADC12H034/ADC12H038,
ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating
12-Bit
Plus
Sign
Serial
I/O
A/D
Converters
with
MUX
and
Sample/Hold
1999 National Semiconductor Corporation
DS011354
www.national.com
ADC12038 Simplified Block Diagram
Connection Diagrams
DS011354-1
16-Pin Wide Body
SO Packages
DS011354-6
Top View
20-Pin Wide Body
SO Packages
DS011354-7
Top View
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2
Connection Diagrams
(Continued)
Ordering Information
Industrial Temperature Range
Package
-40C
T
A
+85C
ADC12H030CIWM, ADC12030CIWM
M16B
ADC12H032CIWM, ADC12032CIWM
M20B
ADC12H034CIN, ADC12034CIN
N24C
ADC12H034CIWM, ADC12034CIWM
M24B
ADC12H038CIWM, ADC12038CIWM
M28B
Pin Descriptions
CCLK
The clock applied to this input controls the
sucessive approximation conversion time
interval and the acquisition time. The rise
and fall times of the clock edges should not
exceed 1 s.
SCLK
This is the serial data clock input. The clock
applied to this input controls the rate at
which the serial data exchange occurs. The
rising edge loads the information on the DI
pin into the multiplexer address and mode
select shift register. This address controls
which channel of the analog input multi-
plexer (MUX) is selected and the mode of
operation for the A/D. With CS low the fall-
ing edge of SCLK shifts the data resulting
from the previous ADC conversion out on
DO, with the exception of the first bit of data.
When CS is low continously, the first bit of
the data is clocked out on the rising edge of
EOC (end of conversion). When CS is
toggled the falling edge of CS always clocks
out the first bit of data. CS should be
brought low when SCLK is low. The rise and
fall times of the clock edges should not ex-
ceed 1 s.
DI
This is the serial data input pin. The data ap-
plied to this pin is shifted by the rising edge
of SCLK into the multiplexer address and
mode select register.
Table 2 through Table
5 show the assignment of the multiplexer
address and the mode select data.
DO
The data output pin. This pin is an active
push/pull output when CS is low. When CS
is high, this output is TRI-STATE. The A/D
conversion result (D0D12) and converter
status data are clocked out by the falling
edge of SCLK on this pin. The word length
and format of this result can vary (see
Table
1). The word length and format are con-
trolled by the data shifted into the multi-
plexer address and mode select register
(see
Table 5).
EOC
This pin is an active push/pull output and in-
dicates the status of the ADC12030/2/4/8.
When low, it signals that the A/D is busy with
a conversion, auto-calibration, auto-zero or
power down cycle. The rising edge of EOC
signals the end of one of these cycles.
CS
This is the chip select pin. When a logic low
is applied to this pin, the rising edge of
SCLK shifts the data on DI into the address
register. This low also brings DO out of
TRI-STATE. With CS low the falling edge of
SCLK shifts the data resulting from the pre-
vious ADC conversion out on DO, with the
24-Pin Wide Body
SO Packages
DS011354-8
Top View
28-Pin Wide Body
SO Packages
DS011354-9
Top View
www.national.com
3
Pin Descriptions
(Continued)
exception of the first bit of data. When CS is
low continously, the first bit of the data is
clocked out on the rising edge of EOC (end
of conversion). When CS is toggled the fall-
ing edge of CS always clocks out the first bit
of data. CS should be brought low when
SCLK is low. The falling edge of CS resets a
conversion in progress and starts the se-
quence for a new conversion. When CS is
brought back low during a conversion, that
conversion is prematurely terminated. The
data in the output latches may be corrupted.
Therefore, when CS is brought back low
during a conversion in progress the data
output at that time should be ignored. CS
may also be left continuously low. In this
case it is imperative that the correct number
of SCLK pulses be applied to the ADC in or-
der to remain synchronous. After the ADC
supply power is applied it expects to see 13
clock pulses for each I/O sequence. The
number of clock pulses the ADC expects is
the same as the digital output word length.
This word length can be modified by the
data shifted in on the DO pin.
Table 5 details
the data required.
DOR
This is the data output ready pin. This pin is
an active push/pull output. It is low when the
conversion result is being shifted out and
goes high to signal that all the data has
been shifted out.
CONV
A logic low is required on this pin to program
any mode or change the ADC's configura-
tion as listed in the Mode Programming
Table 5 such as 12-bit conversion, 8-bit con-
version, Auto Cal, Auto Zero etc. When this
pin is high the ADC is placed in the read
data only mode. While in the read data only
mode, bringing CS low and pulsing SCLK
will only clock out on DO any data stored in
the ADCs output shift register. The data on
DI will be neglected. A new conversion will
not be started and the ADC will remain in
the mode and/or configuration previously
programmed. Read data only cannot be
performed while a conversion, Auto-Cal or
Auto-Zero are in progress.
PD
This is the power down pin. When PD is
high the A/D is powered down; when PD is
low the A/D is powered up. The A/D takes a
maximum of 250 s to power up after the
command is given.
CH0CH7
These are the analog inputs of the MUX. A
channel input is selected by the address in-
formation at the DI pin, which is loaded on
the rising edge of SCLK into the address
register (See
Tables 2, 3, 4).
The voltage applied to these inputs should
not exceed V
A
+ or go below GND. Exceed-
ing this range on an unselected channel will
corrupt the reading of a selected channel.
COM
This pin is another analog input pin. It is
used as a pseudo ground when the analog
multiplexer is single-ended.
MUXOUT1,
MUXOUT2
These
are
the
multiplexer
output
pins.
A/DIN1, /DIN2 These are the converter input pins. MUX-
OUT1 is usually tied to A/DIN1. MUXOUT2
is usually tied to A/DIN2. If external circuitry
is placed between MUXOUT1 and A/DIN1,
or MUXOUT2 and A/DIN2 it may be neces-
sary to protect these pins. The voltage at
these pins should not exceed V
A
+
or go be-
low AGND (see
Figure 5).
V
REF
+
This is the positive analog voltage reference
input. In order to maintain accuracy, the
voltage range of V
REF
(V
REF
= V
REF
+ -
V
REF
-) is 1 V
DC
to 5.0 V
DC
and the voltage
at V
REF
+ cannot exceed V
A
+. See
Figure 6
for recommended bypassing.
V
REF
-
The negative voltage reference input. In or-
der to maintain accuracy, the voltage at this
pin must not go below GND or exceed V
A
+.
(See
Figure 6).
V
A
+, V
D
+
These are the analog and digital power sup-
ply pins. V
A
+
and V
D
+
are not connected to-
gether on the chip. These pins should be
tied to the same power supply and by-
passed separately (see
Figure 6). The oper-
ating voltage range of V
A
+ and V
D
+ is
4.5 V
DC
to 5.5 V
DC
.
DGND
This is the digital ground pin (see
Figure 6).
AGND
This is the analog ground pin (see
Figure 6).
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4
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltage
(V
+
= V
A
+ = V
D
+)
6.5V
Voltage at Inputs and Outputs
except CH0CH7 and COM
-0.3V to V
+
+0.3V
Voltage at Analog Inputs
CH0CH7 and COM
GND -5V to V
+
+5V
|V
A
+ - V
D
+|
300 mV
Input Current at Any Pin (Note 3)
30 mA
Package Input Current (Note 3)
120 mA
Package Dissipation at
T
A
= 25C (Note 4)
500 mW
ESD Susceptability (Note 5)
Human Body Model
1500V
Soldering Information
N Packages (10 seconds)
260C
SO Package (Note 6):
Vapor Phase (60 seconds)
215C
Infrared (15 seconds)
220C
Storage Temperature
-65C to +150C
Operating Ratings
(Notes 1, 2)
Operating Temperature Range
T
MIN
T
A
T
MAX
ADC12030CIWM,
ADC12H030CIWM,
ADC12032CIWM,
ADC12H032CIWM,
ADC12034CIN, ADC12034CIWM,
ADC12H034CIN,
ADC12H034CIWM,
ADC12038CIWM,
ADC12H038CIWM
-40C
T
A
+85C
Supply Voltage (V
+
= V
A
+ = V
D
+)
+4.5V to +5.5V
|V
A
+ - V
D
+|
100 mV
V
REF
+
0V to V
A
+
V
REF
-
0V to V
REF
+
V
REF
(V
REF
+ - V
REF
-)
1V to V
A
+
V
REF
Common Mode Voltage Range
0.1 V
A
+ to 0.6 V
A
+
A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 Voltage Range
0V to V
A
+
A/D IN Common Mode
Voltage Range
0V to V
A
+
Converter Electrical Characteristics
The following specifications apply for V
+
= V
A
+ = V
D
+ = +5.0 V
DC
, V
REF
+ = +4.096 V
DC
, V
REF
- = 0 V
DC
, 12-bit + sign conver-
sion mode, f
CK
= f
SK
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5 MHz for the
ADC12030, ADC12032, ADC12034 and ADC12038, R
S
= 25
, source impedance for V
REF
+ and V
REF
-
25
, fully-differential
input with fixed 2.048V common-mode voltage, and 10(t
CK
) acquisition time unless otherwise specified. Boldface limits apply
for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C. (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
Resolution with No
Missing Codes
12 + sign
Bits (min)
+ILE
Positive Integral Linearity Error
After Auto-Cal (Notes 12, 18)
1/2
1
LSB (max)
-ILE
Negative Integral Linearity Error
After Auto-Cal (Notes 12, 18)
1/2
1
LSB (max)
DNL
Differential Non-Linearity
After Auto-Cal
1
LSB (max)
Positive Full-Scale Error
After Auto-Cal (Notes 12, 18)
1/2
3.0
LSB (max)
Negative Full-Scale Error
After Auto-Cal (Notes 12, 18)
1/2
3.0
LSB (max)
Offset Error
After Auto-Cal (Notes 5, 18)
1/2
2
LSB (max)
V
IN
(+) = V
IN
(-) = 2.048V
DC Common Mode Error
After Auto-Cal (Note 15)
2
3.5
LSB (max)
TUE
Total Unadjusted Error
After Auto-Cal
1
LSB
(Notes 12, 13, 14)
Resolution with No
Missing Codes
8-bit + sign mode
8 + sign
Bits (min)
+INL
Positive Integral Linearity Error
8-bit + sign mode (Note 12)
1/2
LSB (max)
-INL
Negative Integral Linearity Error
8-bit + sign mode (Note 12)
1/2
LSB (max)
DNL
Differential Non-Linearity
8-bit + sign mode
3/4
LSB (max)
Positive Full-Scale Error
8-bit + sign mode (Note 12)
1/2
LSB (max)
Negative Full-Scale Error
8-bit + sign mode (Note 12)
1/2
LSB (max)
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