LM98555
CCD Driver
General Description
The LM98555 is a highly integrated driver circuit intended for
CCD driving applications. It combines 25 drivers of varying
drive strengths into one chip to provide a complete CCD
driving solution. Due to this one-chip integration, optimal
skew control is achieved for this demanding application.
Features
n
All CCD drivers integrated into one package
n
High strength drivers designed specifically for CCD
loads
n
Ability to scale clock driver strength
n
Skew specifications guaranteed
n
Separate input and output power supplies
n
CMOS process technology
n
64-pin TSSOP package with extended power handling
capability
Key Specifications
Supply Voltage
Inputs
3.0 to 5.5V
Drivers
4.5 to 5.8V
Maximum Output Skew
Between P1A
and P2A
outputs
0.5 ns
Maximum Power
Dissipation
2.0W
Functional Description
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
20126401
FIGURE 1. Functional Block Diagram
February 2006
LM98555
CCD
Driver
2006 National Semiconductor Corporation
DS201264
www.national.com
Pin Descriptions
Symbol
Pin
Type
Description
Driver inputs
P2B
IN
8
Input
CMOS logic input for the P2B driver.
RS
IN
9
Input
CMOS logic input for the RS driver.
CP
IN
10
Input
CMOS logic input for the CP driver.
P1A
IN
15
Input
CMOS logic input for the P1A ganged (8) driver set.
P2A
IN
18
Input
CMOS logic input for the P2A ganged (8) driver set.
SH
IN
21
Input
CMOS logic input for the SH ganged (3) driver set.
AFE
IN
22
Input
CMOS logic input for the AFE driver.
MCL
IN
23
Input
CMOS logic input for the MCL driver.
SHD
IN
24
Input
CMOS logic input for the SHD driver.
Driver Outputs
SHD
OUT
28
Output;
Low-Strength
Driver output for the SHD
IN
input signal.
MCL
OUT
30
Output;
Low-Strength
Driver output for the MCL
IN
input signal.
AFE
OUT
31
Output;
Low-Strength
Driver output for the AFE
IN
input signal.
CP
OUT
2
Output;
Low-Strength
Driver output for the CP
IN
input signal. Typically used to drive the Clamp
Gate input of the CCD.
RS
OUT
3
Output;
Low-Strength
Driver output for the RS
IN
input signal. Typically used to drive the Reset
Gate input of the CCD.
P2B
OUT
5
Output;
Low-Strength
Driver output for the P2B
IN
input signal.
P2A
OUT0
47
Output;
TRI-STATE
;
High-Strength
Ganged driver outputs for the P2A
IN
input. Typically the user may join
together these outputs to drive the
2 clock input of the CCD. Some of
these outputs may be disabled using the EN(1:0) inputs - see the
Functional Description section.
P2A
OUT1
46
P2A
OUT2
43
P2A
OUT3
42
P2A
OUT4
39
P2A
OUT5
38
P2A
OUT6
35
P2A
OUT7
34
P1A
OUT0
50
Output;
TRI-STATE;
High-Strength
Ganged driver outputs for the P1A
IN
input. Typically the user may join
together these outputs to drive the
1 clock input of the CCD. Some of
these outputs may be disabled using the EN(1:0) inputs - see the
Functional Description section.
P1A
OUT1
51
P1A
OUT2
54
P1A
OUT3
55
P1A
OUT4
58
P1A
OUT5
59
P1A
OUT6
62
P1A
OUT7
63
SH
OUT0
26
Output;
Low-Strength
Ganged driver outputs for the SH
IN
input signal. Typically used to drive the
Shift Gate input of the CCD.
SH
OUT1
27
SH
OUT2
6
Logic Inputs
EN0
11
Input
Driver enable control. Some of the P1A and P2A drivers can be disabled
using these inputs. See the Functional Description section.
EN1
12
LM98555
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
-0.5V to 6.2V
Package Power Rating at 25C
(Note 2)
2.0 Watts
Voltage on Any Input or Output Pin
-0.5V to V
DD
+0.5V
DC Input Current at Any Pin
25 mA
DC Package Input Current
50 mA
Storage Temperature
-65C to +150C
Lead temperature (Soldering, 10
sec.)
300C
ESD Susceptibility
Human Body Model
2000V
Machine Model
200V
Operating Conditions
Supply Voltage
V
DDI
+3.0V to +5.5V
Supply Voltage
V
DDO
+4.5V to +5.8V
Ambient Temperature (T
A
)
0 to 70C
Operating Frequency
30 MHz
Power Dissipation (Note 3)
2.0W
Package Thermal Resistances
Package
J-A
(Note 4)
J-PAD
(Thermal Pad)
64-Lead Exposed Pad TSSOP 36.8C / W 6.2C / W
DC Electrical Characteristics
The following specifications apply for GND = 0V, V
DDI
= 3.3V, V
DDO
= 5.0V, unless noted otherwise. Boldface limits apply for
T
A
= T
MIN
to T
MAX
; all other limits T
A
= 25C
Symbol
Parameter
Conditions
Min
Typical
Max
Units
I
I
Logic 1 Input Current
V
I
= V
DDI
-1
0.004
1
A
Logic 0 Input Current
V
I
= GND
I
-1
0.006
1
A
V
IT
Input Threshold
V
DDI
= 3.3V
1.41
1.57
1.75
V
Input Threshold
V
DDI
= 5.0V
2.48
V
Input Threshold Hysteresis
V
DDI
= 3.3V
-72
11
100
mV
V
IT
Input Threshold Variation
Between P1A, P2A inputs
-100
100
mV
R
O
Output Impedance P1A and
P2A Outputs
I
LOAD
= 525 mA
6.1
9.9
R
O
= (V
DDO
- V
O
)/I
OH
or
R
O
= V
O
/I
OL
R
O
Output Impedance All Other
Outputs
I
LOAD
= 280 mA
10.2
17.4
R
O
= (V
DDO
- V
O
)/I
OH
or
R
O
= V
O
/I
OL
AC Electrical Characteristics
The following specifications apply for GND = 0V, V
DDI
= 3.3V, V
DDO
= 5.0V, unless noted otherwise. Boldface limits apply for
T
A
= T
MIN
to T
MAX
; all other limits T
A
= 25C
Symbol
Parameter
Conditions
Min
Typical
Max
Units
t
PHL
Prop Delay: High-to-Low
P1A and P2A Outputs
CL = 220 pF, R
L
= 10
(Note 5)
3.06
4.6
6.55
ns
t
PHL
Prop Delay: High-to-Low
CP, RS, P2B Outputs
CL = 82 pF, R
L
= 10
(Note 5)
(Note 7)
4.1
ns
t
PLH
Prop Delay: Low-to-High
P1A and P2A Outputs
CL = 220 pF, R
L
= 10
(Note 6)
3.38
4.9
6.68
ns
t
PLH
Prop Delay: Low-to-High
CP, RS, P2B Outputs
CL = 82 pF, R
L
= 10
(Note 6)
(Note 7)
4.2
ns
t
SKEW
Prop Delay Skew High-to-Low
Between any P1A or P2A
Outputs on a Single Unit
C
L
= 220 pF, R
L
= 10
109
387
ps
Prop Delay Skew Low-to-High
157
490
Important Note: Not all drivers can be loaded to the highest specified load at the same time without violating the maximum power dissipation limit. The system
design must guarantee that the maximum power dissipation specification is never exceeded.
LM98555
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