LP2995
DDR Termination Regulator
General Description
The LP2995 linear regulator is designed to meet the JEDEC
SSTL-2 and SSTL-3 specifications for termination of DDR-
SDRAM. The device contains a high-speed operational am-
plifier to provide excellent response to load transients. The
output stage prevents shoot through while delivering 1.5A
continuous current and transient peaks up to 3A in the
application as required for DDR-SDRAM termination. The
LP2995 also incorporates a V
SENSE
pin to provide superior
load regulation and a V
REF
output as a reference for the
chipset and DDR DIMMS.
Patents Pending
Features
n
Low output voltage offset
n
Works with +5v, +3.3v and 2.5v rails
n
Source and sink current
n
Low external component count
n
No external resistors required
n
Linear topology
n
Available in SO-8, PSOP-8 or LLP-16 packages
n
Low cost and easy to use
Applications
n
DDR Termination Voltage
n
SSTL-2
n
SSTL-3
Typical Application Circuit
20039302
July 2003
LP2995
DDR
T
ermination
Regulator
2003 National Semiconductor Corporation
DS200393
www.national.com
Connection Diagrams
SO-8 (M08A) Package
LQA- 16 Package
20039320
Top View
20039304
Top View
PSOP-8 (MRA08A) Package
20039350
Top View
Pin Description
SO-8 Pin or
PSOP-8 Pin
LLP Pin
Name
Function
1
1,3,4,6,9, 13,16
NC
No internal connection. Can be used for vias.
2
2
GND
Ground.
3
5
VSENSE
Feedback pin for regulating VTT.
4
7
VREF
Buffered internal reference voltage of
VDDQ/2.
5
8
VDDQ
Input for internal reference equal to VDDQ/2.
6
10
AVIN
Analog input pin.
7
11, 12
PVIN
Power input pin.
8
14, 15
VTT
Output voltage for connection to termination
resistors.
Ordering Information
Order Number
Package Type
NSC Package
Drawing
Supplied As
LP2995M
SO-8
M08A
95 Units per Rail
LP2995MX
SO-8
M08A
2500 Units Tape and Reel
LP2995MR
PSOP-8
MRA08A
95 Units per Rail
LP2995MRX
PSOP-8
MRA08A
2500 Units Tape and Reel
LP2995LQ
LLP-16
LQA16A
1000 Units Tape and Reel
LP2995LQX
LLP-16
LQA16A
4500 Units Tape and Reel
LP2995
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
PVIN, AVIN, VDDQ to GND
-0.3V to +6V
Storage Temp. Range
-65C to +150C
Junction Temperature
150C
SO-8 Thermal Resistance (
JA
)
151C/W
LLP-16 Thermal Resistance (
JA
)
51C/W
Lead Temperature (Soldering, 10 sec)
260C
ESD Rating (Note 7)
1kV
Operating Range
Junction Temp. Range (Note 5)
0C to +125C
AVIN to GND
2.2V to 5.5V
PVIN to GND
2.2V to AVIN
Electrical Characteristics
Specifications with standard typeface are for T
J
= 25C and limits in boldface
type apply over the full Operating Temperature Range (T
J
= 0C to +125C). Unless otherwise specified,
AVIN = PVIN = 2.5V, VDDQ = 2.5V (Note 6).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
REF
V
REF
Voltage
I
REF_OUT
= 0mA
1.21
1.235
1.26
V
VOS
VTT
V
TT
Output Voltage Offset
I
OUT
= 0A
(Note 2)
-15
-20
0
15
20
mV
V
TT
/V
TT
Load Regulation
(Note 3)
I
OUT
= 0 to 1.5A
0.5
%
I
OUT
= 0 to -1.5A
-0.5
Z
VREF
V
REF
Output Impedance
I
REF
= -5A to +5A
5
k
Z
VDDQ
VDDQ Input Impedance
100
k
I
q
Quiescent Current
I
OUT
= 0A
(Note 4)
250
400
A
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed
test conditions.
Note 2: V
TT
offset is the voltage measurement defined as V
TT
subtracted from V
REF
.
Note 3: Load regulation is tested by using a 10ms current pulse and measuring V
TT
.
Note 4: Quiescent current defined as the current flow into AVIN.
Note 5: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at
JA
= 151 C/W
junction to ambient with no heat sink. The device in the LLP-16 must be derated at
JA
= 51 C/W junction to ambient.
Note 6: Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).
Note 7: The human body model is a 100pF capacitor discharged through a 1.5k
resistor into each pin.
LP2995
www.national.com
3
PDF 
ZIP
